From: Stephen Boyd <sboyd@kernel.org>
To: Sivaprakash Murugesan <sivaprak@codeaurora.org>,
agross@kernel.org, bjorn.andersson@linaro.org,
devicetree@vger.kernel.org, jassisinghbrar@gmail.com,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, mturquette@baylibre.com,
robh+dt@kernel.org
Subject: Re: [PATCH V3 3/8] clk: qcom: Add A53 PLL support for ipq6018 devices
Date: Thu, 14 May 2020 13:40:39 -0700 [thread overview]
Message-ID: <158948883904.215346.15910533287389644445@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <4025e5c3-b532-d235-f73b-2b86055bdde2@codeaurora.org>
Quoting Sivaprakash Murugesan (2020-04-22 03:44:33)
> On 4/22/2020 2:30 PM, Stephen Boyd wrote:
> > Quoting Sivaprakash Murugesan (2020-04-13 19:55:17)
> >> diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c
> >> index 45cfc57..a95351c 100644
> >> --- a/drivers/clk/qcom/a53-pll.c
> >> +++ b/drivers/clk/qcom/a53-pll.c
> >> @@ -57,30 +146,26 @@ static int qcom_a53pll_probe(struct platform_device *pdev)
> >> if (IS_ERR(regmap))
> >> return PTR_ERR(regmap);
> >>
> >> - pll->l_reg = 0x04;
> >> - pll->m_reg = 0x08;
> >> - pll->n_reg = 0x0c;
> >> - pll->config_reg = 0x14;
> >> - pll->mode_reg = 0x00;
> >> - pll->status_reg = 0x1c;
> >> - pll->status_bit = 16;
> >> - pll->freq_tbl = a53pll_freq;
> >> -
> >> - init.name = "a53pll";
> >> - init.parent_names = (const char *[]){ "xo" };
> >> - init.num_parents = 1;
> >> - init.ops = &clk_pll_sr2_ops;
> >> - init.flags = CLK_IS_CRITICAL;
> > Please document why a clk is critical.
> ok
> >
> >> - pll->clkr.hw.init = &init;
> >> -
> >> - ret = devm_clk_register_regmap(dev, &pll->clkr);
> >> + if (pll_data->flags & PLL_IS_ALPHA) {
> >> + struct clk_alpha_pll *alpha_pll =
> >> + pll_data->a53pll.alpha_pll.pll;
> >> + struct alpha_pll_config *alpha_pll_config =
> >> + pll_data->a53pll.alpha_pll.pll_config;
> >> +
> >> + clk_alpha_pll_configure(alpha_pll, regmap, alpha_pll_config);
> >> + clkr = &pll_data->a53pll.alpha_pll.pll->clkr;
> >> + } else {
> >> + clkr = &pll_data->a53pll.pll->clkr;
> >> + }
> > Sorry, the design is confusing.
>
> The basic idea is to add support for various PLLs available to clock the
> A53 core.
>
> if this messing up the code, can the alpha pll support be moved to a
> separate file?
>
> It would be very helpful if you provide your input on this.
Isn't the alpha PLL support already in a different file? Is it sometimes
an alpha pll and other times it is something else?
next prev parent reply other threads:[~2020-05-14 20:40 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-14 2:55 [PATCH V3 0/8] Add APSS clock controller support for IPQ6018 Sivaprakash Murugesan
2020-04-14 2:55 ` [PATCH V3 1/8] dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block Sivaprakash Murugesan
2020-04-20 20:59 ` Rob Herring
2020-05-04 6:14 ` Sivaprakash Murugesan
2020-04-14 2:55 ` [PATCH V3 2/8] dt-bindings: clock: Add YAML schemas for QCOM A53 PLL Sivaprakash Murugesan
2020-04-20 21:01 ` Rob Herring
2020-05-04 6:13 ` Sivaprakash Murugesan
2020-04-20 21:03 ` Rob Herring
2020-04-14 2:55 ` [PATCH V3 3/8] clk: qcom: Add A53 PLL support for ipq6018 devices Sivaprakash Murugesan
2020-04-22 9:00 ` Stephen Boyd
2020-04-22 10:44 ` Sivaprakash Murugesan
2020-05-14 20:40 ` Stephen Boyd [this message]
2020-05-24 9:36 ` Sivaprakash Murugesan
2020-04-14 2:55 ` [PATCH V3 4/8] clk: qcom: Add DT bindings for ipq6018 apss clock controller Sivaprakash Murugesan
2020-04-14 2:55 ` [PATCH V3 5/8] clk: qcom: Add ipq " Sivaprakash Murugesan
2020-04-22 9:04 ` Stephen Boyd
2020-05-04 6:10 ` Sivaprakash Murugesan
2020-04-14 2:55 ` [PATCH V3 6/8] dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block Sivaprakash Murugesan
2020-04-20 21:05 ` Rob Herring
2020-04-14 2:55 ` [PATCH V3 7/8] mailbox: qcom: Add ipq6018 apcs compatible Sivaprakash Murugesan
2020-04-14 2:55 ` [PATCH V3 8/8] arm64: dts: ipq6018: Add a53 pll and apcs clock Sivaprakash Murugesan
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