From: Stephen Boyd <sboyd@kernel.org>
To: Jolly Shah <jolly.shah@xilinx.com>,
arm@kernel.org, linux-clk@vger.kernel.org,
michal.simek@xilinx.com, mturquette@baylibre.com, olof@lixom.net
Cc: rajanv@xilinx.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Tejas Patel <tejas.patel@xilinx.com>,
Jolly Shah <jolly.shah@xilinx.com>
Subject: Re: [PATCH v2 2/4] drivers: clk: zynqmp: Fix divider2 calculation
Date: Tue, 26 May 2020 18:01:23 -0700 [thread overview]
Message-ID: <159054128348.88029.11223617733496629973@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <1583185843-20707-3-git-send-email-jolly.shah@xilinx.com>
Quoting Jolly Shah (2020-03-02 13:50:41)
> From: Tejas Patel <tejas.patel@xilinx.com>
>
> zynqmp_get_divider2_val() calculates, divider value of type DIV2 clock,
> considering best possible combination of DIV1 and DIV2.
>
> To find best possible values of DIV1 and DIV2, DIV1's parent rate
> should be consider and not DIV2's parent rate since it would rate of
> div1 clock. Consider a below topology,
>
> out_clk->div2_clk->div1_clk->fixed_parent
>
> where out_clk = (fixed_parent/div1_clk) / div2_clk, so parent clock
> of div1_clk (i.e. out_clk) should be divided by div1_clk and div2_clk.
>
> Existing code divides parent rate of div2_clk's clock instead of
> div1_clk's parent rate, which is wrong.
>
> Fix the same by considering div1's parent clock rate.
>
> Fixes: 4ebd92d2e228 ("clk: zynqmp: Fix divider calculation")
> Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
> ---
Applied to clk-next
next prev parent reply other threads:[~2020-05-27 1:01 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-02 21:50 [PATCH v2 0/4] drivers: clk: zynqmp: minor bux fixes for zynqmp clock driver Jolly Shah
2020-03-02 21:50 ` [PATCH v2 1/4] drivers: clk: zynqmp: Limit bestdiv with maxdiv Jolly Shah
2020-05-27 1:01 ` Stephen Boyd
2020-03-02 21:50 ` [PATCH v2 2/4] drivers: clk: zynqmp: Fix divider2 calculation Jolly Shah
2020-05-27 1:01 ` Stephen Boyd [this message]
2020-03-02 21:50 ` [PATCH v2 3/4] drivers: clk: zynqmp: Fix invalid clock name queries Jolly Shah
2020-05-27 1:01 ` Stephen Boyd
2020-03-02 21:50 ` [PATCH v2 4/4] drivers: clk: zynqmp: fix memory leak in zynqmp_register_clocks Jolly Shah
2020-05-27 1:01 ` Stephen Boyd
2020-03-23 21:15 ` [PATCH v2 0/4] drivers: clk: zynqmp: minor bux fixes for zynqmp clock driver Jolly Shah
2020-04-09 20:44 ` Jolly Shah
2020-04-21 7:50 ` Michal Simek
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