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From: Stephen Boyd <sboyd@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
	Serge Semin <Sergey.Semin@baikalelectronics.ru>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>,
	Serge Semin <fancer.lancer@gmail.com>,
	Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
	Arnd Bergmann <arnd@arndb.de>, Rob Herring <robh+dt@kernel.org>,
	linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v3 3/4] clk: Add Baikal-T1 CCU PLLs driver
Date: Sat, 30 May 2020 11:14:22 -0700	[thread overview]
Message-ID: <159086246246.69627.14574003566166284722@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20200526222056.18072-4-Sergey.Semin@baikalelectronics.ru>

Quoting Serge Semin (2020-05-26 15:20:55)
> Baikal-T1 is supposed to be supplied with a high-frequency external
> oscillator. But in order to create signals suitable for each IP-block
> embedded into the SoC the oscillator output is primarily connected to
> a set of CCU PLLs. There are five of them to create clocks for the MIPS
> P5600 cores, an embedded DDR controller, SATA, Ethernet and PCIe domains.
> The last three domains though named by the biggest system interfaces in
> fact include nearly all of the rest SoC peripherals. Each of the PLLs is
> based on True Circuits TSMC CLN28HPM IP-core with an interface wrapper
> (so called safe PLL' clocks switcher) to simplify the PLL configuration
> procedure.
> 
> This driver creates the of-based hardware clocks to use them then in
> the corresponding subsystems. In order to simplify the driver code we
> split the functionality up into the PLLs clocks operations and hardware
> clocks declaration/registration procedures.
> 
> Even though the PLLs are based on the same IP-core, they may have some
> differences. In particular, some CCU PLLs support the output clock change
> without gating them (like CPU or PCIe PLLs), while the others don't, some
> CCU PLLs are critical and aren't supposed to be gated. In order to cover
> all of these cases the hardware clocks driver is designed with an
> info-descriptor pattern. So there are special static descriptors declared
> for each PLL, which is then used to create a hardware clock with proper
> operations. Additionally debugfs-files are provided for each PLL' field
> to make sure the implemented rate-PLLs-dividers calculation algorithm is
> correct.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> 
> ---

Applied to clk-next

  reply	other threads:[~2020-05-30 18:14 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-26 22:20 [PATCH v3 0/4] clk: Add Baikal-T1 SoC Clock Control Unit support Serge Semin
2020-05-26 22:20 ` [PATCH v3 1/4] dt-bindings: clk: Add Baikal-T1 CCU PLLs binding Serge Semin
2020-05-29 17:54   ` Rob Herring
2020-05-30 18:14   ` Stephen Boyd
2020-05-26 22:20 ` [PATCH v3 2/4] dt-bindings: clk: Add Baikal-T1 CCU Dividers binding Serge Semin
2020-05-29 17:55   ` Rob Herring
2020-05-30 18:14   ` Stephen Boyd
2020-05-26 22:20 ` [PATCH v3 3/4] clk: Add Baikal-T1 CCU PLLs driver Serge Semin
2020-05-30 18:14   ` Stephen Boyd [this message]
2020-05-26 22:20 ` [PATCH v3 4/4] clk: Add Baikal-T1 CCU Dividers driver Serge Semin
2020-05-30 18:14   ` Stephen Boyd

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