From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org,
tglx@linutronix.de, bp@alien8.de, x86@kernel.org,
linux-kernel@vger.kernel.org
Cc: mark.rutland@arm.com, alexander.shishkin@linux.intel.com,
jolsa@redhat.com, namhyung@kernel.org, dave.hansen@intel.com,
yu-cheng.yu@intel.com, bigeasy@linutronix.de, gorcunov@gmail.com,
hpa@zytor.com, alexey.budankov@linux.intel.com,
eranian@google.com, ak@linux.intel.com, like.xu@linux.intel.com,
yao.jin@linux.intel.com, Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH 09/21] perf/x86: Expose CPUID enumeration bits for arch LBR
Date: Fri, 19 Jun 2020 07:03:57 -0700 [thread overview]
Message-ID: <1592575449-64278-10-git-send-email-kan.liang@linux.intel.com> (raw)
In-Reply-To: <1592575449-64278-1-git-send-email-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
The LBR capabilities of Architecture LBR are retrieved from the CPUID
enumeration once at boot time. The capabilities have to be saved for
future usage.
Several new fields in x86_pmu are added to indicate the capabilities.
The fields will be used in the following patches.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/perf_event.h | 44 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index e33d348..cbfc55b 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -689,6 +689,50 @@ struct x86_pmu {
const int *lbr_sel_map; /* lbr_select mappings */
bool lbr_double_abort; /* duplicated lbr aborts */
bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
+ bool arch_lbr; /* Arch LBR supported */
+
+ /* Arch LBR Capabilities */
+ union {
+ struct {
+ /* Supported LBR depth values */
+ unsigned int arch_lbr_depth_mask:8;
+
+ unsigned int reserved:22;
+
+ /* Deep C-state Reset */
+ unsigned int arch_lbr_deep_c_reset:1;
+
+ /* IP values contain LIP */
+ unsigned int arch_lbr_lip:1;
+ };
+ unsigned int arch_lbr_eax;
+ };
+ union {
+ struct {
+ /* CPL Filtering Supported */
+ unsigned int arch_lbr_cpl:1;
+
+ /* Branch Filtering Supported */
+ unsigned int arch_lbr_filter:1;
+
+ /* Call-stack Mode Supported */
+ unsigned int arch_lbr_call_stack:1;
+ };
+ unsigned int arch_lbr_ebx;
+ };
+ union {
+ struct {
+ /* Mispredict Bit Supported */
+ unsigned int arch_lbr_mispred:1;
+
+ /* Timed LBRs Supported */
+ unsigned int arch_lbr_timed_lbr:1;
+
+ /* Branch Type Field Supported */
+ unsigned int arch_lbr_br_type:1;
+ };
+ unsigned int arch_lbr_ecx;
+ };
void (*lbr_enable)(bool pmi);
void (*lbr_disable)(void);
--
2.7.4
next prev parent reply other threads:[~2020-06-19 14:08 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-19 14:03 [PATCH 00/21] Support Architectural LBR kan.liang
2020-06-19 14:03 ` [PATCH 01/21] x86/cpufeatures: Add Architectural LBRs feature bit kan.liang
2020-06-19 14:03 ` [PATCH 02/21] perf/x86/intel/lbr: Add pointers for LBR enable and disable kan.liang
2020-06-19 14:03 ` [PATCH 03/21] perf/x86/intel/lbr: Add pointer for LBR reset kan.liang
2020-06-19 14:03 ` [PATCH 04/21] perf/x86/intel/lbr: Add pointer for LBR read kan.liang
2020-06-19 14:03 ` [PATCH 05/21] perf/x86/intel/lbr: Add pointers for LBR save and restore kan.liang
2020-06-19 14:03 ` [PATCH 06/21] perf/x86/intel/lbr: Factor out a new struct for generic optimization kan.liang
2020-06-19 14:03 ` [PATCH 07/21] perf/x86/intel/lbr: Use dynamic data structure for task_ctx kan.liang
2020-06-19 14:03 ` [PATCH 08/21] x86/msr-index: Add bunch of MSRs for Arch LBR kan.liang
2020-06-19 19:11 ` Peter Zijlstra
2020-06-19 14:03 ` kan.liang [this message]
2020-06-19 18:31 ` [PATCH 09/21] perf/x86: Expose CPUID enumeration bits for arch LBR Peter Zijlstra
2020-06-19 14:03 ` [PATCH 10/21] perf/x86/intel: Check Arch LBR MSRs kan.liang
2020-06-19 14:03 ` [PATCH 11/21] perf/x86/intel/lbr: Support LBR_CTL kan.liang
2020-06-19 18:40 ` Peter Zijlstra
2020-06-19 19:15 ` Liang, Kan
2020-06-19 19:22 ` Peter Zijlstra
2020-06-19 14:04 ` [PATCH 12/21] perf/x86/intel/lbr: Support Architectural LBR kan.liang
2020-06-19 19:08 ` Peter Zijlstra
2020-06-19 19:40 ` Liang, Kan
2020-06-19 14:04 ` [PATCH 13/21] perf/core: Factor out functions to allocate/free the task_ctx_data kan.liang
2020-06-19 14:04 ` [PATCH 14/21] perf/core: Use kmem_cache to allocate the PMU specific data kan.liang
2020-06-19 14:04 ` [PATCH 15/21] perf/x86/intel/lbr: Create kmem_cache for the LBR context data kan.liang
2020-06-19 14:04 ` [PATCH 16/21] perf/x86: Remove task_ctx_size kan.liang
2020-06-19 14:04 ` [PATCH 17/21] x86/fpu: Use proper mask to replace full instruction mask kan.liang
2020-06-19 19:31 ` Peter Zijlstra
2020-06-22 14:52 ` Liang, Kan
2020-06-22 15:02 ` Dave Hansen
2020-06-22 17:47 ` Liang, Kan
2020-06-22 18:05 ` Dave Hansen
2020-06-22 18:46 ` Liang, Kan
2020-06-19 14:04 ` [PATCH 18/21] x86/fpu/xstate: Support dynamic supervisor feature for LBR kan.liang
2020-06-19 14:04 ` [PATCH 19/21] x86/fpu/xstate: Add helpers for LBR dynamic supervisor feature kan.liang
2020-06-19 14:04 ` [PATCH 20/21] perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switch kan.liang
2020-06-19 19:41 ` Peter Zijlstra
2020-06-19 22:28 ` Liang, Kan
2020-06-19 14:04 ` [PATCH 21/21] perf/x86/intel/lbr: Support XSAVES for arch LBR read kan.liang
2020-06-22 18:49 ` Cyrill Gorcunov
2020-06-22 19:11 ` Liang, Kan
2020-06-22 19:31 ` Cyrill Gorcunov
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