From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35861C433DF for ; Tue, 30 Jun 2020 23:46:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 196B32081A for ; Tue, 30 Jun 2020 23:46:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727115AbgF3XqD (ORCPT ); Tue, 30 Jun 2020 19:46:03 -0400 Received: from mga04.intel.com ([192.55.52.120]:13148 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726842AbgF3XpZ (ORCPT ); Tue, 30 Jun 2020 19:45:25 -0400 IronPort-SDR: eaJaHODaF8Ee9s2zi8BbmgkdomD7IXUAJ1uFLAtWb/j4YlNlDAXfEWGiw3qaeyQ130fTF+yr0f +XOElnXmW6IA== X-IronPort-AV: E=McAfee;i="6000,8403,9668"; a="143893349" X-IronPort-AV: E=Sophos;i="5.75,298,1589266800"; d="scan'208";a="143893349" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2020 16:45:19 -0700 IronPort-SDR: GeT/ckjKwMJQl1DBqGH+pOCXGqHfXhWGoz51qRDi499akJMp6d5xsgkznBDatAYIAHPfIAbq/a +xaB/oIqhxPQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,298,1589266800"; d="scan'208";a="386842563" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga001.fm.intel.com with ESMTP; 30 Jun 2020 16:44:53 -0700 From: Fenghua Yu To: "Thomas Gleixner" , "Joerg Roedel" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "H Peter Anvin" , "David Woodhouse" , "Lu Baolu" , "Felix Kuehling" , "Dave Hansen" , "Tony Luck" , "Jean-Philippe Brucker" , "Christoph Hellwig" , "Ashok Raj" , "Jacob Jun Pan" , "Dave Jiang" , "Sohil Mehta" , "Ravi V Shankar" Cc: "linux-kernel" , "x86" , iommu@lists.linux-foundation.org, "amd-gfx" , Fenghua Yu Subject: [PATCH v5 06/12] x86/msr-index: Define IA32_PASID MSR Date: Tue, 30 Jun 2020 16:44:36 -0700 Message-Id: <1593560682-40814-7-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1593560682-40814-1-git-send-email-fenghua.yu@intel.com> References: <1593560682-40814-1-git-send-email-fenghua.yu@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The IA32_PASID MSR (0xd93) contains the Process Address Space Identifier (PASID), a 20-bit value. Bit 31 must be set to indicate the value programmed in the MSR is valid. Hardware uses PASID to identify process address space and direct responses to the right address space. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Change "identify process" to "identify process address space" in the commit message (Thomas) arch/x86/include/asm/msr-index.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index e8370e64a155..e5f699ff1dd6 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -237,6 +237,9 @@ #define MSR_IA32_LASTINTFROMIP 0x000001dd #define MSR_IA32_LASTINTTOIP 0x000001de +#define MSR_IA32_PASID 0x00000d93 +#define MSR_IA32_PASID_VALID BIT_ULL(31) + /* DEBUGCTLMSR bits (others vary by model): */ #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ #define DEBUGCTLMSR_BTF_SHIFT 1 -- 2.19.1