From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70E41C433DF for ; Wed, 15 Jul 2020 11:25:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E65D2071B for ; Wed, 15 Jul 2020 11:25:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="uxP8Ndge" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730033AbgGOLZD (ORCPT ); Wed, 15 Jul 2020 07:25:03 -0400 Received: from esa4.microchip.iphmx.com ([68.232.154.123]:9354 "EHLO esa4.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729938AbgGOLZD (ORCPT ); Wed, 15 Jul 2020 07:25:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1594812302; x=1626348302; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=OiorU3mloH4us6zLoZjtYC+dFT05f/X+NWvYwynXGXI=; b=uxP8NdgeBp7ZLgsIQIsnMmjj0Ttry06Jw5UZDY0d+Yv8Ssemia9kCeTh /tezAXw1lIVi0bfpnrODfSBv44/ofVprpRtk6zEkT5s2RdbqbrIJ+qM0P E3KBrKhuwo+wCHdObzB2YkCR8oaVwIWrvB1xg4NqT2ZVzlml0UUPZc3n9 sxbBKk3PNkGtbcVN1o4OYCuJscJ7a69U2Y/rQlsrNpj9NXlk4YWSrE8lh yhd9w2uzLsTJBtzGQs/2SQxBxDwP6X3ziDobgoOGLZixUpaeMqMkTYcHj UVba/fNTcHClPztsOVM04Z9+N2aCA3S8abzJiH72X4TWlf5sXpvlD1BET g==; IronPort-SDR: t0ZuGGPZmRCG5NfXRVN+SA6Lhi25YdMegTP15Tb45+6eus82/1aeWzV3YxIqCdCs6Tz74HXtu8 hjzjw9No1F89m7fmrFmDtJ/n0ehl2wmgZcCla1H2I+iXK1xghvC90vDg2kHXyg2LsejHK1mOSw hXjIK4Hf6XP6E09xqcy+d24+Iv8rZOb4pPsvj9FlKFse3Windys6FAw6Uvr9TO7Y3glFVNuz49 NnhUIku0wuZRCGBSPAIVM3sz8n+my+ieey+1C0G5RYGbK7DRcYcI0kVdTs0AcsOlOGeRCqzpIi Va0= X-IronPort-AV: E=Sophos;i="5.75,355,1589266800"; d="scan'208";a="79986118" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 15 Jul 2020 04:24:57 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 15 Jul 2020 04:24:25 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 15 Jul 2020 04:24:22 -0700 From: Claudiu Beznea To: , , , , CC: , , , , "Claudiu Beznea" Subject: [PATCH 06/19] clk: at91: sam9x60-pll: check fcore against ranges Date: Wed, 15 Jul 2020 14:24:14 +0300 Message-ID: <1594812267-6697-7-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594812267-6697-1-git-send-email-claudiu.beznea@microchip.com> References: <1594812267-6697-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org According to datasheet the range of 600-1200MHz is for the the frequency generated by the fractional part of the PLL (namely Fcorepllck according to datasheet). With this in mind the output range of the PLL itself (fractional + div), taking into account that the diverder is 8 bits wide, is 600/256-1200Hz=2.3-1200MHz. Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver") Signed-off-by: Claudiu Beznea --- drivers/clk/at91/clk-sam9x60-pll.c | 12 +++++++++++- drivers/clk/at91/sam9x60.c | 2 +- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index dfb91c190bd1..00f2afd6e9b6 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -21,6 +21,9 @@ #define UPLL_DIV 2 #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1) +#define FCORE_MIN (600000000) +#define FCORE_MAX (1200000000) + #define PLL_MAX_ID 1 struct sam9x60_pll { @@ -169,6 +172,7 @@ static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll, unsigned long bestdiv = 0; unsigned long bestmul = 0; unsigned long bestfrac = 0; + unsigned long long fcore = 0; if (rate < characteristics->output[0].min || rate > characteristics->output[0].max) @@ -213,6 +217,11 @@ static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll, remainder = rate - tmprate; } + fcore = parent_rate * (tmpmul + 1) + + ((u64)parent_rate * tmpfrac >> 22); + if (fcore < FCORE_MIN || fcore > FCORE_MAX) + continue; + /* * Compare the remainder with the best remainder found until * now and elect a new best multiplier/divider pair if the @@ -232,7 +241,8 @@ static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll, } /* Check if bestrate is a valid output rate */ - if (bestrate < characteristics->output[0].min || + if (fcore < FCORE_MIN || fcore > FCORE_MAX || + bestrate < characteristics->output[0].min || bestrate > characteristics->output[0].max) return -ERANGE; diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index 3e20aa68259f..633891b98d43 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -22,7 +22,7 @@ static const struct clk_master_layout sam9x60_master_layout = { }; static const struct clk_range plla_outputs[] = { - { .min = 300000000, .max = 600000000 }, + { .min = 2343750, .max = 1200000000 }, }; static const struct clk_pll_characteristics plla_characteristics = { -- 2.7.4