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[110.174.173.27]) by smtp.gmail.com with ESMTPSA id v2sm1146479pje.19.2020.07.16.19.44.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 19:44:05 -0700 (PDT) Date: Fri, 17 Jul 2020 12:44:00 +1000 From: Nicholas Piggin Subject: Re: [PATCH v3 0/3] Off-load TLB invalidations to host for !GTSE To: Bharata B Rao , Qian Cai Cc: aneesh.kumar@linux.ibm.com, linux-kernel@vger.kernel.org, linux-next@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au, sfr@canb.auug.org.au References: <20200703053608.12884-1-bharata@linux.ibm.com> <20200716172713.GA4565@lca.pw> <1594950229.jn9ipe6td1.astroid@bobo.none> In-Reply-To: <1594950229.jn9ipe6td1.astroid@bobo.none> MIME-Version: 1.0 Message-Id: <1594953143.b8px5ir35m.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Excerpts from Nicholas Piggin's message of July 17, 2020 12:08 pm: > Excerpts from Qian Cai's message of July 17, 2020 3:27 am: >> On Fri, Jul 03, 2020 at 11:06:05AM +0530, Bharata B Rao wrote: >>> Hypervisor may choose not to enable Guest Translation Shootdown Enable >>> (GTSE) option for the guest. When GTSE isn't ON, the guest OS isn't >>> permitted to use instructions like tblie and tlbsync directly, but is >>> expected to make hypervisor calls to get the TLB flushed. >>>=20 >>> This series enables the TLB flush routines in the radix code to >>> off-load TLB flushing to hypervisor via the newly proposed hcall >>> H_RPT_INVALIDATE.=20 >>>=20 >>> To easily check the availability of GTSE, it is made an MMU feature. >>> The OV5 handling and H_REGISTER_PROC_TBL hcall are changed to >>> handle GTSE as an optionally available feature and to not assume GTSE >>> when radix support is available. >>>=20 >>> The actual hcall implementation for KVM isn't included in this >>> patchset and will be posted separately. >>>=20 >>> Changes in v3 >>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>> - Fixed a bug in the hcall wrapper code where we were missing setting >>> H_RPTI_TYPE_NESTED while retrying the failed flush request with >>> a full flush for the nested case. >>> - s/psize_to_h_rpti/psize_to_rpti_pgsize >>>=20 >>> v2: https://lore.kernel.org/linuxppc-dev/20200626131000.5207-1-bharata@= linux.ibm.com/T/#t >>>=20 >>> Bharata B Rao (2): >>> powerpc/mm: Enable radix GTSE only if supported. >>> powerpc/pseries: H_REGISTER_PROC_TBL should ask for GTSE only if >>> enabled >>>=20 >>> Nicholas Piggin (1): >>> powerpc/mm/book3s64/radix: Off-load TLB invalidations to host when >>> !GTSE >>=20 >> Reverting the whole series fixed random memory corruptions during boot o= n >> POWER9 PowerNV systems below. >=20 > If I s/mmu_has_feature(MMU_FTR_GTSE)/(1)/g in radix_tlb.c, then the .o > disasm is the same as reverting my patch. >=20 > Feature bits not being set right? PowerNV should be pretty simple, seems > to do the same as FTR_TYPE_RADIX. Might need this fix --- diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 9cc49f265c86..54c9bcea9d4e 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -163,7 +163,7 @@ static struct ibm_pa_feature { { .pabyte =3D 0, .pabit =3D 6, .cpu_features =3D CPU_FTR_NOEXECUTE }, { .pabyte =3D 1, .pabit =3D 2, .mmu_features =3D MMU_FTR_CI_LARGE_PAGE = }, #ifdef CONFIG_PPC_RADIX_MMU - { .pabyte =3D 40, .pabit =3D 0, .mmu_features =3D MMU_FTR_TYPE_RADIX }, + { .pabyte =3D 40, .pabit =3D 0, .mmu_features =3D (MMU_FTR_TYPE_RADIX | = MMU_FTR_GTSE) }, #endif { .pabyte =3D 1, .pabit =3D 1, .invert =3D 1, .cpu_features =3D CPU_FTR_= NODSISRALIGN }, { .pabyte =3D 5, .pabit =3D 0, .cpu_features =3D CPU_FTR_REAL_LE,