From: Yongqiang Niu <yongqiang.niu@mediatek.com>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: CK Hu <ck.hu@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
"Rob Herring" <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Mark Rutland <mark.rutland@arm.com>, <devicetree@vger.kernel.org>,
"David Airlie" <airlied@linux.ie>,
linux-kernel <linux-kernel@vger.kernel.org>,
"DRI Development" <dri-devel@lists.freedesktop.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
Daniel Vetter <daniel@ffwll.ch>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data
Date: Sat, 25 Jul 2020 11:13:08 +0800 [thread overview]
Message-ID: <1595646788.13250.9.camel@mhfsdcap03> (raw)
In-Reply-To: <CAAOTY_9jE1=ff9YU8WT7RJ4_27G+BKu335GT7_iTw1x2t0=UkA@mail.gmail.com>
On Sat, 2020-07-25 at 10:11 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
>
> Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:05寫道：
> >
> > add mmsys private data
> >
> > Feature: drm/mediatek
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> > drivers/soc/mediatek/Makefile | 1 +
> > drivers/soc/mediatek/mmsys/Makefile | 2 +
> > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++-------------------------
> > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++
> > 5 files changed, 314 insertions(+), 225 deletions(-)
> > create mode 100644 drivers/soc/mediatek/mmsys/Makefile
> > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> >
> > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> > index 2afa7b9..b37ac2c 100644
> > --- a/drivers/soc/mediatek/Makefile
> > +++ b/drivers/soc/mediatek/Makefile
> > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
> > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> > +obj-$(CONFIG_MTK_MMSYS) += mmsys/
> > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
> > new file mode 100644
> > index 0000000..33b0dab
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mmsys/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +obj-y += mt2701-mmsys.o
> > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> > new file mode 100644
> > index 0000000..b8e53b0
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> > @@ -0,0 +1,250 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +//
> > +// Copyright (c) 2020 MediaTek Inc.
> > +
> > +#include <linux/device.h>
> > +#include <linux/io.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +
> > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
> > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
> > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
> > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
> > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
> > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
> > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
> > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
> > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
> > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
> > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
> > +
> > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
> > +#define DISP_REG_CONFIG_OUT_SEL 0x04c
> > +#define DISP_REG_CONFIG_DSI_SEL 0x050
> > +#define DISP_REG_CONFIG_DPI_SEL 0x064
> > +
> > +#define OVL0_MOUT_EN_COLOR0 0x1
> > +#define OD_MOUT_EN_RDMA0 0x1
> > +#define OD1_MOUT_EN_RDMA1 BIT(16)
> > +#define UFOE_MOUT_EN_DSI0 0x1
> > +#define COLOR0_SEL_IN_OVL0 0x1
> > +#define OVL1_MOUT_EN_COLOR1 0x1
> > +#define GAMMA_MOUT_EN_RDMA1 0x1
> > +#define RDMA0_SOUT_DPI0 0x2
> > +#define RDMA0_SOUT_DPI1 0x3
> > +#define RDMA0_SOUT_DSI1 0x1
> > +#define RDMA0_SOUT_DSI2 0x4
> > +#define RDMA0_SOUT_DSI3 0x5
> > +#define RDMA1_SOUT_DPI0 0x2
> > +#define RDMA1_SOUT_DPI1 0x3
> > +#define RDMA1_SOUT_DSI1 0x1
> > +#define RDMA1_SOUT_DSI2 0x4
> > +#define RDMA1_SOUT_DSI3 0x5
> > +#define RDMA2_SOUT_DPI0 0x2
> > +#define RDMA2_SOUT_DPI1 0x3
> > +#define RDMA2_SOUT_DSI1 0x1
> > +#define RDMA2_SOUT_DSI2 0x4
> > +#define RDMA2_SOUT_DSI3 0x5
> > +#define DPI0_SEL_IN_RDMA1 0x1
> > +#define DPI0_SEL_IN_RDMA2 0x3
> > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
> > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
> > +#define DSI0_SEL_IN_RDMA1 0x1
> > +#define DSI0_SEL_IN_RDMA2 0x4
> > +#define DSI1_SEL_IN_RDMA1 0x1
> > +#define DSI1_SEL_IN_RDMA2 0x4
> > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
> > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
> > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
> > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
> > +#define COLOR1_SEL_IN_OVL1 0x1
> > +
> > +#define OVL_MOUT_EN_RDMA 0x1
> > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
> > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
> > +#define DSI_SEL_IN_BLS 0x0
> > +#define DPI_SEL_IN_BLS 0x0
> > +#define DSI_SEL_IN_RDMA 0x1
> > +
> > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > + enum mtk_ddp_comp_id next,
> > + unsigned int *addr)
> > +{
> > + unsigned int value;
> > +
> > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > + value = OVL0_MOUT_EN_COLOR0;
> > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > + value = OVL_MOUT_EN_RDMA;
> > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > + value = OD_MOUT_EN_RDMA0;
> > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> > + value = UFOE_MOUT_EN_DSI0;
> > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> > + value = OVL1_MOUT_EN_COLOR1;
> > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > + value = GAMMA_MOUT_EN_RDMA1;
> > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > + value = OD1_MOUT_EN_RDMA1;
> > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + value = RDMA0_SOUT_DPI0;
> > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + value = RDMA0_SOUT_DPI1;
> > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + value = RDMA0_SOUT_DSI1;
> > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + value = RDMA0_SOUT_DSI2;
> > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > + value = RDMA0_SOUT_DSI3;
> > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + value = RDMA1_SOUT_DSI1;
> > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + value = RDMA1_SOUT_DSI2;
> > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + value = RDMA1_SOUT_DSI3;
> > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + value = RDMA1_SOUT_DPI0;
> > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > + value = RDMA1_SOUT_DPI1;
> > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + value = RDMA2_SOUT_DPI0;
> > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + value = RDMA2_SOUT_DPI1;
> > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + value = RDMA2_SOUT_DSI1;
> > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + value = RDMA2_SOUT_DSI2;
> > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > + value = RDMA2_SOUT_DSI3;
> > + } else {
> > + value = 0;
> > + }
> > +
> > + return value;
> > +}
> > +
> > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> > + enum mtk_ddp_comp_id next,
> > + unsigned int *addr)
> > +{
> > + unsigned int value;
> > +
> > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> > + value = COLOR0_SEL_IN_OVL0;
> > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + value = DPI0_SEL_IN_RDMA1;
> > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> > + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + value = DPI1_SEL_IN_RDMA1;
> > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + value = DSI0_SEL_IN_RDMA1;
> > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > + value = DSI1_SEL_IN_RDMA1;
> > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + value = DSI2_SEL_IN_RDMA1;
> > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > + value = DSI3_SEL_IN_RDMA1;
> > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + value = DPI0_SEL_IN_RDMA2;
> > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > + *addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > + value = DPI1_SEL_IN_RDMA2;
> > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + value = DSI0_SEL_IN_RDMA2;
> > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > + value = DSI1_SEL_IN_RDMA2;
> > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + value = DSI2_SEL_IN_RDMA2;
> > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > + value = DSI3_SEL_IN_RDMA2;
> > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> > + value = COLOR1_SEL_IN_OVL1;
> > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> > + *addr = DISP_REG_CONFIG_DSI_SEL;
> > + value = DSI_SEL_IN_BLS;
> > + } else {
> > + value = 0;
> > + }
> > +
> > + return value;
> > +}
> > +
> > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> > + enum mtk_ddp_comp_id cur,
> > + enum mtk_ddp_comp_id next)
> > +{
> > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> > + config_regs + DISP_REG_CONFIG_OUT_SEL);
> > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> > + config_regs + DISP_REG_CONFIG_OUT_SEL);
> > + writel_relaxed(DSI_SEL_IN_RDMA,
> > + config_regs + DISP_REG_CONFIG_DSI_SEL);
> > + writel_relaxed(DPI_SEL_IN_BLS,
> > + config_regs + DISP_REG_CONFIG_DPI_SEL);
> > + }
> > +}
> > +
> > +static struct mtk_mmsys_conn_funcs mmsys_funcs = {
> > + .mout_en = mtk_mmsys_ddp_mout_en,
> > + .sel_in = mtk_mmsys_ddp_sel_in,
> > + .sout_sel = mtk_mmsys_ddp_sout_sel,
>
> I think you could implement these three function to be the same as the
> three of mt8183 with mt2701 version of mmsys_mout_en[],
> mmsys_sel_in[], mmsys_sout_sel[]. If you worry that you could not test
> on mt2701, we could temporarily accept this and wait for someone has
> mt2701 (or mt8173) to rewrite these three function to be the same as
> mt8183.
>
> Regards,
> Chun-Kuang.
hi Chun-Kuang.
thanks very much for your understand.
actually, the display path connection of mt2701, mt2712, mt8173, mt6779,
mt6797 are all different with each other.
there will be mtxx-mmsys.c for every SoC.
and the corresponded SoC upstream member will coding these and test it
on the SoC if it is need.
>
> > +};
> > +
next prev parent reply other threads:[~2020-07-25 3:14 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-23 2:03 [v7, PATCH 0/7] add drm support for MT8183 Yongqiang Niu
2020-07-23 2:03 ` [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h Yongqiang Niu
2020-07-23 9:34 ` Enric Balletbo Serra
2020-07-23 10:04 ` Yongqiang Niu
2020-07-23 16:21 ` Chun-Kuang Hu
2020-07-23 2:03 ` [v7, PATCH 2/7] mtk-mmsys: add mmsys private data Yongqiang Niu
2020-07-23 9:32 ` Enric Balletbo Serra
2020-07-25 3:27 ` Yongqiang Niu
2020-07-28 10:25 ` Enric Balletbo Serra
2020-07-25 2:11 ` Chun-Kuang Hu
2020-07-25 3:13 ` Yongqiang Niu [this message]
2020-07-23 2:03 ` [v7, PATCH 3/7] mtk-mmsys: add mt8183 mmsys support Yongqiang Niu
2020-07-24 13:49 ` Nicolas Boichat
2020-07-23 2:03 ` [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display Yongqiang Niu
2020-07-23 15:41 ` Matthias Brugger
2020-07-23 16:59 ` Rob Herring
2020-07-23 2:03 ` [v7, PATCH 5/7] arm64: dts: add display nodes for mt8183 Yongqiang Niu
2020-07-23 15:42 ` Matthias Brugger
2020-07-23 2:03 ` [v7, PATCH 6/7] drm/mediatek: add fifo_size into rdma private data Yongqiang Niu
2020-07-25 3:50 ` Chun-Kuang Hu
2020-07-23 2:03 ` [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 Yongqiang Niu
2020-07-23 15:40 ` Matthias Brugger
2020-07-25 3:31 ` Yongqiang Niu
2020-07-24 23:24 ` Chun-Kuang Hu
2020-07-25 3:30 ` Yongqiang Niu
2020-07-25 3:45 ` Chun-Kuang Hu
2020-07-27 7:52 ` Yongqiang Niu
2020-07-27 14:50 ` Chun-Kuang Hu
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