From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>
Cc: James Liao <jamesjj.liao@mediatek.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<srv_heupstream@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com>,
Wendell Lin <wendell.lin@mediatek.com>
Subject: [PATCH v2 0/5] Mediatek MT8192 clock support
Date: Wed, 29 Jul 2020 16:44:32 +0800 [thread overview]
Message-ID: <1596012277-8448-1-git-send-email-weiyi.lu@mediatek.com> (raw)
This series is based on v5.8-rc1
changes since v1:
- fix asymmetrical control of PLL
- have en_mask used as divider enable mask on all MediaTek SoC
Weiyi Lu (5):
dt-bindings: ARM: Mediatek: Document bindings for MT8192
clk: mediatek: Add dt-bindings for MT8192 clocks
clk: mediatek: Fix asymmetrical PLL enable and disable control
clk: mediatek: Add configurable enable control to mtk_pll_data
clk: mediatek: Add MT8192 clock support
.../arm/mediatek/mediatek,apmixedsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,audsys.txt | 1 +
.../arm/mediatek/mediatek,camsys-raw.yaml | 40 +
.../bindings/arm/mediatek/mediatek,camsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,imgsys.txt | 2 +
.../arm/mediatek/mediatek,imp_iic_wrap.yaml | 43 +
.../arm/mediatek/mediatek,infracfg.txt | 1 +
.../bindings/arm/mediatek/mediatek,ipesys.txt | 1 +
.../arm/mediatek/mediatek,mdpsys.yaml | 38 +
.../bindings/arm/mediatek/mediatek,mfgcfg.txt | 1 +
.../bindings/arm/mediatek/mediatek,mmsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,msdc.yaml | 39 +
.../arm/mediatek/mediatek,pericfg.yaml | 1 +
.../arm/mediatek/mediatek,scp-adsp.yaml | 38 +
.../arm/mediatek/mediatek,topckgen.txt | 1 +
.../arm/mediatek/mediatek,vdecsys-soc.yaml | 38 +
.../arm/mediatek/mediatek,vdecsys.txt | 1 +
.../arm/mediatek/mediatek,vencsys.txt | 1 +
drivers/clk/mediatek/Kconfig | 146 ++
drivers/clk/mediatek/Makefile | 24 +
drivers/clk/mediatek/clk-mt2701.c | 26 +-
drivers/clk/mediatek/clk-mt2712.c | 30 +-
drivers/clk/mediatek/clk-mt6765.c | 20 +-
drivers/clk/mediatek/clk-mt6779.c | 24 +-
drivers/clk/mediatek/clk-mt6797.c | 20 +-
drivers/clk/mediatek/clk-mt7622.c | 18 +-
drivers/clk/mediatek/clk-mt7629.c | 12 +-
drivers/clk/mediatek/clk-mt8173.c | 42 +-
drivers/clk/mediatek/clk-mt8183.c | 22 +-
drivers/clk/mediatek/clk-mt8192-aud.c | 150 ++
drivers/clk/mediatek/clk-mt8192-cam.c | 69 +
drivers/clk/mediatek/clk-mt8192-cam_rawa.c | 56 +
drivers/clk/mediatek/clk-mt8192-cam_rawb.c | 56 +
drivers/clk/mediatek/clk-mt8192-cam_rawc.c | 56 +
drivers/clk/mediatek/clk-mt8192-img.c | 57 +
drivers/clk/mediatek/clk-mt8192-img2.c | 59 +
.../clk/mediatek/clk-mt8192-imp_iic_wrap_c.c | 61 +
.../clk/mediatek/clk-mt8192-imp_iic_wrap_e.c | 55 +
.../clk/mediatek/clk-mt8192-imp_iic_wrap_n.c | 57 +
.../clk/mediatek/clk-mt8192-imp_iic_wrap_s.c | 59 +
.../clk/mediatek/clk-mt8192-imp_iic_wrap_w.c | 55 +
.../clk/mediatek/clk-mt8192-imp_iic_wrap_ws.c | 59 +
drivers/clk/mediatek/clk-mt8192-ipe.c | 61 +
drivers/clk/mediatek/clk-mt8192-mdp.c | 89 +
drivers/clk/mediatek/clk-mt8192-mfg.c | 54 +
drivers/clk/mediatek/clk-mt8192-mm.c | 108 ++
drivers/clk/mediatek/clk-mt8192-msdc.c | 54 +
drivers/clk/mediatek/clk-mt8192-msdc_top.c | 83 +
drivers/clk/mediatek/clk-mt8192-scp_adsp.c | 55 +
drivers/clk/mediatek/clk-mt8192-vdec.c | 81 +
drivers/clk/mediatek/clk-mt8192-vdec_soc.c | 86 +
drivers/clk/mediatek/clk-mt8192-venc.c | 57 +
drivers/clk/mediatek/clk-mt8192.c | 1549 +++++++++++++++++
drivers/clk/mediatek/clk-mtk.h | 2 +
drivers/clk/mediatek/clk-mux.h | 15 +
drivers/clk/mediatek/clk-pll.c | 20 +-
include/dt-bindings/clock/mt8192-clk.h | 593 +++++++
57 files changed, 4284 insertions(+), 105 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdpsys.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,scp-adsp.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml
create mode 100644 drivers/clk/mediatek/clk-mt8192-aud.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-cam.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawa.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawb.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawc.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-img.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-img2.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_c.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_e.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_n.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_s.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_w.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_ws.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-ipe.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-mdp.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-mfg.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-mm.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-msdc.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-msdc_top.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-scp_adsp.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-vdec.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-vdec_soc.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-venc.c
create mode 100644 drivers/clk/mediatek/clk-mt8192.c
create mode 100644 include/dt-bindings/clock/mt8192-clk.h
next reply other threads:[~2020-07-29 8:44 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-29 8:44 Weiyi Lu [this message]
2020-07-29 8:44 ` [PATCH v2 1/5] dt-bindings: ARM: Mediatek: Document bindings for MT8192 Weiyi Lu
2020-07-29 9:53 ` Enric Balletbo Serra
2020-08-11 7:01 ` Weiyi Lu
2020-07-29 8:44 ` [PATCH v2 2/5] clk: mediatek: Add dt-bindings for MT8192 clocks Weiyi Lu
2020-07-29 8:44 ` [PATCH v2 3/5] clk: mediatek: Fix asymmetrical PLL enable and disable control Weiyi Lu
2020-07-29 10:51 ` Nicolas Boichat
2020-07-29 11:02 ` Nicolas Boichat
2020-08-11 6:34 ` Weiyi Lu
2020-08-11 6:50 ` Weiyi Lu
2020-07-29 8:44 ` [PATCH v2 4/5] clk: mediatek: Add configurable enable control to mtk_pll_data Weiyi Lu
2020-07-29 10:58 ` Nicolas Boichat
2020-08-11 6:43 ` Weiyi Lu
2020-08-11 7:28 ` Nicolas Boichat
2020-08-11 9:31 ` Weiyi Lu
2020-07-29 8:44 ` [PATCH v2 5/5] clk: mediatek: Add MT8192 clock support Weiyi Lu
2020-07-29 9:32 ` Enric Balletbo Serra
2020-08-11 7:03 ` Weiyi Lu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1596012277-8448-1-git-send-email-weiyi.lu@mediatek.com \
--to=weiyi.lu@mediatek.com \
--cc=drinkcat@chromium.org \
--cc=jamesjj.liao@mediatek.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=srv_heupstream@mediatek.com \
--cc=wendell.lin@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).