* [PATCH v2 0/3] perf/x86/rapl: Add Intel SapphireRapids support
@ 2020-08-11 15:31 Zhang Rui
2020-08-11 15:31 ` [PATCH v2 1/3] perf/x86/rapl: Fix missing psys sysfs attributes Zhang Rui
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Zhang Rui @ 2020-08-11 15:31 UTC (permalink / raw)
To: peterz, mingo, acme
Cc: linux-pm, mark.rutland, alexander.shishkin, jolsa, namhyung,
linux-kernel, kan.liang, len.brown, rafael
Hi, all,
This patch set adds rapl perf event support for Intel SapphireRapids
platform.
Patch 1/3 fixes a regression that Psys RAPL Domain sysfs I/F is missing.
Patch 2/3 introduces support for different energy unit quirks.
Patch 3/3 introduces support for Intel SapphireRapids platform, which has
fixed energy units for DRAM RAPL Domain and Psys RAPL Domain.
Any feedbacks are appreciated.
thanks,
rui
v1..v2:
- add ACK from Jiri Olsa.
- update patch 3/3 to solve a conflict introduced in the merge window.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 1/3] perf/x86/rapl: Fix missing psys sysfs attributes
2020-08-11 15:31 [PATCH v2 0/3] perf/x86/rapl: Add Intel SapphireRapids support Zhang Rui
@ 2020-08-11 15:31 ` Zhang Rui
2020-08-14 15:23 ` [tip: perf/urgent] " tip-bot2 for Zhang Rui
2020-08-11 15:31 ` [PATCH v2 2/3] perf/x86/rapl: Support multiple rapl unit quirks Zhang Rui
2020-08-11 15:31 ` [PATCH v2 3/3] perf/x86/rapl: Add support for Intel SPR platform Zhang Rui
2 siblings, 1 reply; 10+ messages in thread
From: Zhang Rui @ 2020-08-11 15:31 UTC (permalink / raw)
To: peterz, mingo, acme
Cc: linux-pm, mark.rutland, alexander.shishkin, jolsa, namhyung,
linux-kernel, kan.liang, len.brown, rafael
This fixes a problem introduced by
commit 5fb5273a905c ("perf/x86/rapl: Use new MSR detection interface")
that perf event sysfs attributes for psys RAPL domain are missing.
Fixes: 5fb5273a905c ("perf/x86/rapl: Use new MSR detection interface")
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Reviewed-by: Len Brown <len.brown@intel.com>
Acked-by: Jiri Olsa <jolsa@redhat.com>
---
arch/x86/events/rapl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index 68b38820b10e..e9723833551f 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -665,7 +665,7 @@ static const struct attribute_group *rapl_attr_update[] = {
&rapl_events_pkg_group,
&rapl_events_ram_group,
&rapl_events_gpu_group,
- &rapl_events_gpu_group,
+ &rapl_events_psys_group,
NULL,
};
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 2/3] perf/x86/rapl: Support multiple rapl unit quirks
2020-08-11 15:31 [PATCH v2 0/3] perf/x86/rapl: Add Intel SapphireRapids support Zhang Rui
2020-08-11 15:31 ` [PATCH v2 1/3] perf/x86/rapl: Fix missing psys sysfs attributes Zhang Rui
@ 2020-08-11 15:31 ` Zhang Rui
2020-08-11 18:19 ` Joe Perches
2020-08-14 15:23 ` [tip: perf/urgent] perf/x86/rapl: Support multiple RAPL " tip-bot2 for Zhang Rui
2020-08-11 15:31 ` [PATCH v2 3/3] perf/x86/rapl: Add support for Intel SPR platform Zhang Rui
2 siblings, 2 replies; 10+ messages in thread
From: Zhang Rui @ 2020-08-11 15:31 UTC (permalink / raw)
To: peterz, mingo, acme
Cc: linux-pm, mark.rutland, alexander.shishkin, jolsa, namhyung,
linux-kernel, kan.liang, len.brown, rafael
There will be more platforms with different fixed energy units.
Enhance the code to support different rapl unit quirks for different
platforms.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Reviewed-by: Len Brown <len.brown@intel.com>
---
arch/x86/events/rapl.c | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index e9723833551f..d0002eb971b7 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -130,11 +130,16 @@ struct rapl_pmus {
struct rapl_pmu *pmus[];
};
+enum rapl_unit_quirk {
+ RAPL_UNIT_QUIRK_NONE,
+ RAPL_UNIT_QUIRK_INTEL_HSW,
+};
+
struct rapl_model {
struct perf_msr *rapl_msrs;
unsigned long events;
unsigned int msr_power_unit;
- bool apply_quirk;
+ enum rapl_unit_quirk unit_quirk;
};
/* 1/2^hw_unit Joule */
@@ -612,14 +617,20 @@ static int rapl_check_hw_unit(struct rapl_model *rm)
for (i = 0; i < NR_RAPL_DOMAINS; i++)
rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL;
+ switch (rm->unit_quirk) {
/*
* DRAM domain on HSW server and KNL has fixed energy unit which can be
* different than the unit from power unit MSR. See
* "Intel Xeon Processor E5-1600 and E5-2600 v3 Product Families, V2
* of 2. Datasheet, September 2014, Reference Number: 330784-001 "
*/
- if (rm->apply_quirk)
+ case RAPL_UNIT_QUIRK_INTEL_HSW:
rapl_hw_unit[PERF_RAPL_RAM] = 16;
+ break;
+ default:
+ break;
+ }
+
/*
* Calculate the timer rate:
@@ -698,7 +709,6 @@ static struct rapl_model model_snb = {
.events = BIT(PERF_RAPL_PP0) |
BIT(PERF_RAPL_PKG) |
BIT(PERF_RAPL_PP1),
- .apply_quirk = false,
.msr_power_unit = MSR_RAPL_POWER_UNIT,
.rapl_msrs = intel_rapl_msrs,
};
@@ -707,7 +717,6 @@ static struct rapl_model model_snbep = {
.events = BIT(PERF_RAPL_PP0) |
BIT(PERF_RAPL_PKG) |
BIT(PERF_RAPL_RAM),
- .apply_quirk = false,
.msr_power_unit = MSR_RAPL_POWER_UNIT,
.rapl_msrs = intel_rapl_msrs,
};
@@ -717,7 +726,6 @@ static struct rapl_model model_hsw = {
BIT(PERF_RAPL_PKG) |
BIT(PERF_RAPL_RAM) |
BIT(PERF_RAPL_PP1),
- .apply_quirk = false,
.msr_power_unit = MSR_RAPL_POWER_UNIT,
.rapl_msrs = intel_rapl_msrs,
};
@@ -726,7 +734,7 @@ static struct rapl_model model_hsx = {
.events = BIT(PERF_RAPL_PP0) |
BIT(PERF_RAPL_PKG) |
BIT(PERF_RAPL_RAM),
- .apply_quirk = true,
+ .unit_quirk = RAPL_UNIT_QUIRK_INTEL_HSW,
.msr_power_unit = MSR_RAPL_POWER_UNIT,
.rapl_msrs = intel_rapl_msrs,
};
@@ -734,7 +742,7 @@ static struct rapl_model model_hsx = {
static struct rapl_model model_knl = {
.events = BIT(PERF_RAPL_PKG) |
BIT(PERF_RAPL_RAM),
- .apply_quirk = true,
+ .unit_quirk = RAPL_UNIT_QUIRK_INTEL_HSW,
.msr_power_unit = MSR_RAPL_POWER_UNIT,
.rapl_msrs = intel_rapl_msrs,
};
@@ -745,14 +753,12 @@ static struct rapl_model model_skl = {
BIT(PERF_RAPL_RAM) |
BIT(PERF_RAPL_PP1) |
BIT(PERF_RAPL_PSYS),
- .apply_quirk = false,
.msr_power_unit = MSR_RAPL_POWER_UNIT,
.rapl_msrs = intel_rapl_msrs,
};
static struct rapl_model model_amd_fam17h = {
.events = BIT(PERF_RAPL_PKG),
- .apply_quirk = false,
.msr_power_unit = MSR_AMD_RAPL_POWER_UNIT,
.rapl_msrs = amd_rapl_msrs,
};
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 3/3] perf/x86/rapl: Add support for Intel SPR platform
2020-08-11 15:31 [PATCH v2 0/3] perf/x86/rapl: Add Intel SapphireRapids support Zhang Rui
2020-08-11 15:31 ` [PATCH v2 1/3] perf/x86/rapl: Fix missing psys sysfs attributes Zhang Rui
2020-08-11 15:31 ` [PATCH v2 2/3] perf/x86/rapl: Support multiple rapl unit quirks Zhang Rui
@ 2020-08-11 15:31 ` Zhang Rui
2020-08-14 15:23 ` [tip: perf/urgent] " tip-bot2 for Zhang Rui
2 siblings, 1 reply; 10+ messages in thread
From: Zhang Rui @ 2020-08-11 15:31 UTC (permalink / raw)
To: peterz, mingo, acme
Cc: linux-pm, mark.rutland, alexander.shishkin, jolsa, namhyung,
linux-kernel, kan.liang, len.brown, rafael
Intel SPR platform uses fixed 16 bit energy unit for DRAM RAPL domain,
and fixed 0 bit energy unit for Psys RAPL domain.
After this, on SPR platform the energy counters appear in perf list.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Acked-by: Len Brown <len.brown@intel.com>
---
arch/x86/events/rapl.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index d0002eb971b7..67b411f7e8c4 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -133,6 +133,7 @@ struct rapl_pmus {
enum rapl_unit_quirk {
RAPL_UNIT_QUIRK_NONE,
RAPL_UNIT_QUIRK_INTEL_HSW,
+ RAPL_UNIT_QUIRK_INTEL_SPR,
};
struct rapl_model {
@@ -627,6 +628,14 @@ static int rapl_check_hw_unit(struct rapl_model *rm)
case RAPL_UNIT_QUIRK_INTEL_HSW:
rapl_hw_unit[PERF_RAPL_RAM] = 16;
break;
+ /*
+ * SPR shares the same DRAM domain energy unit as HSW, plus it
+ * also has a fixed energy unit for Psys domain.
+ */
+ case RAPL_UNIT_QUIRK_INTEL_SPR:
+ rapl_hw_unit[PERF_RAPL_RAM] = 16;
+ rapl_hw_unit[PERF_RAPL_PSYS] = 0;
+ break;
default:
break;
}
@@ -757,6 +766,16 @@ static struct rapl_model model_skl = {
.rapl_msrs = intel_rapl_msrs,
};
+static struct rapl_model model_spr = {
+ .events = BIT(PERF_RAPL_PP0) |
+ BIT(PERF_RAPL_PKG) |
+ BIT(PERF_RAPL_RAM) |
+ BIT(PERF_RAPL_PSYS),
+ .unit_quirk = RAPL_UNIT_QUIRK_INTEL_SPR,
+ .msr_power_unit = MSR_RAPL_POWER_UNIT,
+ .rapl_msrs = intel_rapl_msrs,
+};
+
static struct rapl_model model_amd_fam17h = {
.events = BIT(PERF_RAPL_PKG),
.msr_power_unit = MSR_AMD_RAPL_POWER_UNIT,
@@ -793,6 +812,7 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &model_hsx),
X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &model_skl),
X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &model_skl),
+ X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &model_spr),
X86_MATCH_VENDOR_FAM(AMD, 0x17, &model_amd_fam17h),
X86_MATCH_VENDOR_FAM(HYGON, 0x18, &model_amd_fam17h),
{},
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] perf/x86/rapl: Support multiple rapl unit quirks
2020-08-11 15:31 ` [PATCH v2 2/3] perf/x86/rapl: Support multiple rapl unit quirks Zhang Rui
@ 2020-08-11 18:19 ` Joe Perches
2020-08-12 3:29 ` Zhang Rui
2020-08-14 15:23 ` [tip: perf/urgent] perf/x86/rapl: Support multiple RAPL " tip-bot2 for Zhang Rui
1 sibling, 1 reply; 10+ messages in thread
From: Joe Perches @ 2020-08-11 18:19 UTC (permalink / raw)
To: Zhang Rui, peterz, mingo, acme
Cc: linux-pm, mark.rutland, alexander.shishkin, jolsa, namhyung,
linux-kernel, kan.liang, len.brown, rafael
On Tue, 2020-08-11 at 23:31 +0800, Zhang Rui wrote:
> There will be more platforms with different fixed energy units.
> Enhance the code to support different rapl unit quirks for different
> platforms.
This seems like one quirk per platform.
Should multiple quirks on individual platforms be supported?
> diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
[]
> @@ -130,11 +130,16 @@ struct rapl_pmus {
> struct rapl_pmu *pmus[];
> };
>
> +enum rapl_unit_quirk {
> + RAPL_UNIT_QUIRK_NONE,
> + RAPL_UNIT_QUIRK_INTEL_HSW,
> +};
> +
> struct rapl_model {
> struct perf_msr *rapl_msrs;
> unsigned long events;
> unsigned int msr_power_unit;
> - bool apply_quirk;
> + enum rapl_unit_quirk unit_quirk;
> };
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] perf/x86/rapl: Support multiple rapl unit quirks
2020-08-11 18:19 ` Joe Perches
@ 2020-08-12 3:29 ` Zhang Rui
2020-08-12 3:51 ` Joe Perches
0 siblings, 1 reply; 10+ messages in thread
From: Zhang Rui @ 2020-08-12 3:29 UTC (permalink / raw)
To: Joe Perches, peterz, mingo, acme
Cc: linux-pm, mark.rutland, alexander.shishkin, jolsa, namhyung,
linux-kernel, kan.liang, len.brown, rafael
Hi,
Thanks for reviewing.
On Tue, 2020-08-11 at 11:19 -0700, Joe Perches wrote:
> On Tue, 2020-08-11 at 23:31 +0800, Zhang Rui wrote:
> > There will be more platforms with different fixed energy units.
> > Enhance the code to support different rapl unit quirks for
> > different
> > platforms.
>
> This seems like one quirk per platform.
>
> Should multiple quirks on individual platforms be supported?
>
enum rapl_unit_quirk is just used as a flag.
multiple quirks can be deployed with the same flag, just like what I
did in patch 3/3.
Also different platforms can either have different flags or share the
same flag.
thanks,
rui
> > diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
>
> []
> > @@ -130,11 +130,16 @@ struct rapl_pmus {
> > struct rapl_pmu *pmus[];
> > };
> >
> > +enum rapl_unit_quirk {
> > + RAPL_UNIT_QUIRK_NONE,
> > + RAPL_UNIT_QUIRK_INTEL_HSW,
> > +};
> > +
> > struct rapl_model {
> > struct perf_msr *rapl_msrs;
> > unsigned long events;
> > unsigned int msr_power_unit;
> > - bool apply_quirk;
> > + enum rapl_unit_quirk unit_quirk;
> > };
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] perf/x86/rapl: Support multiple rapl unit quirks
2020-08-12 3:29 ` Zhang Rui
@ 2020-08-12 3:51 ` Joe Perches
0 siblings, 0 replies; 10+ messages in thread
From: Joe Perches @ 2020-08-12 3:51 UTC (permalink / raw)
To: Zhang Rui, peterz, mingo, acme
Cc: linux-pm, mark.rutland, alexander.shishkin, jolsa, namhyung,
linux-kernel, kan.liang, len.brown, rafael
On Wed, 2020-08-12 at 11:29 +0800, Zhang Rui wrote:
> Hi,
>
> Thanks for reviewing.
>
> On Tue, 2020-08-11 at 11:19 -0700, Joe Perches wrote:
> > On Tue, 2020-08-11 at 23:31 +0800, Zhang Rui wrote:
> > > There will be more platforms with different fixed energy units.
> > > Enhance the code to support different rapl unit quirks for
> > > different
> > > platforms.
> >
> > This seems like one quirk per platform.
> >
> > Should multiple quirks on individual platforms be supported?
> >
> enum rapl_unit_quirk is just used as a flag.
> multiple quirks can be deployed with the same flag, just like what I
> did in patch 3/3.
> Also different platforms can either have different flags or share the
> same flag.
Sure, but it does lead to possible code duplication in the quirks
as enums can not be combined like bit flags.
No worries, your code, your choice...
^ permalink raw reply [flat|nested] 10+ messages in thread
* [tip: perf/urgent] perf/x86/rapl: Add support for Intel SPR platform
2020-08-11 15:31 ` [PATCH v2 3/3] perf/x86/rapl: Add support for Intel SPR platform Zhang Rui
@ 2020-08-14 15:23 ` tip-bot2 for Zhang Rui
0 siblings, 0 replies; 10+ messages in thread
From: tip-bot2 for Zhang Rui @ 2020-08-14 15:23 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Zhang Rui, Ingo Molnar, Kan Liang, Len Brown, x86, LKML
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: bcfd218b66790243ef303c1b35ce59f786ded225
Gitweb: https://git.kernel.org/tip/bcfd218b66790243ef303c1b35ce59f786ded225
Author: Zhang Rui <rui.zhang@intel.com>
AuthorDate: Tue, 11 Aug 2020 23:31:49 +08:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Fri, 14 Aug 2020 12:35:12 +02:00
perf/x86/rapl: Add support for Intel SPR platform
Intel SPR platform uses fixed 16 bit energy unit for DRAM RAPL domain,
and fixed 0 bit energy unit for Psys RAPL domain.
After this, on SPR platform the energy counters appear in perf list.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Acked-by: Len Brown <len.brown@intel.com>
Link: https://lore.kernel.org/r/20200811153149.12242-4-rui.zhang@intel.com
---
arch/x86/events/rapl.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index d0002eb..67b411f 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -133,6 +133,7 @@ struct rapl_pmus {
enum rapl_unit_quirk {
RAPL_UNIT_QUIRK_NONE,
RAPL_UNIT_QUIRK_INTEL_HSW,
+ RAPL_UNIT_QUIRK_INTEL_SPR,
};
struct rapl_model {
@@ -627,6 +628,14 @@ static int rapl_check_hw_unit(struct rapl_model *rm)
case RAPL_UNIT_QUIRK_INTEL_HSW:
rapl_hw_unit[PERF_RAPL_RAM] = 16;
break;
+ /*
+ * SPR shares the same DRAM domain energy unit as HSW, plus it
+ * also has a fixed energy unit for Psys domain.
+ */
+ case RAPL_UNIT_QUIRK_INTEL_SPR:
+ rapl_hw_unit[PERF_RAPL_RAM] = 16;
+ rapl_hw_unit[PERF_RAPL_PSYS] = 0;
+ break;
default:
break;
}
@@ -757,6 +766,16 @@ static struct rapl_model model_skl = {
.rapl_msrs = intel_rapl_msrs,
};
+static struct rapl_model model_spr = {
+ .events = BIT(PERF_RAPL_PP0) |
+ BIT(PERF_RAPL_PKG) |
+ BIT(PERF_RAPL_RAM) |
+ BIT(PERF_RAPL_PSYS),
+ .unit_quirk = RAPL_UNIT_QUIRK_INTEL_SPR,
+ .msr_power_unit = MSR_RAPL_POWER_UNIT,
+ .rapl_msrs = intel_rapl_msrs,
+};
+
static struct rapl_model model_amd_fam17h = {
.events = BIT(PERF_RAPL_PKG),
.msr_power_unit = MSR_AMD_RAPL_POWER_UNIT,
@@ -793,6 +812,7 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &model_hsx),
X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &model_skl),
X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &model_skl),
+ X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &model_spr),
X86_MATCH_VENDOR_FAM(AMD, 0x17, &model_amd_fam17h),
X86_MATCH_VENDOR_FAM(HYGON, 0x18, &model_amd_fam17h),
{},
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [tip: perf/urgent] perf/x86/rapl: Support multiple RAPL unit quirks
2020-08-11 15:31 ` [PATCH v2 2/3] perf/x86/rapl: Support multiple rapl unit quirks Zhang Rui
2020-08-11 18:19 ` Joe Perches
@ 2020-08-14 15:23 ` tip-bot2 for Zhang Rui
1 sibling, 0 replies; 10+ messages in thread
From: tip-bot2 for Zhang Rui @ 2020-08-14 15:23 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Zhang Rui, Ingo Molnar, Kan Liang, Len Brown, x86, LKML
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 74f41adab0f4a61857833e1b6fa8e9ad12c251b6
Gitweb: https://git.kernel.org/tip/74f41adab0f4a61857833e1b6fa8e9ad12c251b6
Author: Zhang Rui <rui.zhang@intel.com>
AuthorDate: Tue, 11 Aug 2020 23:31:48 +08:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Fri, 14 Aug 2020 12:35:12 +02:00
perf/x86/rapl: Support multiple RAPL unit quirks
There will be more platforms with different fixed energy units.
Enhance the code to support different RAPL unit quirks for different
platforms.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Reviewed-by: Len Brown <len.brown@intel.com>
Link: https://lore.kernel.org/r/20200811153149.12242-3-rui.zhang@intel.com
---
arch/x86/events/rapl.c | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index e972383..d0002eb 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -130,11 +130,16 @@ struct rapl_pmus {
struct rapl_pmu *pmus[];
};
+enum rapl_unit_quirk {
+ RAPL_UNIT_QUIRK_NONE,
+ RAPL_UNIT_QUIRK_INTEL_HSW,
+};
+
struct rapl_model {
struct perf_msr *rapl_msrs;
unsigned long events;
unsigned int msr_power_unit;
- bool apply_quirk;
+ enum rapl_unit_quirk unit_quirk;
};
/* 1/2^hw_unit Joule */
@@ -612,14 +617,20 @@ static int rapl_check_hw_unit(struct rapl_model *rm)
for (i = 0; i < NR_RAPL_DOMAINS; i++)
rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL;
+ switch (rm->unit_quirk) {
/*
* DRAM domain on HSW server and KNL has fixed energy unit which can be
* different than the unit from power unit MSR. See
* "Intel Xeon Processor E5-1600 and E5-2600 v3 Product Families, V2
* of 2. Datasheet, September 2014, Reference Number: 330784-001 "
*/
- if (rm->apply_quirk)
+ case RAPL_UNIT_QUIRK_INTEL_HSW:
rapl_hw_unit[PERF_RAPL_RAM] = 16;
+ break;
+ default:
+ break;
+ }
+
/*
* Calculate the timer rate:
@@ -698,7 +709,6 @@ static struct rapl_model model_snb = {
.events = BIT(PERF_RAPL_PP0) |
BIT(PERF_RAPL_PKG) |
BIT(PERF_RAPL_PP1),
- .apply_quirk = false,
.msr_power_unit = MSR_RAPL_POWER_UNIT,
.rapl_msrs = intel_rapl_msrs,
};
@@ -707,7 +717,6 @@ static struct rapl_model model_snbep = {
.events = BIT(PERF_RAPL_PP0) |
BIT(PERF_RAPL_PKG) |
BIT(PERF_RAPL_RAM),
- .apply_quirk = false,
.msr_power_unit = MSR_RAPL_POWER_UNIT,
.rapl_msrs = intel_rapl_msrs,
};
@@ -717,7 +726,6 @@ static struct rapl_model model_hsw = {
BIT(PERF_RAPL_PKG) |
BIT(PERF_RAPL_RAM) |
BIT(PERF_RAPL_PP1),
- .apply_quirk = false,
.msr_power_unit = MSR_RAPL_POWER_UNIT,
.rapl_msrs = intel_rapl_msrs,
};
@@ -726,7 +734,7 @@ static struct rapl_model model_hsx = {
.events = BIT(PERF_RAPL_PP0) |
BIT(PERF_RAPL_PKG) |
BIT(PERF_RAPL_RAM),
- .apply_quirk = true,
+ .unit_quirk = RAPL_UNIT_QUIRK_INTEL_HSW,
.msr_power_unit = MSR_RAPL_POWER_UNIT,
.rapl_msrs = intel_rapl_msrs,
};
@@ -734,7 +742,7 @@ static struct rapl_model model_hsx = {
static struct rapl_model model_knl = {
.events = BIT(PERF_RAPL_PKG) |
BIT(PERF_RAPL_RAM),
- .apply_quirk = true,
+ .unit_quirk = RAPL_UNIT_QUIRK_INTEL_HSW,
.msr_power_unit = MSR_RAPL_POWER_UNIT,
.rapl_msrs = intel_rapl_msrs,
};
@@ -745,14 +753,12 @@ static struct rapl_model model_skl = {
BIT(PERF_RAPL_RAM) |
BIT(PERF_RAPL_PP1) |
BIT(PERF_RAPL_PSYS),
- .apply_quirk = false,
.msr_power_unit = MSR_RAPL_POWER_UNIT,
.rapl_msrs = intel_rapl_msrs,
};
static struct rapl_model model_amd_fam17h = {
.events = BIT(PERF_RAPL_PKG),
- .apply_quirk = false,
.msr_power_unit = MSR_AMD_RAPL_POWER_UNIT,
.rapl_msrs = amd_rapl_msrs,
};
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [tip: perf/urgent] perf/x86/rapl: Fix missing psys sysfs attributes
2020-08-11 15:31 ` [PATCH v2 1/3] perf/x86/rapl: Fix missing psys sysfs attributes Zhang Rui
@ 2020-08-14 15:23 ` tip-bot2 for Zhang Rui
0 siblings, 0 replies; 10+ messages in thread
From: tip-bot2 for Zhang Rui @ 2020-08-14 15:23 UTC (permalink / raw)
To: linux-tip-commits
Cc: Zhang Rui, Ingo Molnar, Kan Liang, Len Brown, Jiri Olsa, x86, LKML
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 4bb5fcb97a5df0bbc0a27e0252b1e7ce140a8431
Gitweb: https://git.kernel.org/tip/4bb5fcb97a5df0bbc0a27e0252b1e7ce140a8431
Author: Zhang Rui <rui.zhang@intel.com>
AuthorDate: Tue, 11 Aug 2020 23:31:47 +08:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Fri, 14 Aug 2020 12:35:11 +02:00
perf/x86/rapl: Fix missing psys sysfs attributes
This fixes a problem introduced by commit:
5fb5273a905c ("perf/x86/rapl: Use new MSR detection interface")
that perf event sysfs attributes for psys RAPL domain are missing.
Fixes: 5fb5273a905c ("perf/x86/rapl: Use new MSR detection interface")
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Reviewed-by: Len Brown <len.brown@intel.com>
Acked-by: Jiri Olsa <jolsa@redhat.com>
Link: https://lore.kernel.org/r/20200811153149.12242-2-rui.zhang@intel.com
---
arch/x86/events/rapl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index 68b3882..e972383 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -665,7 +665,7 @@ static const struct attribute_group *rapl_attr_update[] = {
&rapl_events_pkg_group,
&rapl_events_ram_group,
&rapl_events_gpu_group,
- &rapl_events_gpu_group,
+ &rapl_events_psys_group,
NULL,
};
^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-08-14 15:24 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-11 15:31 [PATCH v2 0/3] perf/x86/rapl: Add Intel SapphireRapids support Zhang Rui
2020-08-11 15:31 ` [PATCH v2 1/3] perf/x86/rapl: Fix missing psys sysfs attributes Zhang Rui
2020-08-14 15:23 ` [tip: perf/urgent] " tip-bot2 for Zhang Rui
2020-08-11 15:31 ` [PATCH v2 2/3] perf/x86/rapl: Support multiple rapl unit quirks Zhang Rui
2020-08-11 18:19 ` Joe Perches
2020-08-12 3:29 ` Zhang Rui
2020-08-12 3:51 ` Joe Perches
2020-08-14 15:23 ` [tip: perf/urgent] perf/x86/rapl: Support multiple RAPL " tip-bot2 for Zhang Rui
2020-08-11 15:31 ` [PATCH v2 3/3] perf/x86/rapl: Add support for Intel SPR platform Zhang Rui
2020-08-14 15:23 ` [tip: perf/urgent] " tip-bot2 for Zhang Rui
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