linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@redhat.com, linux-kernel@vger.kernel.org
Cc: bhelgaas@google.com, eranian@google.com, ak@linux.intel.com,
	Kan Liang <kan.liang@linux.intel.com>
Subject: [RESEND PATCH V2 0/6] Support PCIe3 uncore PMU on Snow Ridge
Date: Mon, 14 Sep 2020 07:34:14 -0700	[thread overview]
Message-ID: <1600094060-82746-1-git-send-email-kan.liang@linux.intel.com> (raw)

From: Kan Liang <kan.liang@linux.intel.com>

Changes since V1:
- Drop the platform device solution
- A new uncore PCI sub driver solution is introduced which searches
  the PCIe Root Port device via pci_get_device() and id table.
  Register a PCI bus notifier for the remove notification. Once the
  device is removed, the uncore driver can be notified to unregister
  the corresponding PMU.
- Modify the parameters of uncore_pci_pmu_unregister() function.

The Snow Ridge integrated PCIe3 uncore performance monitoring unit (PMU)
can be used to collect the performance data, e.g., the utilization
between the PCIe devices and the components (in M2IOSF) which are
responsible for translating and managing the requests to/from the
device. The performance data is very useful for analyzing the
performance of the PCIe devices.

The PCIe3 uncore PMU was once supported in the Linux kernel, but it was
removed by the commit 2167f1625c2f ("perf/x86/intel/uncore: Remove
PCIe3 unit for SNR") due to the conflict between the PCIe Root Port
driver and the perf uncore driver. The counters of the PCIe3 uncore PMU
are located in the configuration space of the PCIe Root Port device,
which already has a bonded driver portdrv_pci. One device can only have
one bonded driver. The uncore driver is always failed to be loaded.

To re-enable the PCIe3 uncore PMU support in the uncore driver, a new
solution should be introduced, which has to meet the requirements as
below:
- must have a reliable way to find the PCIe Root Port device from the
  uncore driver;
- must be able to access the uncore counters of the PCIe Root Port
  device from the uncore driver;
- must support hotplug. When the PCIe Root Port device is removed, the
  uncore driver has to be notified and unregisters the PCIe3 uncore
  PMU.

In the v1 patch set, a new platform device solution is implemented to
address the issue, but it's rejected.
https://lkml.kernel.org/r/20200708183034.GA466341@bjorn-Precision-5520

A new uncore PCI sub driver solution is introduced from the V2 patch
set, which:
- searches the PCIe Root Port device via pci_get_device() and id table.
  The matched pci_dev can be used to register a PMU for accessing the
  counters in the PCIe Root Port device.
- register a PCI bus notifier. Once the device is removed, the uncore
  driver can be notified to unregister the corresponding PMU.

Kan Liang (6):
  perf/x86/intel/uncore: Factor out uncore_pci_get_dev_die_info()
  perf/x86/intel/uncore: Factor out uncore_pci_find_dev_pmu()
  perf/x86/intel/uncore: Factor out uncore_pci_pmu_register()
  perf/x86/intel/uncore: Factor out uncore_pci_pmu_unregister()
  perf/x86/intel/uncore: Generic support for the PCI sub driver
  perf/x86/intel/uncore: Support PCIe3 unit on Snow Ridge

 arch/x86/events/intel/uncore.c       | 273 +++++++++++++++++++++++++++--------
 arch/x86/events/intel/uncore.h       |   1 +
 arch/x86/events/intel/uncore_snbep.c |  53 +++++++
 3 files changed, 265 insertions(+), 62 deletions(-)

-- 
2.7.4


             reply	other threads:[~2020-09-14 14:47 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-14 14:34 kan.liang [this message]
2020-09-14 14:34 ` [RESEND PATCH V2 1/6] perf/x86/intel/uncore: Factor out uncore_pci_get_dev_die_info() kan.liang
2020-09-25 12:23   ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-09-14 14:34 ` [RESEND PATCH V2 2/6] perf/x86/intel/uncore: Factor out uncore_pci_find_dev_pmu() kan.liang
2020-09-25 12:23   ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-09-14 14:34 ` [RESEND PATCH V2 3/6] perf/x86/intel/uncore: Factor out uncore_pci_pmu_register() kan.liang
2020-09-25 12:23   ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-09-14 14:34 ` [RESEND PATCH V2 4/6] perf/x86/intel/uncore: Factor out uncore_pci_pmu_unregister() kan.liang
2020-09-25 12:23   ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-09-14 14:34 ` [RESEND PATCH V2 5/6] perf/x86/intel/uncore: Generic support for the PCI sub driver kan.liang
2020-09-21 22:19   ` Bjorn Helgaas
2020-09-22 13:05     ` Liang, Kan
2020-09-25 12:23   ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-09-14 14:34 ` [RESEND PATCH V2 6/6] perf/x86/intel/uncore: Support PCIe3 unit on Snow Ridge kan.liang
2020-09-25 12:23   ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-09-21 15:06 ` [RESEND PATCH V2 0/6] Support PCIe3 uncore PMU " peterz
2020-09-21 22:19   ` Bjorn Helgaas
2020-09-24 11:08     ` Peter Zijlstra

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1600094060-82746-1-git-send-email-kan.liang@linux.intel.com \
    --to=kan.liang@linux.intel.com \
    --cc=ak@linux.intel.com \
    --cc=bhelgaas@google.com \
    --cc=eranian@google.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mingo@redhat.com \
    --cc=peterz@infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).