From: Hector Yuan <hector.yuan@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-pm@vger.kernel.org>, <devicetree@vger.kernel.org>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
"Viresh Kumar" <viresh.kumar@linaro.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <wsd_upstream@mediatek.com>
Subject: Re: [PATCH v7 2/2] dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW
Date: Mon, 21 Sep 2020 10:23:57 +0800 [thread overview]
Message-ID: <1600655037.3787.1.camel@mtkswgap22> (raw)
In-Reply-To: <1599712262-8819-3-git-send-email-hector.yuan@mediatek.com>
Hi, Rob sir:
Sorry to bother you, may I have your review comment for the binding
part?
Appreciated.
On Thu, 2020-09-10 at 12:31 +0800, Hector Yuan wrote:
> From: "Hector.Yuan" <hector.yuan@mediatek.com>
>
> Add devicetree bindings for MediaTek HW driver.
>
> Signed-off-by: Hector.Yuan <hector.yuan@mediatek.com>
> ---
> .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 141 ++++++++++++++++++++
> 1 file changed, 141 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
>
> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
> new file mode 100644
> index 0000000..118a163
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
> @@ -0,0 +1,141 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek's CPUFREQ Bindings
> +
> +maintainers:
> + - Hector Yuan <hector.yuan@mediatek.com>
> +
> +description:
> + CPUFREQ HW is a hardware engine used by MediaTek
> + SoCs to manage frequency in hardware. It is capable of controlling frequency
> + for multiple clusters.
> +
> +properties:
> + compatible:
> + const: "mediatek,cpufreq-hw"
> +
> + reg:
> + minItems: 1
> + maxItems: 2
> + description: |
> + Addresses and sizes for the memory of the HW bases in each frequency domain.
> +
> + reg-names:
> + items:
> + - const: "freq-domain0"
> + - const: "freq-domain1"
> + description: |
> + Frequency domain name. i.e.
> + "freq-domain0", "freq-domain1".
> +
> + "#freq-domain-cells":
> + const: 1
> + description: |
> + Number of cells in a freqency domain specifier.
> +
> + mtk-freq-domain:
> + maxItems: 1
> + description: |
> + Define this cpu belongs to which frequency domain. i.e.
> + cpu0-3 belong to frequency domain0,
> + cpu4-6 belong to frequency domain1.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - "#freq-domain-cells"
> +
> +examples:
> + - |
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + mtk-freq-domain = <&cpufreq_hw 0>;
> + reg = <0x000>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + mtk-freq-domain = <&cpufreq_hw 0>;
> + reg = <0x100>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + mtk-freq-domain = <&cpufreq_hw 0>;
> + reg = <0x200>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + mtk-freq-domain = <&cpufreq_hw 0>;
> + reg = <0x300>;
> + };
> +
> + cpu4: cpu@4 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + mtk-freq-domain = <&cpufreq_hw 1>;
> + reg = <0x400>;
> + };
> +
> + cpu5: cpu@5 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + enable-method = "psci";
> + mtk-freq-domain = <&cpufreq_hw 1>;
> + reg = <0x500>;
> + };
> +
> + cpu6: cpu@6 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75";
> + enable-method = "psci";
> + mtk-freq-domain = <&cpufreq_hw 1>;
> + reg = <0x600>;
> + };
> +
> + cpu7: cpu@7 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75";
> + enable-method = "psci";
> + mtk-freq-domain = <&cpufreq_hw 1>;
> + reg = <0x700>;
> + };
> + };
> +
> + /* ... */
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpufreq_hw: cpufreq@11bc00 {
> + compatible = "mediatek,cpufreq-hw";
> + reg = <0 0x11bc10 0 0x8c>,
> + <0 0x11bca0 0 0x8c>;
> + reg-names = "freq-domain0", "freq-domain1";
> + #freq-domain-cells = <1>;
> + };
> + };
> +
> +
> +
> +
next prev parent reply other threads:[~2020-09-21 2:24 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-10 4:31 [PATCH v7] cpufreq: mediatek-hw: Add support for Mediatek cpufreq HW driver Hector Yuan
2020-09-10 4:31 ` [PATCH v7 1/2] " Hector Yuan
2020-09-10 4:31 ` [PATCH v7 2/2] dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW Hector Yuan
2020-09-21 2:23 ` Hector Yuan [this message]
2020-09-22 20:28 ` Rob Herring
2020-09-23 13:10 ` Hector Yuan
2020-09-24 2:36 ` Hector Yuan
2020-09-25 2:27 ` Hector Yuan
2020-09-25 6:15 ` Viresh Kumar
2020-09-25 7:25 ` Hector Yuan
2020-10-05 2:29 ` Hector Yuan
2020-09-10 5:03 ` [PATCH v7] cpufreq: mediatek-hw: Add support for Mediatek cpufreq HW driver Viresh Kumar
2020-09-10 5:30 ` Hector Yuan
2020-09-10 5:34 ` Viresh Kumar
2020-09-16 11:39 ` Hector Yuan
2020-09-17 2:31 ` Hector Yuan
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