From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3677DC4741F for ; Wed, 30 Sep 2020 18:59:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EB68E20BED for ; Wed, 30 Sep 2020 18:59:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="xHPJUPfh"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="rKqTso6Y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731131AbgI3S7G (ORCPT ); Wed, 30 Sep 2020 14:59:06 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:58844 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730436AbgI3S64 (ORCPT ); Wed, 30 Sep 2020 14:58:56 -0400 Date: Wed, 30 Sep 2020 18:58:53 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1601492334; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FdnwzdonN6u4LB8CVus79ZJeeIfXYlzK3NjD4Y09slk=; b=xHPJUPfhOALyHDRWsMMFGBmx4zXIYjG7nY+nNUZ5W/JNVHr5NuUsidDtQfQ3N4EmnRFIf2 RQsmVnZc8to/yQqUFLJi56DNplaIpx8xpqu1brrDrnxQM1v5Qq6auaVJACYuDPXvyQOLc9 DM0fROsiMAtWoaZfCVmagbRKrOolxqBr7HacpyYh/hE9W6Y4xMIGx6LkT1ChygiTWNjsp/ dCZrEm/MvLt2XtX8pP2I3npRM1gmrojHg+TrprWNDuS6k3Q6vv2xqQA4cubhqaTlZf10tx cEcEpdHFGEwxIixzPhSWQBHrHhfwcxnVwA6yNBk2QB/Gq6RN5TBb7LHbcqCitg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1601492334; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FdnwzdonN6u4LB8CVus79ZJeeIfXYlzK3NjD4Y09slk=; b=rKqTso6Y6bHomOf2G5ad44bQZLG/959Z9FNAqCT8IMjo7IfIBqQe2zXHiAPfs//pOmalp6 teOKwtJDLtwbEICw== From: "tip-bot2 for Kan Liang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/msr: Add Jasper Lake support Cc: Kan Liang , "Peter Zijlstra (Intel)" , x86 , LKML In-Reply-To: <1601296242-32763-2-git-send-email-kan.liang@linux.intel.com> References: <1601296242-32763-2-git-send-email-kan.liang@linux.intel.com> MIME-Version: 1.0 Message-ID: <160149233376.7002.4167522878778127644.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the perf/core branch of tip: Commit-ID: c3bb8a9fa31b99f5b7d2e45cd0a10db91349f4c9 Gitweb: https://git.kernel.org/tip/c3bb8a9fa31b99f5b7d2e45cd0a10db91349f4c9 Author: Kan Liang AuthorDate: Mon, 28 Sep 2020 05:30:42 -07:00 Committer: Peter Zijlstra CommitterDate: Tue, 29 Sep 2020 09:57:02 +02:00 perf/x86/msr: Add Jasper Lake support The Jasper Lake processor is also a Tremont microarchitecture. From the perspective of perf MSR, there is nothing changed compared with Elkhart Lake. Share the code path with Elkhart Lake. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/1601296242-32763-2-git-send-email-kan.liang@linux.intel.com --- arch/x86/events/msr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index a949f6f..4be8f9c 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -78,6 +78,7 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_ATOM_GOLDMONT_PLUS: case INTEL_FAM6_ATOM_TREMONT_D: case INTEL_FAM6_ATOM_TREMONT: + case INTEL_FAM6_ATOM_TREMONT_L: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM: