* [RESEND PATCH 1/2] perf/x86/intel: Add Jasper Lake support
@ 2020-09-28 12:30 kan.liang
2020-09-28 12:30 ` [RESEND PATCH 2/2] perf/x86/msr: " kan.liang
2020-09-30 18:58 ` [tip: perf/core] perf/x86/intel: " tip-bot2 for Kan Liang
0 siblings, 2 replies; 4+ messages in thread
From: kan.liang @ 2020-09-28 12:30 UTC (permalink / raw)
To: peterz, mingo, acme, linux-kernel; +Cc: ak, Kan Liang
From: Kan Liang <kan.liang@linux.intel.com>
The Jasper Lake processor is also a Tremont microarchitecture. From the
perspective of Intel PMU, there is nothing changed compared with
Elkhart Lake.
Share the perf code with Elkhart Lake.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index c72e490..75dea67 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5135,6 +5135,7 @@ __init int intel_pmu_init(void)
case INTEL_FAM6_ATOM_TREMONT_D:
case INTEL_FAM6_ATOM_TREMONT:
+ case INTEL_FAM6_ATOM_TREMONT_L:
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [RESEND PATCH 2/2] perf/x86/msr: Add Jasper Lake support
2020-09-28 12:30 [RESEND PATCH 1/2] perf/x86/intel: Add Jasper Lake support kan.liang
@ 2020-09-28 12:30 ` kan.liang
2020-09-30 18:58 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-09-30 18:58 ` [tip: perf/core] perf/x86/intel: " tip-bot2 for Kan Liang
1 sibling, 1 reply; 4+ messages in thread
From: kan.liang @ 2020-09-28 12:30 UTC (permalink / raw)
To: peterz, mingo, acme, linux-kernel; +Cc: ak, Kan Liang
From: Kan Liang <kan.liang@linux.intel.com>
The Jasper Lake processor is also a Tremont microarchitecture. From the
perspective of perf MSR, there is nothing changed compared with
Elkhart Lake.
Share the code path with Elkhart Lake.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/msr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index a949f6f..4be8f9c 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -78,6 +78,7 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
case INTEL_FAM6_ATOM_TREMONT_D:
case INTEL_FAM6_ATOM_TREMONT:
+ case INTEL_FAM6_ATOM_TREMONT_L:
case INTEL_FAM6_XEON_PHI_KNL:
case INTEL_FAM6_XEON_PHI_KNM:
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [tip: perf/core] perf/x86/msr: Add Jasper Lake support
2020-09-28 12:30 ` [RESEND PATCH 2/2] perf/x86/msr: " kan.liang
@ 2020-09-30 18:58 ` tip-bot2 for Kan Liang
0 siblings, 0 replies; 4+ messages in thread
From: tip-bot2 for Kan Liang @ 2020-09-30 18:58 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Kan Liang, Peter Zijlstra (Intel), x86, LKML
The following commit has been merged into the perf/core branch of tip:
Commit-ID: c3bb8a9fa31b99f5b7d2e45cd0a10db91349f4c9
Gitweb: https://git.kernel.org/tip/c3bb8a9fa31b99f5b7d2e45cd0a10db91349f4c9
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Mon, 28 Sep 2020 05:30:42 -07:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Tue, 29 Sep 2020 09:57:02 +02:00
perf/x86/msr: Add Jasper Lake support
The Jasper Lake processor is also a Tremont microarchitecture. From the
perspective of perf MSR, there is nothing changed compared with
Elkhart Lake.
Share the code path with Elkhart Lake.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1601296242-32763-2-git-send-email-kan.liang@linux.intel.com
---
arch/x86/events/msr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index a949f6f..4be8f9c 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -78,6 +78,7 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
case INTEL_FAM6_ATOM_TREMONT_D:
case INTEL_FAM6_ATOM_TREMONT:
+ case INTEL_FAM6_ATOM_TREMONT_L:
case INTEL_FAM6_XEON_PHI_KNL:
case INTEL_FAM6_XEON_PHI_KNM:
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [tip: perf/core] perf/x86/intel: Add Jasper Lake support
2020-09-28 12:30 [RESEND PATCH 1/2] perf/x86/intel: Add Jasper Lake support kan.liang
2020-09-28 12:30 ` [RESEND PATCH 2/2] perf/x86/msr: " kan.liang
@ 2020-09-30 18:58 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 4+ messages in thread
From: tip-bot2 for Kan Liang @ 2020-09-30 18:58 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Kan Liang, Peter Zijlstra (Intel), x86, LKML
The following commit has been merged into the perf/core branch of tip:
Commit-ID: dbfd638889a0396f5fe14ff3cc2263ec1e1cac62
Gitweb: https://git.kernel.org/tip/dbfd638889a0396f5fe14ff3cc2263ec1e1cac62
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Mon, 28 Sep 2020 05:30:41 -07:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Tue, 29 Sep 2020 09:57:01 +02:00
perf/x86/intel: Add Jasper Lake support
The Jasper Lake processor is also a Tremont microarchitecture. From the
perspective of Intel PMU, there is nothing changed compared with
Elkhart Lake.
Share the perf code with Elkhart Lake.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1601296242-32763-1-git-send-email-kan.liang@linux.intel.com
---
arch/x86/events/intel/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index c72e490..75dea67 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5135,6 +5135,7 @@ __init int intel_pmu_init(void)
case INTEL_FAM6_ATOM_TREMONT_D:
case INTEL_FAM6_ATOM_TREMONT:
+ case INTEL_FAM6_ATOM_TREMONT_L:
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-09-30 18:59 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2020-09-28 12:30 [RESEND PATCH 1/2] perf/x86/intel: Add Jasper Lake support kan.liang
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2020-09-30 18:58 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-09-30 18:58 ` [tip: perf/core] perf/x86/intel: " tip-bot2 for Kan Liang
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