From: Md Sadre Alam <mdalam@codeaurora.org>
To: agross@kernel.org, bjorn.andersson@linaro.org,
miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
robh+dt@kernel.org, linux-arm-msm@vger.kernel.org,
linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: mdalam@codeaurora.org, sricharan@codeaurora.org
Subject: [PATCH 3/5] mtd: rawnand: qcom: Read QPIC version
Date: Sat, 10 Oct 2020 11:01:40 +0530 [thread overview]
Message-ID: <1602307902-16761-4-git-send-email-mdalam@codeaurora.org> (raw)
In-Reply-To: <1602307902-16761-1-git-send-email-mdalam@codeaurora.org>
This change will add support to read QPIC version.
QPIC version V2.0 onwards some new register introduced
in QPIC. So based on hw_version we will update those
register.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
---
drivers/mtd/nand/raw/qcom_nandc.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index f5064ab..eabb803 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -443,6 +443,7 @@ struct qcom_nand_controller {
u32 cmd1, vld;
const struct qcom_nandc_props *props;
+ u32 hw_version;
};
/*
@@ -2538,6 +2539,7 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
int ecc_mode = 1;
int num_addr_cycle = 5, dsbl_sts_aftr_write = 0;
int wr_rd_bsy_gap = 2, recovery_cycle = 7;
+ u32 version_reg;
/* controller only supports 512 bytes data steps */
ecc->size = NANDC_STEP_SIZE;
@@ -2545,6 +2547,26 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
cwperpage = mtd->writesize / NANDC_STEP_SIZE;
/*
+ * Read the required ecc strength from NAND device and overwrite the
+ * device tree ecc strength
+ */
+ if (chip->base.eccreq.strength >= 8)
+ ecc->strength = 8;
+
+ /* Read QPIC version register */
+ if (nandc->props->is_serial_nand)
+ version_reg = (NAND_VERSION + 0x4000);
+ else
+ version_reg = NAND_VERSION;
+ nandc->hw_version = nandc_read(nandc, version_reg);
+ pr_debug("QPIC controller hw version Major:%d, Minor:%d\n",
+ ((nandc->hw_version & NAND_VERSION_MAJOR_MASK)
+ >> NAND_VERSION_MAJOR_SHIFT),
+ ((nandc->hw_version & NAND_VERSION_MINOR_MASK)
+ >> NAND_VERSION_MINOR_SHIFT));
+ nandc->hw_version = ((nandc->hw_version & NAND_VERSION_MAJOR_MASK)
+ >> NAND_VERSION_MAJOR_SHIFT);
+ /*
* Each CW has 4 available OOB bytes which will be protected with ECC
* so remaining bytes can be used for ECC.
*/
--
2.7.4
next prev parent reply other threads:[~2020-10-10 5:45 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-10 5:31 [PATCH 0/5] mtd: rawnand: qcom: Add support for QSPI nand Md Sadre Alam
2020-10-10 5:31 ` [PATCH 1/5] dt-bindings: qcom_nandc: IPQ5018 QPIC NAND documentation Md Sadre Alam
2020-10-13 16:21 ` Rob Herring
2020-10-10 5:31 ` [PATCH 2/5] mtd: rawnand: qcom: Add initial support for qspi nand Md Sadre Alam
2020-10-29 9:07 ` Boris Brezillon
2023-03-06 14:15 ` Md Sadre Alam
2023-03-06 14:33 ` Md Sadre Alam
2023-03-06 14:38 ` Miquel Raynal
2023-03-27 13:54 ` Md Sadre Alam
2023-03-27 14:49 ` Miquel Raynal
2023-03-28 11:18 ` Md Sadre Alam
2020-10-10 5:31 ` Md Sadre Alam [this message]
2020-10-10 5:31 ` [PATCH 4/5] mtd: rawnand: qcom: Enable support for erase,read & write for serial nand Md Sadre Alam
2020-10-10 5:31 ` [PATCH 5/5] mtd: rawnand: qcom: Add support for serial training Md Sadre Alam
2020-10-28 9:48 ` [PATCH 0/5] mtd: rawnand: qcom: Add support for QSPI nand Miquel Raynal
2020-10-28 18:24 ` mdalam
2020-10-29 7:53 ` Miquel Raynal
2020-10-29 8:37 ` Miquel Raynal
2020-10-29 8:38 ` Boris Brezillon
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