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From: Sibi Sankar <sibis@codeaurora.org>
To: bjorn.andersson@linaro.org, mka@chromium.org
Cc: agross@kernel.org, linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	evgreen@chromium.org, dianders@chromium.org, robh+dt@kernel.org,
	swboyd@chromium.org, Sibi Sankar <sibis@codeaurora.org>
Subject: [PATCH 1/2] arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling on SC7180-lite
Date: Thu, 15 Oct 2020 23:15:38 +0530
Message-ID: <1602783939-7177-1-git-send-email-sibis@codeaurora.org> (raw)

Tweak the DDR/L3 bandwidth votes on the lite variant of the SC7180 SoC
since the gold cores only support frequencies upto 2.1 GHz.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180-lite.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-lite.dtsi

diff --git a/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi
new file mode 100644
index 000000000000..cff50275cfe1
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * SC7180 lite device tree source
+ *
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+&cpu6_opp11 {
+	opp-peak-kBps = <8532000 22425600>;
+};
+
+&cpu6_opp12 {
+	opp-peak-kBps = <8532000 23347200>;
+};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


             reply index

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-15 17:45 Sibi Sankar [this message]
2020-10-15 17:45 ` [PATCH 2/2] arm64: dts: qcom: sc7180: Add DDR/L3 votes for the pro variant Sibi Sankar
2020-10-16 22:59 ` [PATCH 1/2] arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling on SC7180-lite Doug Anderson

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