[PATCH v4 23/34] clk: mediatek: Add MT8192 imp i2c wrapper w clock support

[Weiyi Lu <weiyi.lu@mediatek.com>]

Add MT8192 imp i2c wrapper w clock provider

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 drivers/clk/mediatek/Kconfig                     |  6 +++
 drivers/clk/mediatek/Makefile                    |  1 +
 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_w.c | 59 ++++++++++++++++++++++++
 3 files changed, 66 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_w.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index e16b8b2..8a9d9f6 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -515,6 +515,12 @@ config COMMON_CLK_MT8192_IMP_IIC_WRAP_S
 	help
 	  This driver supports MediaTek MT8192 imp_iic_wrap_s clocks.
 
+config COMMON_CLK_MT8192_IMP_IIC_WRAP_W
+	bool "Clock driver for MediaTek MT8192 imp_iic_wrap_w"
+	depends on COMMON_CLK_MT8192
+	help
+	  This driver supports MediaTek MT8192 imp_iic_wrap_w clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 719505d..1d3598a 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -73,5 +73,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_C) += clk-mt8192-imp_iic_wrap_c.o
 obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_E) += clk-mt8192-imp_iic_wrap_e.o
 obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_N) += clk-mt8192-imp_iic_wrap_n.o
 obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_S) += clk-mt8192-imp_iic_wrap_s.o
+obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_W) += clk-mt8192-imp_iic_wrap_w.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_w.c b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_w.c
new file mode 100644
index 0000000..7e125ec
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_w.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2020 MediaTek Inc.
+// Author: Weiyi Lu <weiyi.lu@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8192-clk.h>
+
+static const struct mtk_gate_regs imp_iic_wrap_w_cg_regs = {
+	.set_ofs = 0xe08,
+	.clr_ofs = 0xe04,
+	.sta_ofs = 0xe00,
+};
+
+#define GATE_IMP_IIC_WRAP_W(_id, _name, _parent, _shift)			\
+	GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_w_cg_regs, _shift,	\
+		&mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
+
+static const struct mtk_gate imp_iic_wrap_w_clks[] = {
+	GATE_IMP_IIC_WRAP_W(CLK_IMP_IIC_WRAP_W_I2C5, "imp_iic_wrap_w_i2c5", "infra_i2c0", 0),
+};
+
+static int clk_mt8192_imp_iic_wrap_w_probe(struct platform_device *pdev)
+{
+	struct clk_onecell_data *clk_data;
+	struct device_node *node = pdev->dev.of_node;
+	int r;
+
+	clk_data = mtk_alloc_clk_data(CLK_IMP_IIC_WRAP_W_NR_CLK);
+	if (!clk_data)
+		return -ENOMEM;
+
+	r = mtk_clk_register_gates(node, imp_iic_wrap_w_clks, ARRAY_SIZE(imp_iic_wrap_w_clks),
+			clk_data);
+	if (r)
+		return r;
+
+	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8192_imp_iic_wrap_w[] = {
+	{ .compatible = "mediatek,mt8192-imp_iic_wrap_w", },
+	{}
+};
+
+static struct platform_driver clk_mt8192_imp_iic_wrap_w_drv = {
+	.probe = clk_mt8192_imp_iic_wrap_w_probe,
+	.driver = {
+		.name = "clk-mt8192-imp_iic_wrap_w",
+		.of_match_table = of_match_clk_mt8192_imp_iic_wrap_w,
+	},
+};
+
+builtin_platform_driver(clk_mt8192_imp_iic_wrap_w_drv);
-- 
1.8.1.1.dirty