From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE79FC55178 for ; Thu, 29 Oct 2020 10:51:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7670620EDD for ; Thu, 29 Oct 2020 10:51:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="hw9ncp3c"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0QiFqh+5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726805AbgJ2Kvl (ORCPT ); Thu, 29 Oct 2020 06:51:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725927AbgJ2Kvk (ORCPT ); Thu, 29 Oct 2020 06:51:40 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA40AC0613CF; Thu, 29 Oct 2020 03:51:40 -0700 (PDT) Date: Thu, 29 Oct 2020 10:51:37 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1603968698; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Azl78zt/NBcg5O7rnft4BwuImw5wLENmFNMrTqxlEQA=; b=hw9ncp3cknEGaid3kCcbMJ3b3x+E6pxImtxjLmPdQ0HlQnyy2CuHosQ6qZPuu04di8d3wS w8XUMpIYfidi0qmi84MCMEEYBLZEj/dtWyLFpEGaSUWScl3derSPS9vS35224xIRh/MSiN ErDqDWWOAnJiitHGM9aF1lfpNqBPttLrh1GHjnj/9uUy3PjRc82KskwE2h5PYGlNtgya/0 I0LICQ3BKmv2sUSx55weTpkwt4G6ROOQ3AsaxP8g1en56f5V4lJk/HQ6nRNzuM/pkWaROG IKko2qk01cAbYrmaTpDboyElP7hvWXlKZxqLzKyA8CjUCmPnlyGwpzK5ukJdEw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1603968698; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Azl78zt/NBcg5O7rnft4BwuImw5wLENmFNMrTqxlEQA=; b=0QiFqh+5R3Num3ZekOLHlKUS16x7MbEivBV9zTUlbfsgmdTXKkSYu/CE+Ys9Lj8JbIwxIe hMQQET6+TvrcrnCQ== From: "tip-bot2 for Kan Liang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Add event constraint for CYCLE_ACTIVITY.STALLS_MEM_ANY Cc: Andi Kleen , Kan Liang , "Peter Zijlstra (Intel)" , stable@vger.kernel.org, x86 , LKML In-Reply-To: <20201019164529.32154-1-kan.liang@linux.intel.com> References: <20201019164529.32154-1-kan.liang@linux.intel.com> MIME-Version: 1.0 Message-ID: <160396869773.397.6435807847521409209.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the perf/core branch of tip: Commit-ID: 306e3e91edf1c6739a55312edd110d298ff498dd Gitweb: https://git.kernel.org/tip/306e3e91edf1c6739a55312edd110d298ff498dd Author: Kan Liang AuthorDate: Mon, 19 Oct 2020 09:45:29 -07:00 Committer: Peter Zijlstra CommitterDate: Thu, 29 Oct 2020 11:00:41 +01:00 perf/x86/intel: Add event constraint for CYCLE_ACTIVITY.STALLS_MEM_ANY The event CYCLE_ACTIVITY.STALLS_MEM_ANY (0x14a3) should be available on all 8 GP counters on ICL, but it's only scheduled on the first four counters due to the current ICL constraint table. Add a line for the CYCLE_ACTIVITY.STALLS_MEM_ANY event in the ICL constraint table. Correct the comments for the CYCLE_ACTIVITY.CYCLES_MEM_ANY event. Fixes: 6017608936c1 ("perf/x86/intel: Add Icelake support") Reported-by: Andi Kleen Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20201019164529.32154-1-kan.liang@linux.intel.com --- arch/x86/events/intel/core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 4d70c7d..0e590c5 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -257,7 +257,8 @@ static struct event_constraint intel_icl_event_constraints[] = { INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf), INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ - INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ + INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ + INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),