From: Huazhong Tan <tanhuazhong@huawei.com>
To: <davem@davemloft.net>
Cc: <netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<salil.mehta@huawei.com>, <yisen.zhuang@huawei.com>,
<linuxarm@huawei.com>, <kuba@kernel.org>,
Huazhong Tan <tanhuazhong@huawei.com>
Subject: [PATCH V2 net-next 03/11] net: hns3: add support for 1us unit GL configuration
Date: Mon, 9 Nov 2020 11:22:31 +0800 [thread overview]
Message-ID: <1604892159-19990-4-git-send-email-tanhuazhong@huawei.com> (raw)
In-Reply-To: <1604892159-19990-1-git-send-email-tanhuazhong@huawei.com>
For device whose version is above V3(include V3), the GL
configuration can set as 1us unit, so adds support for
configuring this field.
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
---
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 26 ++++++++++++++++++----
drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 3 +++
drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 6 +++++
3 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
index 6e08719..2813fe5 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
@@ -224,17 +224,27 @@ void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
u32 gl_value)
{
- u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
+ u32 new_val;
- writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
+ if (tqp_vector->rx_group.coal.unit_1us)
+ new_val = gl_value | HNS3_INT_GL_1US;
+ else
+ new_val = hns3_gl_usec_to_reg(gl_value);
+
+ writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
}
void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
u32 gl_value)
{
- u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
+ u32 new_val;
+
+ if (tqp_vector->tx_group.coal.unit_1us)
+ new_val = gl_value | HNS3_INT_GL_1US;
+ else
+ new_val = hns3_gl_usec_to_reg(gl_value);
- writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
+ writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
}
void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
@@ -272,6 +282,14 @@ static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
rx_coal->flow_level = HNS3_FLOW_LOW;
tx_coal->flow_level = HNS3_FLOW_LOW;
+ /* device version above V3(include V3), GL can configure 1us
+ * unit, so uses 1us unit.
+ */
+ if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
+ tx_coal->unit_1us = 1;
+ rx_coal->unit_1us = 1;
+ }
+
if (ae_dev->dev_specs.int_ql_max) {
tx_coal->ql_enable = 1;
rx_coal->ql_enable = 1;
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
index be099dd..4651ad1 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
@@ -425,6 +425,8 @@ enum hns3_flow_level_range {
#define HNS3_INT_GL_18K 0x0036
#define HNS3_INT_GL_8K 0x007C
+#define HNS3_INT_GL_1US BIT(31)
+
#define HNS3_INT_RL_MAX 0x00EC
#define HNS3_INT_RL_ENABLE_MASK 0x40
@@ -436,6 +438,7 @@ struct hns3_enet_coalesce {
u16 int_ql_max;
u8 gl_adapt_enable:1;
u8 ql_enable:1;
+ u8 unit_1us:1;
enum hns3_flow_level_range flow_level;
};
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
index 9e90d67..8d5c194 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
@@ -1148,6 +1148,12 @@ static int hns3_check_gl_coalesce_para(struct net_device *netdev,
return -EINVAL;
}
+ /* device version above V3(include V3), GL uses 1us unit,
+ * so the round down is not needed.
+ */
+ if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
+ return 0;
+
rx_gl = hns3_gl_round_down(cmd->rx_coalesce_usecs);
if (rx_gl != cmd->rx_coalesce_usecs) {
netdev_info(netdev,
--
2.7.4
next prev parent reply other threads:[~2020-11-09 3:22 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-09 3:22 [PATCH V2 net-next 00/11] net: hns3: updates for -next Huazhong Tan
2020-11-09 3:22 ` [PATCH V2 net-next 01/11] net: hns3: add support for configuring interrupt quantity limiting Huazhong Tan
2020-11-11 1:13 ` Jakub Kicinski
2020-11-11 1:15 ` tanhuazhong
2020-11-09 3:22 ` [PATCH V2 net-next 02/11] net: hns3: add support for querying maximum value of GL Huazhong Tan
2020-11-09 3:22 ` Huazhong Tan [this message]
2020-11-09 3:22 ` [PATCH V2 net-next 04/11] net: hns3: rename gl_adapt_enable in struct hns3_enet_coalesce Huazhong Tan
2020-11-09 3:22 ` [PATCH V2 net-next 05/11] net: hns3: add support for dynamic interrupt moderation Huazhong Tan
2020-11-11 1:20 ` Jakub Kicinski
2020-11-11 2:31 ` tanhuazhong
2020-11-09 3:22 ` [PATCH V2 net-next 06/11] net: hns3: add ethtool priv-flag for DIM Huazhong Tan
2020-11-09 3:22 ` [PATCH V2 net-next 07/11] net: hns3: add hns3_state_init() to do state initialization Huazhong Tan
2020-11-09 3:22 ` [PATCH V2 net-next 08/11] net: hns3: add a check for ethtool priv-flag interface Huazhong Tan
2020-11-09 3:22 ` [PATCH V2 net-next 09/11] net: hns3: add support for EQ/CQ mode configuration Huazhong Tan
2020-11-11 1:25 ` Jakub Kicinski
2020-11-11 3:03 ` tanhuazhong
2020-11-09 3:22 ` [PATCH V2 net-next 10/11] net: hns3: add ethtool priv-flag for EQ/CQ Huazhong Tan
2020-11-09 3:22 ` [PATCH V2 net-next 11/11] net: hns3: add debugfs support for interrupt coalesce Huazhong Tan
2020-11-11 1:28 ` Jakub Kicinski
2020-11-11 3:16 ` tanhuazhong
2020-11-11 16:15 ` Jakub Kicinski
2020-11-12 0:48 ` tanhuazhong
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