From: Crystal Guo <crystal.guo@mediatek.com>
To: Ikjoon Jang <ikjn@chromium.org>
Cc: "p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"Yong Liang (梁勇)" <Yong.Liang@mediatek.com>,
"Stanley Chu (朱原陞)" <stanley.chu@mediatek.com>,
srv_heupstream <srv_heupstream@mediatek.com>,
"Seiya Wang (王迺君)" <seiya.wang@mediatek.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Fan Chen (陳凡)" <fan.chen@mediatek.com>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
"Yingjoe Chen (陳英洲)" <Yingjoe.Chen@mediatek.com>,
"s-anna@ti.com" <s-anna@ti.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [v6, 3/3] reset-controller: ti: force the write operation when assert or deassert
Date: Wed, 2 Dec 2020 19:06:42 +0800 [thread overview]
Message-ID: <1606907202.14806.65.camel@mhfsdcap03> (raw)
In-Reply-To: <20201130111340.GA3042402@chromium.org>
On Mon, 2020-11-30 at 19:13 +0800, Ikjoon Jang wrote:
> On Wed, Sep 30, 2020 at 10:21:59AM +0800, Crystal Guo wrote:
> > Force the write operation in case the read already happens
> > to return the correct value.
> >
> > Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
> > ---
> > drivers/reset/reset-ti-syscon.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
> > index 5d1f8306cd4f..c34394f1e9e2 100644
> > --- a/drivers/reset/reset-ti-syscon.c
> > +++ b/drivers/reset/reset-ti-syscon.c
> > @@ -97,7 +97,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev *rcdev,
> > mask = BIT(control->assert_bit);
> > value = (control->flags & ASSERT_SET) ? mask : 0x0;
> >
> > - return regmap_update_bits(data->regmap, control->assert_offset, mask, value);
> > + return regmap_write_bits(data->regmap, control->assert_offset, mask, value);
> > }
>
> I don't think there are no reset controllers with cached regmap,
> thus I don't think this is needed.
> Are there any specific reasons behind this, what I've missed here?
>
> We need to be sure that all other devices using this driver
> should have no side effects on write.
>
> I can think of a weird controller doing unwanted things internally
> on every write disregarding the current state. (or is this overly
> paranoid?)
>
The specific reason is that, the clear bit may keep the same value with
the set bit, but the clear operation can be only be completed by writing
1 to the clear bit, not just with the current fake state "1".
> >
> > /**
> > @@ -128,7 +128,7 @@ static int ti_syscon_reset_deassert(struct reset_controller_dev *rcdev,
> > mask = BIT(control->deassert_bit);
> > value = (control->flags & DEASSERT_SET) ? mask : 0x0;
> >
> > - return regmap_update_bits(data->regmap, control->deassert_offset, mask, value);
> > + return regmap_write_bits(data->regmap, control->deassert_offset, mask, value);
> > }
> >
> > /**
next prev parent reply other threads:[~2020-12-02 11:08 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-30 2:21 [v6,0/3] introduce TI reset controller for MT8192 SoC Crystal Guo
2020-09-30 2:21 ` [v6,1/3] dt-binding: reset-controller: mediatek: add YAML schemas Crystal Guo
2020-10-14 13:30 ` Crystal Guo
2020-11-11 8:28 ` Stanley Chu
2020-12-03 7:41 ` Philipp Zabel
2020-12-26 9:06 ` Crystal Guo
2020-09-30 2:21 ` [v6,2/3] reset-controller: ti: introduce a new reset handler Crystal Guo
2020-11-30 10:35 ` Ikjoon Jang
2020-12-04 2:34 ` Crystal Guo
2020-09-30 2:21 ` [v6,3/3] reset-controller: ti: force the write operation when assert or deassert Crystal Guo
2020-11-30 11:13 ` [v6, 3/3] " Ikjoon Jang
2020-12-02 11:06 ` Crystal Guo [this message]
2020-12-03 3:30 ` Ikjoon Jang
2020-12-03 7:45 ` [v6,3/3] " Philipp Zabel
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