From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
To: Srikar Dronamraju <srikar@linux.vnet.ibm.com>,
Anton Blanchard <anton@ozlabs.org>,
Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>,
Michael Ellerman <mpe@ellerman.id.au>,
Michael Neuling <mikey@neuling.org>,
Nicholas Piggin <npiggin@gmail.com>,
Nathan Lynch <nathanl@linux.ibm.com>,
Peter Zijlstra <peterz@infradead.org>,
Valentin Schneider <valentin.schneider@arm.com>
Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
"Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
Subject: [PATCH 3/3] powerpc/cacheinfo: Print correct cache-sibling map/list for L2 cache
Date: Fri, 4 Dec 2020 10:18:47 +0530 [thread overview]
Message-ID: <1607057327-29822-4-git-send-email-ego@linux.vnet.ibm.com> (raw)
In-Reply-To: <1607057327-29822-1-git-send-email-ego@linux.vnet.ibm.com>
From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
On POWER platforms where only some groups of threads within a core
share the L2-cache (indicated by the ibm,thread-groups device-tree
property), we currently print the incorrect shared_cpu_map/list for
L2-cache in the sysfs.
This patch reports the correct shared_cpu_map/list on such platforms.
Example:
On a platform with "ibm,thread-groups" set to
00000001 00000002 00000004 00000000
00000002 00000004 00000006 00000001
00000003 00000005 00000007 00000002
00000002 00000004 00000000 00000002
00000004 00000006 00000001 00000003
00000005 00000007
This indicates that threads {0,2,4,6} in the core share the L2-cache
and threads {1,3,5,7} in the core share the L2 cache.
However, without the patch, the shared_cpu_map/list for L2 for CPUs 0,
1 is reported in the sysfs as follows:
/sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_list:0-7
/sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_map:000000,000000ff
/sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_list:0-7
/sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_map:000000,000000ff
With the patch, the shared_cpu_map/list for L2 cache for CPUs 0, 1 is
correctly reported as follows:
/sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_list:0,2,4,6
/sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_map:000000,00000055
/sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_list:1,3,5,7
/sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_map:000000,000000aa
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
---
arch/powerpc/kernel/cacheinfo.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/kernel/cacheinfo.c b/arch/powerpc/kernel/cacheinfo.c
index 65ab9fc..1cc8f37 100644
--- a/arch/powerpc/kernel/cacheinfo.c
+++ b/arch/powerpc/kernel/cacheinfo.c
@@ -651,15 +651,22 @@ static unsigned int index_dir_to_cpu(struct cache_index_dir *index)
return dev->id;
}
+extern bool thread_group_shares_l2;
/*
* On big-core systems, each core has two groups of CPUs each of which
* has its own L1-cache. The thread-siblings which share l1-cache with
* @cpu can be obtained via cpu_smallcore_mask().
+ *
+ * On some big-core systems, the L2 cache is shared only between some
+ * groups of siblings. This is already parsed and encoded in
+ * cpu_l2_cache_mask().
*/
static const struct cpumask *get_big_core_shared_cpu_map(int cpu, struct cache *cache)
{
if (cache->level == 1)
return cpu_smallcore_mask(cpu);
+ if (cache->level == 2 && thread_group_shares_l2)
+ return cpu_l2_cache_mask(cpu);
return &cache->shared_cpu_map;
}
--
1.9.4
next prev parent reply other threads:[~2020-12-04 4:50 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-04 4:48 [PATCH 0/3] Extend Parsing "ibm,thread-groups" for Shared-L2 information Gautham R. Shenoy
2020-12-04 4:48 ` [PATCH 1/3] powerpc/smp: Parse ibm,thread-groups with multiple properties Gautham R. Shenoy
2020-12-07 12:10 ` Srikar Dronamraju
2020-12-08 17:25 ` Gautham R Shenoy
2020-12-09 3:59 ` Michael Ellerman
2020-12-09 8:35 ` Srikar Dronamraju
2020-12-09 9:05 ` Gautham R Shenoy
2020-12-04 4:48 ` [PATCH 2/3] powerpc/smp: Add support detecting thread-groups sharing L2 cache Gautham R. Shenoy
2020-12-07 12:40 ` Srikar Dronamraju
2020-12-08 17:42 ` Gautham R Shenoy
2020-12-09 9:14 ` Srikar Dronamraju
2020-12-04 4:48 ` Gautham R. Shenoy [this message]
2020-12-07 13:11 ` [PATCH 3/3] powerpc/cacheinfo: Print correct cache-sibling map/list for " Srikar Dronamraju
2020-12-08 17:56 ` Gautham R Shenoy
2020-12-09 8:39 ` Srikar Dronamraju
2020-12-09 9:07 ` Gautham R Shenoy
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