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Thu, 10 Dec 2020 10:28:25 +0000 From: Yash Shah To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: bp@suse.de, anup@brainfault.org, Jonathan.Cameron@huawei.com, wsa@kernel.org, sam@ravnborg.org, aou@eecs.berkeley.edu, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, sagar.kadam@sifive.com, sachin.ghadi@sifive.com, Yash Shah Subject: [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740 Date: Thu, 10 Dec 2020 15:58:02 +0530 Message-Id: <1607596083-81480-2-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607596083-81480-1-git-send-email-yash.shah@sifive.com> References: <1607596083-81480-1-git-send-email-yash.shah@sifive.com> Content-Type: text/plain X-Originating-IP: [159.117.144.156] X-ClientProxiedBy: CH0PR13CA0015.namprd13.prod.outlook.com (2603:10b6:610:b1::20) To BY5PR13MB4453.namprd13.prod.outlook.com (2603:10b6:a03:1d1::19) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from osubuntu003.open-silicon.com (159.117.144.156) by CH0PR13CA0015.namprd13.prod.outlook.com (2603:10b6:610:b1::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3654.9 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?erTnY11vkoiMQLDllQ+X+iIjBx4BgS5gliab3iDGQqIRnByOm4m6ek1Xa4YM?= =?us-ascii?Q?AOl4bHn6bq2eryZaN/1Fv7m+SbaAhXDRas8WEHqATGMqtRNyfN4LbSu6t4AN?= =?us-ascii?Q?2pKK2RfogXa6L4ICG85khPBAMcpjkIROg7x8sEFIGSys/3ctZrTr184A/9dz?= =?us-ascii?Q?TfN5zHQ0vMKziqKXfoxQIXTXbGOj70QcFnY1vUGpK1Dhq5FNpAhqcTBWis/3?= =?us-ascii?Q?H9Do5Sj7KqqfJMPWvLzu6GZph4ibSK0+tdYfnFjlunFIgbwReBTach0Ei/G3?= =?us-ascii?Q?ajV5ZOYTMEy2BJsplRP/9g71bRtr+UHunqvk/uwf/zVBmw5piJ0YKICqp2OG?= =?us-ascii?Q?xA1BMdQtmC1Juby/F43qaH1XeYxtDvkZ4v9+VfYGplzx1pPVcP7o+MTPPVqd?= =?us-ascii?Q?rD5ls1jM7LZ06+YuplTViozAAHq9EwuzxUUKbi90IEBCrdUcMFbgjyZ1S8z9?= =?us-ascii?Q?5SqkkVZN4uSVJiW1TT7fqARsaE/MQxjnpAAEy8nFTMvC87BKdMMxZZFGyV9x?= =?us-ascii?Q?UomK+RHzm2nxfeesaisJ+E0csctu6hTRD0g/gT9+LqbIZmU9zukYu2Xw0W4G?= =?us-ascii?Q?+jzsAP/2msPOulfY3Dyl8TCJJih+X7Ntdg7LOcE8TdbjdUU8Zd/LycwNYBVj?= =?us-ascii?Q?LqY4EqNaDd3aZqFit66MSDcFUN8JIjhPduoD4noqbmpXiugb4Y4dUhuNR//h?= =?us-ascii?Q?neD2lnz+OlbbjXehbn23FfBEn/CzXEpEhzy6MF/lsIDEJlemfDLGJ/vW0ycN?= =?us-ascii?Q?/0yIwilLbSqcSE+yMGhxZjgvHXiept3wkGhaf1HPBHGPMAUGInQkHlBNud9n?= =?us-ascii?Q?L9o1hV0ZC/m3p9nf5FZ/tGmiBJ9VXqK3A4fI+X5P+taQEh87qkgF0Xdtdi1X?= =?us-ascii?Q?MQ7NPYnKSy7ke5wH8u90qRwCHCXQRhxRVGJNS7TUSc3555ZgIAWFqXy/hFGU?= =?us-ascii?Q?eucciTw6vRpvbpZrYb+BR2Fnsgz3U5IFuxzg08L2bHcp5abVJqUvkoCD+mfS?= =?us-ascii?Q?jxZg?= X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-AuthSource: BY5PR13MB4453.namprd13.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2020 10:28:24.9155 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-Network-Message-Id: 925f851d-2c38-4538-980b-08d89cf65384 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BDXAmXcfqOhYc80BLeKJsDBHu4a0wl1vCs+MoMXqQTH7u14ZQJOaisyLM1J7KBya2T8Sbl0NDqc0I60mXPqi0A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR13MB2838 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540. Update the DT documentation accordingly with "compatible" and "interrupt" property changes. Signed-off-by: Yash Shah --- .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++++++++++++++++++--- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml index efc0198..6a576dc 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml @@ -27,6 +27,7 @@ select: items: - enum: - sifive,fu540-c000-ccache + - sifive,fu740-c000-ccache required: - compatible @@ -34,7 +35,9 @@ select: properties: compatible: items: - - const: sifive,fu540-c000-ccache + - enum: + - sifive,fu540-c000-ccache + - sifive,fu740-c000-ccache - const: cache cache-block-size: @@ -52,10 +55,13 @@ properties: cache-unified: true interrupts: - description: | - Must contain entries for DirError, DataError and DataFail signals. minItems: 3 - maxItems: 3 + maxItems: 4 + items: + - description: DirError interrupt + - description: DataError interrupt + - description: DataFail interrupt + - description: DirFail interrupt reg: maxItems: 1 @@ -67,6 +73,26 @@ properties: The reference to the reserved-memory for the L2 Loosely Integrated Memory region. The reserved memory node should be defined as per the bindings in reserved-memory.txt. +if: + properties: + compatible: + contains: + const: sifive,fu540-c000-ccache + +then: + properties: + interrupts: + description: | + Must contain entries for DirError, DataError and DataFail signals. + maxItems: 3 + +else: + properties: + interrupts: + description: | + Must contain entries for DirError, DataError, DataFail, DirFail signals. + minItems: 4 + additionalProperties: false required: -- 2.7.4