From: Stephen Boyd <sboyd@kernel.org>
To: pawel.mikolaj.chmiel@gmail.com, kgene@kernel.org,
krzk@kernel.org, mturquette@baylibre.com
Cc: s.nawrocki@samsung.com, tomasz.figa@gmail.com,
cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, pawel.mikolaj.chmiel@gmail.com
Subject: Re: [PATCH] clk: exynos7: Mark aclk_fsys1_200 as critical
Date: Thu, 17 Dec 2020 02:14:24 -0800 [thread overview]
Message-ID: <160820006410.1580929.8444804722224099547@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20201024154346.9589-1-pawel.mikolaj.chmiel@gmail.com>
Not sure why this wasn't picked up in the samsung PR. Can you resend?
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index c1ff715e960c..1048d83f097b 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -538,7 +538,8 @@ static const struct samsung_gate_clock top1_gate_clks[] __initconst = {
> ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT |
> CLK_IS_CRITICAL, 0),
> GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
> - ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0),
> + ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT |
> + CLK_IS_CRITICAL, 0),
>
Please put a comment in the code why a clk is critical.
next prev parent reply other threads:[~2020-12-17 10:15 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20201024154433epcas1p3e6cbd7855e24cb5798026134e61c05b1@epcas1p3.samsung.com>
2020-10-24 15:43 ` [PATCH] clk: exynos7: Mark aclk_fsys1_200 as critical Paweł Chmiel
2020-10-26 5:46 ` Chanwoo Choi
2020-10-26 15:16 ` Krzysztof Kozlowski
2020-12-17 10:14 ` Stephen Boyd [this message]
2020-12-17 21:08 ` Paweł Chmiel
2021-04-07 10:03 ` Sylwester Nawrocki
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