From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AAB7C2BBCF for ; Thu, 17 Dec 2020 11:40:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E3719238A0 for ; Thu, 17 Dec 2020 11:40:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727780AbgLQLkM (ORCPT ); Thu, 17 Dec 2020 06:40:12 -0500 Received: from m43-15.mailgun.net ([69.72.43.15]:25257 "EHLO m43-15.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727646AbgLQLkL (ORCPT ); Thu, 17 Dec 2020 06:40:11 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1608205186; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=pgpbVRkcblqvD0JPcoWLhNE2DxHnjYAqCkzDdtx+jhw=; b=Ru2dfocbh++CI9VlCc0wk48w4OWYJxyWi5SuE9UxmKURD0t95SvDJ2aGdssud84KpvHwpkYo 3aJDDEkKrqe+KU1bJc8rDOx6SYoiddKuEHkm1eAYbqVNRqSb8sTuS9tJmY7eBt0RqE5d/PtA UT7SqcQgM9xx0/7Ool+NdCzyZt8= X-Mailgun-Sending-Ip: 69.72.43.15 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n05.prod.us-east-1.postgun.com with SMTP id 5fdb43660564dfefcd7bb905 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 17 Dec 2020 11:39:18 GMT Sender: kgunda=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 652E5C433CA; Thu, 17 Dec 2020 11:39:17 +0000 (UTC) Received: from kgunda-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: kgunda) by smtp.codeaurora.org (Postfix) with ESMTPSA id E569FC433CA; Thu, 17 Dec 2020 11:39:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E569FC433CA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=kgunda@codeaurora.org From: Kiran Gunda To: swboyd@chromium.org, robh@kernel.org, Andy Gross , Bjorn Andersson , Lee Jones , Rob Herring , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Kiran Gunda Subject: [PATCH V3 1/2] mfd: qcom-spmi-pmic: Convert bindings to .yaml format Date: Thu, 17 Dec 2020 17:08:42 +0530 Message-Id: <1608205123-23119-2-git-send-email-kgunda@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1608205123-23119-1-git-send-email-kgunda@codeaurora.org> References: <1608205123-23119-1-git-send-email-kgunda@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the bindings from .txt to .yaml format. Signed-off-by: Kiran Gunda --- .../devicetree/bindings/mfd/qcom,spmi-pmic.txt | 80 ------------- .../devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 127 +++++++++++++++++++++ 2 files changed, 127 insertions(+), 80 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt create mode 100644 Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt deleted file mode 100644 index 79367a4..0000000 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt +++ /dev/null @@ -1,80 +0,0 @@ - Qualcomm SPMI PMICs multi-function device bindings - -The Qualcomm SPMI series presently includes PM8941, PM8841 and PMA8084 -PMICs. These PMICs use a QPNP scheme through SPMI interface. -QPNP is effectively a partitioning scheme for dividing the SPMI extended -register space up into logical pieces, and set of fixed register -locations/definitions within these regions, with some of these regions -specifically used for interrupt handling. - -The QPNP PMICs are used with the Qualcomm Snapdragon series SoCs, and are -interfaced to the chip via the SPMI (System Power Management Interface) bus. -Support for multiple independent functions are implemented by splitting the -16-bit SPMI slave address space into 256 smaller fixed-size regions, 256 bytes -each. A function can consume one or more of these fixed-size register regions. - -Required properties: -- compatible: Should contain one of: - "qcom,pm8941", - "qcom,pm8841", - "qcom,pma8084", - "qcom,pm8019", - "qcom,pm8226", - "qcom,pm8110", - "qcom,pma8084", - "qcom,pmi8962", - "qcom,pmd9635", - "qcom,pm8994", - "qcom,pmi8994", - "qcom,pm8916", - "qcom,pm8004", - "qcom,pm8909", - "qcom,pm8950", - "qcom,pmi8950", - "qcom,pm8998", - "qcom,pmi8998", - "qcom,pm8005", - or generalized "qcom,spmi-pmic". -- reg: Specifies the SPMI USID slave address for this device. - For more information see: - Documentation/devicetree/bindings/spmi/spmi.yaml - -Required properties for peripheral child nodes: -- compatible: Should contain "qcom,xxx", where "xxx" is a peripheral name. - -Optional properties for peripheral child nodes: -- interrupts: Interrupts are specified as a 4-tuple. For more information - see: - Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt -- interrupt-names: Corresponding interrupt name to the interrupts property - -Each child node of SPMI slave id represents a function of the PMIC. In the -example below the rtc device node represents a peripheral of pm8941 -SID = 0. The regulator device node represents a peripheral of pm8941 SID = 1. - -Example: - - spmi { - compatible = "qcom,spmi-pmic-arb"; - - pm8941@0 { - compatible = "qcom,pm8941", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - - rtc { - compatible = "qcom,rtc"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "alarm"; - }; - }; - - pm8941@1 { - compatible = "qcom,pm8941", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - - regulator { - compatible = "qcom,regulator"; - regulator-name = "8941_boost"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml new file mode 100644 index 0000000..0b3e440 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SPMI PMICs multi-function device bindings + +maintainers: + - Stephen Boyd + +description: | + The Qualcomm SPMI PMICs use a QPNP scheme through SPMI interface. + QPNP is effectively a partitioning scheme for dividing the SPMI extended + register space up into logical pieces, and set of fixed register + locations/definitions within these regions, with some of these regions + specifically used for interrupt handling. + + The QPNP PMICs are used with the Qualcomm Snapdragon series SoCs, and are + interfaced to the chip via the SPMI (System Power Management Interface) bus. + Support for multiple independent functions are implemented by splitting the + 16-bit SPMI slave address space into 256 smaller fixed-size regions, 256 bytes + each. A function can consume one or more of these fixed-size register regions. + +properties: + spmi_bus: + type: object + description: SPMI bus node + +patternProperties: + "^pmic@[0-9]$": + description: Child PMIC nodes + type: object + + properties: + compatible: + items: + - enum: + # Sorted based on subtype ID the device reports + - qcom,pm8941 + - qcom,pm8841 + - qcom,pma8084 + - qcom,pm8019 + - qcom,pm8226 + - qcom,pm8110 + - qcom,pma8084 + - qcom,pmi8962 + - qcom,pmd9635 + - qcom,pm8994 + - qcom,pmi8994 + - qcom,pm8916 + - qcom,pm8004 + - qcom,pm8909 + - qcom,pm8950 + - qcom,pmi8950 + - qcom,pm8998 + - qcom,pmi8998 + - qcom,pm8005 + - qcom,pm660l + - qcom,pm660 + + - enum: + - qcom,spmi-pmic + + reg: + maxItems: 1 + description: + Specifies the SPMI USID slave address for this device. + For more information see bindings/spmi/spmi.txt + + patternProperties: + "@[0-9a-f]$": + description: + Each child node of SPMI slave id represents a function of the PMIC. + In the example below the rtc device node represents a peripheral of + pm8941 SID = 0. The regulator device node represents a peripheral of + pm8941 SID = 1. + type: object + + properties: + interrupts: + maxItems: 4 + description: + Interrupts are specified as a 4-tuple. For more information + see bindings/spmi/qcom,spmi-pmic-arb.txt + + interrupt-names: + description: + Corresponding interrupt name to the interrupts property + + required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + spmi_bus { + compatible = "qcom,spmi-pmic-arb"; + #address-cells = <2>; + #size-cells = <0>; + + pmic@0 { + compatible = "qcom,pm8941"; + reg = <0x0 SPMI_USID>; + + rtc { + compatible = "qcom,rtc"; + interrupts = <0x0 0x61 0x1 0x1>; + interrupt-names = "alarm"; + }; + }; + + pmic@1 { + compatible = "qcom,pm8941"; + reg = <0x1 SPMI_USID>; + + regulator { + compatible = "qcom,regulator"; + regulator-name = "8941_boost"; + }; + }; + }; +... -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project