From: Stephen Boyd <sboyd@kernel.org>
To: Daniel Palmer <daniel@0x0f.com>,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, w@1wt.eu,
Daniel Palmer <daniel@0x0f.com>
Subject: Re: [PATCH 2/6] dt-bindings: clk: mstar msc313 mpll binding description
Date: Sat, 19 Dec 2020 19:39:20 -0800 [thread overview]
Message-ID: <160843556037.1580929.13575770228476494246@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20201114135044.724385-3-daniel@0x0f.com>
Quoting Daniel Palmer (2020-11-14 05:50:40)
> Add a binding description for the MStar/SigmaStar MPLL clock block.
>
> Signed-off-by: Daniel Palmer <daniel@0x0f.com>
> ---
> .../bindings/clock/mstar,msc313-mpll.yaml | 58 +++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml b/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml
> new file mode 100644
> index 000000000000..9ddc1163b31b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/mstar,msc313-mpll.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MStar/Sigmastar MSC313 MPLL
> +
> +maintainers:
> + - Daniel Palmer <daniel@thingy.jp>
> +
> +description: |
> + The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that
> + takes the external xtal input and multiplies it to create a high
> + frequency clock and divides that down into a number of clocks that
> + peripherals use.
> +
> +properties:
> + compatible:
> + const: mstar,msc313-mpll
> +
> + "#clock-cells":
> + const: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-output-names:
> + minItems: 8
> + maxItems: 8
> + description: |
> + This should provide a name for the internal PLL clock and then
> + a name for each of the divided outputs.
Is this necessary?
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - "#clock-cells"
> + - clocks
> + - clock-output-names
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + mpll@206000 {
> + compatible = "mstar,msc313-mpll";
> + reg = <0x206000 0x200>;
> + #clock-cells = <1>;
> + clocks = <&xtal>;
> + clock-output-names = "mpll", "mpll_div_2",
> + "mpll_div_3", "mpll_div_4",
> + "mpll_div_5", "mpll_div_6",
> + "mpll_div_7", "mpll_div_10";
It looks like it can be derived in the driver.
next prev parent reply other threads:[~2020-12-20 3:40 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-14 13:50 [PATCH 0/6] ARM: mstar: Basic MPLL support Daniel Palmer
2020-11-14 13:50 ` [PATCH 1/6] dt-bindings: clk: mstar msc313 mpll binding header Daniel Palmer
2020-12-07 19:02 ` Rob Herring
2020-11-14 13:50 ` [PATCH 2/6] dt-bindings: clk: mstar msc313 mpll binding description Daniel Palmer
2020-12-07 19:03 ` Rob Herring
2020-12-20 3:39 ` Stephen Boyd [this message]
2020-12-20 6:35 ` Daniel Palmer
2020-12-20 18:44 ` Stephen Boyd
2020-12-21 8:51 ` Daniel Palmer
2021-02-10 2:29 ` Stephen Boyd
2021-02-11 2:28 ` Daniel Palmer
2021-02-11 2:55 ` Stephen Boyd
2020-11-14 13:50 ` [PATCH 3/6] clk: mstar: MStar/SigmaStar MPLL driver Daniel Palmer
2020-12-20 4:36 ` Stephen Boyd
2020-12-20 6:42 ` Daniel Palmer
2020-12-20 18:43 ` Stephen Boyd
2020-12-21 8:40 ` Daniel Palmer
2020-11-14 13:50 ` [PATCH 4/6] ARM: mstar: Select MSTAR_MSC313_MPLL Daniel Palmer
2020-11-14 13:50 ` [PATCH 5/6] ARM: mstar: Add the external clocks to the base dsti Daniel Palmer
2020-11-14 13:50 ` [PATCH 6/6] ARM: mstar: Add mpll to base dtsi Daniel Palmer
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