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[193.116.97.30]) by smtp.gmail.com with ESMTPSA id 6sm39988438pfj.216.2020.12.29.18.33.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Dec 2020 18:33:08 -0800 (PST) Date: Wed, 30 Dec 2020 12:33:02 +1000 From: Nicholas Piggin Subject: Re: [RFC please help] membarrier: Rewrite sync_core_before_usermode() To: Russell King - ARM Linux admin Cc: Arnd Bergmann , Benjamin Herrenschmidt , Catalin Marinas , Jann Horn , linux-arm-kernel , linux-kernel , linuxppc-dev , Andy Lutomirski , Mathieu Desnoyers , Michael Ellerman , paulmck , Paul Mackerras , Peter Zijlstra , stable , Will Deacon , x86 References: <20201228102537.GG1551@shell.armlinux.org.uk> <20201228190852.GI1551@shell.armlinux.org.uk> <1086654515.3607.1609187556216.JavaMail.zimbra@efficios.com> <1609200902.me5niwm2t6.astroid@bobo.none> <1609210162.4d8dqilke6.astroid@bobo.none> <20201229104456.GK1551@shell.armlinux.org.uk> In-Reply-To: <20201229104456.GK1551@shell.armlinux.org.uk> MIME-Version: 1.0 Message-Id: <1609290821.wrfh89v23a.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Excerpts from Russell King - ARM Linux admin's message of December 29, 2020= 8:44 pm: > On Tue, Dec 29, 2020 at 01:09:12PM +1000, Nicholas Piggin wrote: >> I think it should certainly be documented in terms of what guarantees >> it provides to application, _not_ the kinds of instructions it may or >> may not induce the core to execute. And if existing API can't be >> re-documented sanely, then deprecatd and new ones added that DTRT. >> Possibly under a new system call, if arch's like ARM want a range >> flush and we don't want to expand the multiplexing behaviour of >> membarrier even more (sigh). >=20 > The 32-bit ARM sys_cacheflush() is there only to support self-modifying > code, and takes whatever actions are necessary to support that. > Exactly what actions it takes are cache implementation specific, and > should be of no concern to the caller, but the underlying thing is... > it's to support self-modifying code. Caveat cacheflush() should not be used in programs intended to be portab= le. On Linux, this call first appeared on the MIPS architecture, but no= wa=E2=80=90 days, Linux provides a cacheflush() system call on some other archit= ec=E2=80=90 tures, but with different arguments. What a disaster. Another badly designed interface, although it didn't=20 originate in Linux it sounds like we weren't to be outdone so we messed it up even worse. flushing caches is neither necessary nor sufficient for code modification on many processors. Maybe some old MIPS specific private thing was fine, but certainly before it grew to other architectures, somebody should=20 have thought for more than 2 minutes about it. Sigh. >=20 > Sadly, because it's existed for 20+ years, and it has historically been > sufficient for other purposes too, it has seen quite a bit of abuse > despite its design purpose not changing - it's been used by graphics > drivers for example. They quickly learnt the error of their ways with > ARMv6+, since it does not do sufficient for their purposes given the > cache architectures found there. >=20 > Let's not go around redesigning this after twenty odd years, requiring > a hell of a lot of pain to users. This interface is called by code > generated by GCC, so to change it you're looking at patching GCC as > well as the kernel, and you basically will make new programs > incompatible with older kernels - very bad news for users. For something to be redesigned it had to have been designed in the first=20 place, so there is no danger of that don't worry... But no I never=20 suggested making incompatible changes to any existing system call, I=20 said "re-documented". And yes I said deprecated but in Linux that really=20 means kept indefinitely. If ARM, MIPS, 68k etc programs and toolchains keep using what they are=20 using it'll keep working no problem. The point is we're growing new interfaces, and making the same mistakes.=20 It's not portable (ARCH_HAS_MEMBARRIER_SYNC_CORE), it's also specified=20 in terms of low level processor operations rather than higher level=20 intent, and also is not sufficient for self-modifying code (without=20 additional cache flush on some processors). The application wants a call that says something like "memory modified=20 before the call will be visible as instructions (including illegal=20 instructions) by all threads in the program after the system call=20 returns, and no threads will be subject to any effects of executing the=20 previous contents of that memory. So I think the basics are simple (although should confirm with some JIT=20 and debugger etc developers, and not just Android mind you). There are=20 some complications in details, address ranges, virtual/physical, thread=20 local vs process vs different process or system-wide, memory ordering=20 and propagation of i and d sides, etc. But that can be worked through,=20 erring on the side of sanity rather than pointless micro-optmisations. Thanks, Nick