From: Stephen Boyd <sboyd@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
Taniya Das <tdas@codeaurora.org>
Cc: Rajendra Nayak <rnayak@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, robh@kernel.org, robh+dt@kernel.org,
Taniya Das <tdas@codeaurora.org>
Subject: Re: [PATCH v1 1/2] dt-bindings: clock: Add SC7280 GCC clock binding
Date: Tue, 12 Jan 2021 12:06:14 -0800 [thread overview]
Message-ID: <161048197433.3661239.10431667618674179787@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <1608058114-29025-2-git-send-email-tdas@codeaurora.org>
Quoting Taniya Das (2020-12-15 10:48:33)
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> new file mode 100644
> index 0000000..79c64d8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> @@ -0,0 +1,85 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller Binding for SC7280
> +
> +maintainers:
> + - Taniya Das <tdas@codeaurora.org>
> +
> +description: |
> + Qualcomm global clock control module which supports the clocks, resets and
> + power domains on SC7280.
> +
> + See also:
> + - dt-bindings/clock/qcom,gcc-sc7280.h
> +
> +properties:
> + compatible:
> + const: qcom,gcc-sc7280
> +
> + clocks:
> + items:
> + - description: Board XO source
> + - description: Board active XO source
> + - description: Sleep clock source
> + - description: PCIE-0 pipe clock source
> + - description: PCIE-1 pipe clock source
> + - description: USB30 phy wrapper pipe clock source
> +
> + clock-names:
> + items:
> + - const: bi_tcxo
> + - const: bi_tcxo_ao
> + - const: sleep_clk
> + - const: pcie_0_pipe_clk
> + - const: pcie_1_pipe_clk
> + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
Don't ufs phy clks also go into gcc?
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> + '#power-domain-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> + protected-clocks:
> + description:
> + Protected clock specifier list as per common clock binding.
I suppose this is fine.
> +
> +required:
> + - compatible
> + - clocks
> + - clock-names
> + - reg
> + - '#clock-cells'
> + - '#reset-cells'
> + - '#power-domain-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,rpmh.h>
> + clock-controller@100000 {
> + compatible = "qcom,gcc-sc7280";
> + reg = <0x00100000 0x1f0000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&rpmhcc RPMH_CXO_CLK_A>,
> + <&sleep_clk>,
> + <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
> + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
> + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk",
> + "pcie_1_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +...
next prev parent reply other threads:[~2021-01-12 22:00 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-15 18:48 [PATCH v1 0/2] Add Global Clock controller (GCC) driver for SC7280 Taniya Das
2020-12-15 18:48 ` [PATCH v1 1/2] dt-bindings: clock: Add SC7280 GCC clock binding Taniya Das
2020-12-21 19:00 ` Rob Herring
2021-02-10 18:21 ` Taniya Das
2021-01-12 20:06 ` Stephen Boyd [this message]
2021-02-10 18:22 ` Taniya Das
2020-12-15 18:48 ` [PATCH v1 2/2] clk: qcom: Add Global Clock controller (GCC) driver for SC7280 Taniya Das
2021-01-12 20:04 ` Stephen Boyd
2021-02-10 18:24 ` Taniya Das
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