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* [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE
@ 2021-01-27  8:55 Anshuman Khandual
  2021-01-27  8:55 ` [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
                   ` (15 more replies)
  0 siblings, 16 replies; 90+ messages in thread
From: Anshuman Khandual @ 2021-01-27  8:55 UTC (permalink / raw)
  To: linux-arm-kernel, coresight
  Cc: mathieu.poirier, suzuki.poulose, mike.leach, lcherian,
	linux-kernel, Anshuman Khandual

This series enables future IP trace features Embedded Trace Extension (ETE)
and Trace Buffer Extension (TRBE). This series depends on the ETM system
register instruction support series [0] which is available here [1]. This
series which applies on [1] is avaialble here [2] for quick access.

ETE is the PE (CPU) trace unit for CPUs, implementing future architecture
extensions. ETE overlaps with the ETMv4 architecture, with additions to
support the newer architecture features and some restrictions on the
supported features w.r.t ETMv4. The ETE support is added by extending the
ETMv4 driver to recognise the ETE and handle the features as exposed by the
TRCIDRx registers. ETE only supports system instructions access from the
host CPU. The ETE could be integrated with a TRBE (see below), or with the
legacy CoreSight trace bus (e.g, ETRs). Thus the ETE follows same firmware
description as the ETMs and requires a node per instance. 

Trace Buffer Extensions (TRBE) implements a per CPU trace buffer, which is
accessible via the system registers and can be combined with the ETE to
provide a 1x1 configuration of source & sink. TRBE is being represented
here as a CoreSight sink. Primary reason is that the ETE source could work
with other traditional CoreSight sink devices. As TRBE captures the trace
data which is produced by ETE, it cannot work alone.

TRBE representation here have some distinct deviations from a traditional
CoreSight sink device. Coresight path between ETE and TRBE are not built
during boot looking at respective DT or ACPI entries.

Unlike traditional sinks, TRBE can generate interrupts to signal including
many other things, buffer got filled. The interrupt is a PPI and should be
communicated from the platform. DT or ACPI entry representing TRBE should
have the PPI number for a given platform. During perf session, the TRBE IRQ
handler should capture trace for perf auxiliary buffer before restarting it
back. System registers being used here to configure ETE and TRBE could be
referred in the link below.

https://developer.arm.com/docs/ddi0601/g/aarch64-system-registers.

Question:

- Should we implement sysfs based trace sessions for TRBE ?

[0] https://lore.kernel.org/linux-arm-kernel/20210110224850.1880240-1-suzuki.poulose@arm.com/
[1] https://gitlab.arm.com/linux-arm/linux-skp/-/tree/coresight/etm/sysreg-v7
[2] https://gitlab.arm.com/linux-arm/linux-anshuman/-/tree/coresight/ete_trbe_v3

Changes in V3:

- Rebased on coresight/next
- Changed DT bindings for ETE
- Included additional patches for arm64 nvhe, perf aux buffer flags etc
- TRBE changes have been captured in the respective patches

Changes in V2:

https://lore.kernel.org/linux-arm-kernel/1610511498-4058-1-git-send-email-anshuman.khandual@arm.com/

- Converted both ETE and TRBE DT bindings into Yaml
- TRBE changes have been captured in the respective patches
 
Changes in V1:

https://lore.kernel.org/linux-arm-kernel/1608717823-18387-1-git-send-email-anshuman.khandual@arm.com/

- There are not much ETE changes from Suzuki apart from splitting of the ETE DTS patch
- TRBE changes have been captured in the respective patches

Changes in RFC:

https://lore.kernel.org/linux-arm-kernel/1605012309-24812-1-git-send-email-anshuman.khandual@arm.com/

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Linu Cherian <lcherian@marvell.com>
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org

Anshuman Khandual (3):
  coresight: core: Add support for dedicated percpu sinks
  arm64: Add TRBE definitions
  coresight: sink: Add TRBE driver

Suzuki K Poulose (11):
  coresight: etm-perf: Allow an event to use different sinks
  coresight: Do not scan for graph if none is present
  coresight: etm4x: Add support for PE OS lock
  coresight: ete: Add support for ETE sysreg access
  coresight: ete: Add support for ETE tracing
  dts: bindings: Document device tree bindings for ETE
  coresight: etm-perf: Handle stale output handles
  arm64: nvhe: Allow TRBE access at EL1
  dts: bindings: Document device tree bindings for Arm TRBE
  perf: aux: Add flags for the buffer format
  coresight: etm-perf: Add support for trace buffer format

 Documentation/devicetree/bindings/arm/ete.yaml     |   74 ++
 Documentation/devicetree/bindings/arm/trbe.yaml    |   49 +
 Documentation/trace/coresight/coresight-trbe.rst   |   39 +
 arch/arm64/include/asm/el2_setup.h                 |   19 +
 arch/arm64/include/asm/kvm_arm.h                   |    2 +
 arch/arm64/include/asm/sysreg.h                    |   51 +
 drivers/hwtracing/coresight/Kconfig                |   21 +-
 drivers/hwtracing/coresight/Makefile               |    1 +
 drivers/hwtracing/coresight/coresight-core.c       |   16 +-
 drivers/hwtracing/coresight/coresight-etm-perf.c   |   93 +-
 drivers/hwtracing/coresight/coresight-etm4x-core.c |  138 ++-
 .../hwtracing/coresight/coresight-etm4x-sysfs.c    |   19 +-
 drivers/hwtracing/coresight/coresight-etm4x.h      |   81 +-
 drivers/hwtracing/coresight/coresight-platform.c   |    6 +
 drivers/hwtracing/coresight/coresight-trbe.c       | 1025 ++++++++++++++++++++
 drivers/hwtracing/coresight/coresight-trbe.h       |  160 +++
 include/linux/coresight.h                          |   12 +
 include/uapi/linux/perf_event.h                    |   13 +-
 18 files changed, 1759 insertions(+), 60 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/ete.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/trbe.yaml
 create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
 create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
 create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h

-- 
2.7.4


^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
@ 2021-01-27  8:55 ` Anshuman Khandual
  2021-02-01 23:17   ` Mathieu Poirier
  2021-01-27  8:55 ` [PATCH V3 02/14] coresight: Do not scan for graph if none is present Anshuman Khandual
                   ` (14 subsequent siblings)
  15 siblings, 1 reply; 90+ messages in thread
From: Anshuman Khandual @ 2021-01-27  8:55 UTC (permalink / raw)
  To: linux-arm-kernel, coresight
  Cc: mathieu.poirier, suzuki.poulose, mike.leach, lcherian,
	linux-kernel, Anshuman Khandual

From: Suzuki K Poulose <suzuki.poulose@arm.com>

When there are multiple sinks on the system, in the absence
of a specified sink, it is quite possible that a default sink
for an ETM could be different from that of another ETM. However
we do not support having multiple sinks for an event yet. This
patch allows the event to use the default sinks on the ETMs
where they are scheduled as long as the sinks are of the same
type.

e.g, if we have 1x1 topology with per-CPU ETRs, the event can
use the per-CPU ETR for the session. However, if the sinks
are of different type, e.g TMC-ETR on one and a custom sink
on another, the event will only trace on the first detected
sink.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Tested-by: Linu Cherian <lcherian@marvell.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 drivers/hwtracing/coresight/coresight-etm-perf.c | 48 +++++++++++++++++++-----
 1 file changed, 38 insertions(+), 10 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
index bdc34ca..eb9e7e9 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -204,6 +204,13 @@ static void etm_free_aux(void *data)
 	schedule_work(&event_data->work);
 }
 
+static bool sinks_match(struct coresight_device *a, struct coresight_device *b)
+{
+	if (!a || !b)
+		return false;
+	return (sink_ops(a) == sink_ops(b));
+}
+
 static void *etm_setup_aux(struct perf_event *event, void **pages,
 			   int nr_pages, bool overwrite)
 {
@@ -212,6 +219,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
 	cpumask_t *mask;
 	struct coresight_device *sink = NULL;
 	struct etm_event_data *event_data = NULL;
+	bool sink_forced = false;
 
 	event_data = alloc_event_data(cpu);
 	if (!event_data)
@@ -222,6 +230,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
 	if (event->attr.config2) {
 		id = (u32)event->attr.config2;
 		sink = coresight_get_sink_by_id(id);
+		sink_forced = true;
 	}
 
 	mask = &event_data->mask;
@@ -235,7 +244,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
 	 */
 	for_each_cpu(cpu, mask) {
 		struct list_head *path;
-		struct coresight_device *csdev;
+		struct coresight_device *csdev, *new_sink;
 
 		csdev = per_cpu(csdev_src, cpu);
 		/*
@@ -249,21 +258,35 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
 		}
 
 		/*
-		 * No sink provided - look for a default sink for one of the
-		 * devices. At present we only support topology where all CPUs
-		 * use the same sink [N:1], so only need to find one sink. The
-		 * coresight_build_path later will remove any CPU that does not
-		 * attach to the sink, or if we have not found a sink.
+		 * No sink provided - look for a default sink for all the devices.
+		 * We only support multiple sinks, only if all the default sinks
+		 * are of the same type, so that the sink buffer can be shared
+		 * as the event moves around. We don't trace on a CPU if it can't
+		 *
 		 */
-		if (!sink)
-			sink = coresight_find_default_sink(csdev);
+		if (!sink_forced) {
+			new_sink = coresight_find_default_sink(csdev);
+			if (!new_sink) {
+				cpumask_clear_cpu(cpu, mask);
+				continue;
+			}
+			/* Skip checks for the first sink */
+			if (!sink) {
+			       sink = new_sink;
+			} else if (!sinks_match(new_sink, sink)) {
+				cpumask_clear_cpu(cpu, mask);
+				continue;
+			}
+		} else {
+			new_sink = sink;
+		}
 
 		/*
 		 * Building a path doesn't enable it, it simply builds a
 		 * list of devices from source to sink that can be
 		 * referenced later when the path is actually needed.
 		 */
-		path = coresight_build_path(csdev, sink);
+		path = coresight_build_path(csdev, new_sink);
 		if (IS_ERR(path)) {
 			cpumask_clear_cpu(cpu, mask);
 			continue;
@@ -284,7 +307,12 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
 	if (!sink_ops(sink)->alloc_buffer || !sink_ops(sink)->free_buffer)
 		goto err;
 
-	/* Allocate the sink buffer for this session */
+	/*
+	 * Allocate the sink buffer for this session. All the sinks
+	 * where this event can be scheduled are ensured to be of the
+	 * same type. Thus the same sink configuration is used by the
+	 * sinks.
+	 */
 	event_data->snk_config =
 			sink_ops(sink)->alloc_buffer(sink, event, pages,
 						     nr_pages, overwrite);
-- 
2.7.4


^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH V3 02/14] coresight: Do not scan for graph if none is present
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
  2021-01-27  8:55 ` [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
@ 2021-01-27  8:55 ` Anshuman Khandual
  2021-02-01 23:44   ` Mathieu Poirier
  2021-02-02 11:10   ` Mike Leach
  2021-01-27  8:55 ` [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
                   ` (13 subsequent siblings)
  15 siblings, 2 replies; 90+ messages in thread
From: Anshuman Khandual @ 2021-01-27  8:55 UTC (permalink / raw)
  To: linux-arm-kernel, coresight
  Cc: mathieu.poirier, suzuki.poulose, mike.leach, lcherian,
	linux-kernel, Anshuman Khandual

From: Suzuki K Poulose <suzuki.poulose@arm.com>

If a graph node is not found for a given node, of_get_next_endpoint()
will emit the following error message :

 OF: graph: no port node found in /<node_name>

If the given component doesn't have any explicit connections (e.g,
ETE) we could simply ignore the graph parsing.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 drivers/hwtracing/coresight/coresight-platform.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c
index 3629b78..c594f45 100644
--- a/drivers/hwtracing/coresight/coresight-platform.c
+++ b/drivers/hwtracing/coresight/coresight-platform.c
@@ -90,6 +90,12 @@ static void of_coresight_get_ports_legacy(const struct device_node *node,
 	struct of_endpoint endpoint;
 	int in = 0, out = 0;
 
+	/*
+	 * Avoid warnings in of_graph_get_next_endpoint()
+	 * if the device doesn't have any graph connections
+	 */
+	if (!of_graph_is_present(node))
+		return;
 	do {
 		ep = of_graph_get_next_endpoint(node, ep);
 		if (!ep)
-- 
2.7.4


^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
  2021-01-27  8:55 ` [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
  2021-01-27  8:55 ` [PATCH V3 02/14] coresight: Do not scan for graph if none is present Anshuman Khandual
@ 2021-01-27  8:55 ` Anshuman Khandual
  2021-02-02 17:40   ` Mathieu Poirier
                     ` (2 more replies)
  2021-01-27  8:55 ` [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access Anshuman Khandual
                   ` (12 subsequent siblings)
  15 siblings, 3 replies; 90+ messages in thread
From: Anshuman Khandual @ 2021-01-27  8:55 UTC (permalink / raw)
  To: linux-arm-kernel, coresight
  Cc: mathieu.poirier, suzuki.poulose, mike.leach, lcherian,
	linux-kernel, Anshuman Khandual

From: Suzuki K Poulose <suzuki.poulose@arm.com>

ETE may not implement the OS lock and instead could rely on
the PE OS Lock for the trace unit access. This is indicated
by the TRCOLSR.OSM == 0b100. Add support for handling the
PE OS lock

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 drivers/hwtracing/coresight/coresight-etm4x-core.c | 50 ++++++++++++++++++----
 drivers/hwtracing/coresight/coresight-etm4x.h      | 15 +++++++
 2 files changed, 56 insertions(+), 9 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 473ab74..9edf8be 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -114,30 +114,59 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
 	}
 }
 
-static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa)
+static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
+			       struct csdev_access *csa)
 {
-	/* Writing 0 to TRCOSLAR unlocks the trace registers */
-	etm4x_relaxed_write32(csa, 0x0, TRCOSLAR);
-	drvdata->os_unlock = true;
+	u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
+
+	drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
+}
+
+static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
+			      struct csdev_access *csa, u32 val)
+{
+	val = !!val;
+
+	switch (drvdata->os_lock_model) {
+	case ETM_OSLOCK_PRESENT:
+		etm4x_relaxed_write32(csa, val, TRCOSLAR);
+		break;
+	case ETM_OSLOCK_PE:
+		write_sysreg_s(val, SYS_OSLAR_EL1);
+		break;
+	default:
+		pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
+			     smp_processor_id(), drvdata->os_lock_model);
+		fallthrough;
+	case ETM_OSLOCK_NI:
+		return;
+	}
 	isb();
 }
 
+static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
+				      struct csdev_access *csa)
+{
+	WARN_ON(drvdata->cpu != smp_processor_id());
+
+	/* Writing 0 to OS Lock unlocks the trace unit registers */
+	etm_write_os_lock(drvdata, csa, 0x0);
+	drvdata->os_unlock = true;
+}
+
 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
 {
 	if (!WARN_ON(!drvdata->csdev))
 		etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
-
 }
 
 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
 {
 	if (WARN_ON(!drvdata->csdev))
 		return;
-
-	/* Writing 0x1 to TRCOSLAR locks the trace registers */
-	etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR);
+	/* Writing 0x1 to OS Lock locks the trace registers */
+	etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
 	drvdata->os_unlock = false;
-	isb();
 }
 
 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
@@ -906,6 +935,9 @@ static void etm4_init_arch_data(void *info)
 	if (!etm4_init_csdev_access(drvdata, csa))
 		return;
 
+	/* Detect the support for OS Lock before we actuall use it */
+	etm_detect_os_lock(drvdata, csa);
+
 	/* Make sure all registers are accessible */
 	etm4_os_unlock_csa(drvdata, csa);
 	etm4_cs_unlock(drvdata, csa);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 0af6057..0e86eba 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -506,6 +506,20 @@
 					 ETM_MODE_EXCL_USER)
 
 /*
+ * TRCOSLSR.OSLM advertises the OS Lock model.
+ * OSLM[2:0] = TRCOSLSR[4:3,0]
+ *
+ *	0b000 - Trace OS Lock is not implemented.
+ *	0b010 - Trace OS Lock is implemented.
+ *	0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock.
+ */
+#define ETM_OSLOCK_NI		0b000
+#define ETM_OSLOCK_PRESENT	0b010
+#define ETM_OSLOCK_PE		0b100
+
+#define ETM_OSLSR_OSLM(oslsr)	((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1))
+
+/*
  * TRCDEVARCH Bit field definitions
  * Bits[31:21]	- ARCHITECT = Always Arm Ltd.
  *                * Bits[31:28] = 0x4
@@ -897,6 +911,7 @@ struct etmv4_drvdata {
 	u8				s_ex_level;
 	u8				ns_ex_level;
 	u8				q_support;
+	u8				os_lock_model;
 	bool				sticky_enable;
 	bool				boot_enable;
 	bool				os_unlock;
-- 
2.7.4


^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
                   ` (2 preceding siblings ...)
  2021-01-27  8:55 ` [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
@ 2021-01-27  8:55 ` Anshuman Khandual
  2021-02-02 17:52   ` Mathieu Poirier
  2021-02-15 14:08   ` Mike Leach
  2021-01-27  8:55 ` [PATCH V3 05/14] coresight: ete: Add support for ETE tracing Anshuman Khandual
                   ` (11 subsequent siblings)
  15 siblings, 2 replies; 90+ messages in thread
From: Anshuman Khandual @ 2021-01-27  8:55 UTC (permalink / raw)
  To: linux-arm-kernel, coresight
  Cc: mathieu.poirier, suzuki.poulose, mike.leach, lcherian,
	linux-kernel, Anshuman Khandual

From: Suzuki K Poulose <suzuki.poulose@arm.com>

Add support for handling the system registers for Embedded Trace
Extensions (ETE). ETE shares most of the registers with ETMv4 except
for some and also adds some new registers. Re-arrange the ETMv4x list
to share the common definitions and add the ETE sysreg support.

Cc: Mike Leach <mike.leach@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 drivers/hwtracing/coresight/coresight-etm4x-core.c | 32 +++++++++++++
 drivers/hwtracing/coresight/coresight-etm4x.h      | 52 ++++++++++++++++++----
 2 files changed, 75 insertions(+), 9 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 9edf8be..9e92d2a 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -114,6 +114,38 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
 	}
 }
 
+u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
+{
+	u64 res = 0;
+
+	switch (offset) {
+	ETE_READ_CASES(res)
+	default :
+		WARN_ONCE(1, "ete: trying to read unsupported register @%x\n",
+			 offset);
+	}
+
+	if (!_relaxed)
+		__iormb(res);	/* Imitate the !relaxed I/O helpers */
+
+	return res;
+}
+
+void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
+{
+	if (!_relaxed)
+		__iowmb();	/* Imitate the !relaxed I/O helpers */
+	if (!_64bit)
+		val &= GENMASK(31, 0);
+
+	switch (offset) {
+	ETE_WRITE_CASES(val)
+	default :
+		WARN_ONCE(1, "ete: trying to write to unsupported register @%x\n",
+			offset);
+	}
+}
+
 static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
 			       struct csdev_access *csa)
 {
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 0e86eba..ca24ac5 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -29,6 +29,7 @@
 #define TRCAUXCTLR			0x018
 #define TRCEVENTCTL0R			0x020
 #define TRCEVENTCTL1R			0x024
+#define TRCRSR				0x028
 #define TRCSTALLCTLR			0x02C
 #define TRCTSCTLR			0x030
 #define TRCSYNCPR			0x034
@@ -49,6 +50,7 @@
 #define TRCSEQRSTEVR			0x118
 #define TRCSEQSTR			0x11C
 #define TRCEXTINSELR			0x120
+#define TRCEXTINSELRn(n)		(0x120 + (n * 4)) /* n = 0-3 */
 #define TRCCNTRLDVRn(n)			(0x140 + (n * 4)) /* n = 0-3 */
 #define TRCCNTCTLRn(n)			(0x150 + (n * 4)) /* n = 0-3 */
 #define TRCCNTVRn(n)			(0x160 + (n * 4)) /* n = 0-3 */
@@ -160,10 +162,22 @@
 #define CASE_NOP(__unused, x)					\
 	case (x):	/* fall through */
 
+#define ETE_ONLY_SYSREG_LIST(op, val)		\
+	CASE_##op((val), TRCRSR)		\
+	CASE_##op((val), TRCEXTINSELRn(1))	\
+	CASE_##op((val), TRCEXTINSELRn(2))	\
+	CASE_##op((val), TRCEXTINSELRn(3))
+
 /* List of registers accessible via System instructions */
-#define ETM_SYSREG_LIST(op, val)		\
-	CASE_##op((val), TRCPRGCTLR)		\
+#define ETM4x_ONLY_SYSREG_LIST(op, val)		\
 	CASE_##op((val), TRCPROCSELR)		\
+	CASE_##op((val), TRCVDCTLR)		\
+	CASE_##op((val), TRCVDSACCTLR)		\
+	CASE_##op((val), TRCVDARCCTLR)		\
+	CASE_##op((val), TRCOSLAR)
+
+#define ETM_COMMON_SYSREG_LIST(op, val)		\
+	CASE_##op((val), TRCPRGCTLR)		\
 	CASE_##op((val), TRCSTATR)		\
 	CASE_##op((val), TRCCONFIGR)		\
 	CASE_##op((val), TRCAUXCTLR)		\
@@ -180,9 +194,6 @@
 	CASE_##op((val), TRCVIIECTLR)		\
 	CASE_##op((val), TRCVISSCTLR)		\
 	CASE_##op((val), TRCVIPCSSCTLR)		\
-	CASE_##op((val), TRCVDCTLR)		\
-	CASE_##op((val), TRCVDSACCTLR)		\
-	CASE_##op((val), TRCVDARCCTLR)		\
 	CASE_##op((val), TRCSEQEVRn(0))		\
 	CASE_##op((val), TRCSEQEVRn(1))		\
 	CASE_##op((val), TRCSEQEVRn(2))		\
@@ -277,7 +288,6 @@
 	CASE_##op((val), TRCSSPCICRn(5))	\
 	CASE_##op((val), TRCSSPCICRn(6))	\
 	CASE_##op((val), TRCSSPCICRn(7))	\
-	CASE_##op((val), TRCOSLAR)		\
 	CASE_##op((val), TRCOSLSR)		\
 	CASE_##op((val), TRCACVRn(0))		\
 	CASE_##op((val), TRCACVRn(1))		\
@@ -369,12 +379,36 @@
 	CASE_##op((val), TRCPIDR2)		\
 	CASE_##op((val), TRCPIDR3)
 
-#define ETM4x_READ_SYSREG_CASES(res)	ETM_SYSREG_LIST(READ, (res))
-#define ETM4x_WRITE_SYSREG_CASES(val)	ETM_SYSREG_LIST(WRITE, (val))
+#define ETM4x_READ_SYSREG_CASES(res)		\
+	ETM_COMMON_SYSREG_LIST(READ, (res))	\
+	ETM4x_ONLY_SYSREG_LIST(READ, (res))
+
+#define ETM4x_WRITE_SYSREG_CASES(val)		\
+	ETM_COMMON_SYSREG_LIST(WRITE, (val))	\
+	ETM4x_ONLY_SYSREG_LIST(WRITE, (val))
+
+#define ETM_COMMON_SYSREG_LIST_CASES		\
+	ETM_COMMON_SYSREG_LIST(NOP, __unused)
+
+#define ETM4x_SYSREG_LIST_CASES			\
+	ETM_COMMON_SYSREG_LIST_CASES		\
+	ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
 
-#define ETM4x_SYSREG_LIST_CASES		ETM_SYSREG_LIST(NOP, __unused)
 #define ETM4x_MMAP_LIST_CASES		ETM_MMAP_LIST(NOP, __unused)
 
+/* ETE only supports system register access */
+#define ETE_READ_CASES(res)			\
+	ETM_COMMON_SYSREG_LIST(READ, (res))	\
+	ETE_ONLY_SYSREG_LIST(READ, (res))
+
+#define ETE_WRITE_CASES(val)			\
+	ETM_COMMON_SYSREG_LIST(WRITE, (val))	\
+	ETE_ONLY_SYSREG_LIST(WRITE, (val))
+
+#define ETE_ONLY_SYSREG_LIST_CASES		\
+	ETM_COMMON_SYSREG_LIST_CASES		\
+	ETE_ONLY_SYSREG_LIST(NOP, __unused)
+
 #define read_etm4x_sysreg_offset(offset, _64bit)				\
 	({									\
 		u64 __val;							\
-- 
2.7.4


^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH V3 05/14] coresight: ete: Add support for ETE tracing
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
                   ` (3 preceding siblings ...)
  2021-01-27  8:55 ` [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access Anshuman Khandual
@ 2021-01-27  8:55 ` Anshuman Khandual
  2021-02-02 18:56   ` Mathieu Poirier
  2021-01-27  8:55 ` [PATCH V3 06/14] dts: bindings: Document device tree bindings for ETE Anshuman Khandual
                   ` (10 subsequent siblings)
  15 siblings, 1 reply; 90+ messages in thread
From: Anshuman Khandual @ 2021-01-27  8:55 UTC (permalink / raw)
  To: linux-arm-kernel, coresight
  Cc: mathieu.poirier, suzuki.poulose, mike.leach, lcherian,
	linux-kernel, Anshuman Khandual

From: Suzuki K Poulose <suzuki.poulose@arm.com>

Add ETE as one of the supported device types we support
with ETM4x driver. The devices are named following the
existing convention as ete<N>.

ETE mandates that the trace resource status register is programmed
before the tracing is turned on. For the moment simply write to
it indicating TraceActive.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 drivers/hwtracing/coresight/Kconfig                | 10 ++--
 drivers/hwtracing/coresight/coresight-etm4x-core.c | 56 +++++++++++++++++-----
 .../hwtracing/coresight/coresight-etm4x-sysfs.c    | 19 ++++++--
 drivers/hwtracing/coresight/coresight-etm4x.h      | 16 ++++++-
 4 files changed, 79 insertions(+), 22 deletions(-)

diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index 7b44ba2..f154ae7 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -97,15 +97,15 @@ config CORESIGHT_SOURCE_ETM3X
 	  module will be called coresight-etm3x.
 
 config CORESIGHT_SOURCE_ETM4X
-	tristate "CoreSight Embedded Trace Macrocell 4.x driver"
+	tristate "CoreSight ETMv4.x / ETE driver"
 	depends on ARM64
 	select CORESIGHT_LINKS_AND_SINKS
 	select PID_IN_CONTEXTIDR
 	help
-	  This driver provides support for the ETM4.x tracer module, tracing the
-	  instructions that a processor is executing. This is primarily useful
-	  for instruction level tracing. Depending on the implemented version
-	  data tracing may also be available.
+	  This driver provides support for the CoreSight Embedded Trace Macrocell
+	  version 4.x and the Embedded Trace Extensions (ETE). Both are CPU tracer
+	  modules, tracing the instructions that a processor is executing. This is
+	  primarily useful for instruction level tracing.
 
 	  To compile this driver as a module, choose M here: the
 	  module will be called coresight-etm4x.
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 9e92d2a..b40e3c2 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -431,6 +431,13 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 		etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
 	}
 
+	/*
+	 * ETE mandates that the TRCRSR is written to before
+	 * enabling it.
+	 */
+	if (etm4x_is_ete(drvdata))
+		etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
+
 	/* Enable the trace unit */
 	etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
 
@@ -864,13 +871,24 @@ static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
 	 * ETMs implementing sysreg access must implement TRCDEVARCH.
 	 */
 	devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
-	if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH)
+	switch (devarch & ETM_DEVARCH_ID_MASK) {
+	case ETM_DEVARCH_ETMv4x_ARCH:
+		*csa = (struct csdev_access) {
+			.io_mem	= false,
+			.read	= etm4x_sysreg_read,
+			.write	= etm4x_sysreg_write,
+		};
+		break;
+	case ETM_DEVARCH_ETE_ARCH:
+		*csa = (struct csdev_access) {
+			.io_mem	= false,
+			.read	= ete_sysreg_read,
+			.write	= ete_sysreg_write,
+		};
+		break;
+	default:
 		return false;
-	*csa = (struct csdev_access) {
-		.io_mem	= false,
-		.read	= etm4x_sysreg_read,
-		.write	= etm4x_sysreg_write,
-	};
+	}
 
 	drvdata->arch = etm_devarch_to_arch(devarch);
 	return true;
@@ -1808,6 +1826,8 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
 	struct etmv4_drvdata *drvdata;
 	struct coresight_desc desc = { 0 };
 	struct etm4_init_arg init_arg = { 0 };
+	u8 major, minor;
+	char *type_name;
 
 	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 	if (!drvdata)
@@ -1834,10 +1854,6 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
 	if (drvdata->cpu < 0)
 		return drvdata->cpu;
 
-	desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
-	if (!desc.name)
-		return -ENOMEM;
-
 	init_arg.drvdata = drvdata;
 	init_arg.csa = &desc.access;
 	init_arg.pid = etm_pid;
@@ -1853,6 +1869,20 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
 	if (!desc.access.io_mem ||
 	    fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
 		drvdata->skip_power_up = true;
+	major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
+	minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
+	if (etm4x_is_ete(drvdata)) {
+		type_name = "ete";
+		/* ETE v1 has major version == 5. Adjust this for logging.*/
+		major -= 4;
+	} else {
+		type_name = "etm";
+	}
+
+	desc.name = devm_kasprintf(dev, GFP_KERNEL,
+				   "%s%d", type_name, drvdata->cpu);
+	if (!desc.name)
+		return -ENOMEM;
 
 	etm4_init_trace_id(drvdata);
 	etm4_set_default(&drvdata->config);
@@ -1881,9 +1911,8 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
 
 	etmdrvdata[drvdata->cpu] = drvdata;
 
-	dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n",
-		 drvdata->cpu, ETM_ARCH_MAJOR_VERSION(drvdata->arch),
-		 ETM_ARCH_MINOR_VERSION(drvdata->arch));
+	dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
+		 drvdata->cpu, type_name, major, minor);
 
 	if (boot_enable) {
 		coresight_enable(drvdata->csdev);
@@ -2027,6 +2056,7 @@ static struct amba_driver etm4x_amba_driver = {
 
 static const struct of_device_id etm4_sysreg_match[] = {
 	{ .compatible	= "arm,coresight-etm4x-sysreg" },
+	{ .compatible	= "arm,embedded-trace-extension" },
 	{}
 };
 
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index b646d53..1c490bc 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -2374,12 +2374,20 @@ static inline bool
 etm4x_register_implemented(struct etmv4_drvdata *drvdata, u32 offset)
 {
 	switch (offset) {
-	ETM4x_SYSREG_LIST_CASES
+	ETM_COMMON_SYSREG_LIST_CASES
 		/*
-		 * Registers accessible via system instructions are always
-		 * implemented.
+		 * Common registers to ETE & ETM4x accessible via system
+		 * instructions are always implemented.
 		 */
 		return true;
+
+	ETM4x_ONLY_SYSREG_LIST_CASES
+		/*
+		 * We only support etm4x and ete. So if the device is not
+		 * ETE, it must be ETMv4x.
+		 */
+		return !etm4x_is_ete(drvdata);
+
 	ETM4x_MMAP_LIST_CASES
 		/*
 		 * Registers accessible only via memory-mapped registers
@@ -2389,8 +2397,13 @@ etm4x_register_implemented(struct etmv4_drvdata *drvdata, u32 offset)
 		 * coresight_register() and the csdev is not initialized
 		 * until that is done. So rely on the drvdata->base to
 		 * detect if we have a memory mapped access.
+		 * Also ETE doesn't implement memory mapped access, thus
+		 * it is sufficient to check that we are using mmio.
 		 */
 		return !!drvdata->base;
+
+	ETE_ONLY_SYSREG_LIST_CASES
+		return etm4x_is_ete(drvdata);
 	}
 
 	return false;
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index ca24ac5..8b90de5 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -128,6 +128,8 @@
 #define TRCCIDR2			0xFF8
 #define TRCCIDR3			0xFFC
 
+#define TRCRSR_TA			BIT(12)
+
 /*
  * System instructions to access ETM registers.
  * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
@@ -390,6 +392,9 @@
 #define ETM_COMMON_SYSREG_LIST_CASES		\
 	ETM_COMMON_SYSREG_LIST(NOP, __unused)
 
+#define ETM4x_ONLY_SYSREG_LIST_CASES		\
+	ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
+
 #define ETM4x_SYSREG_LIST_CASES			\
 	ETM_COMMON_SYSREG_LIST_CASES		\
 	ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
@@ -406,7 +411,6 @@
 	ETE_ONLY_SYSREG_LIST(WRITE, (val))
 
 #define ETE_ONLY_SYSREG_LIST_CASES		\
-	ETM_COMMON_SYSREG_LIST_CASES		\
 	ETE_ONLY_SYSREG_LIST(NOP, __unused)
 
 #define read_etm4x_sysreg_offset(offset, _64bit)				\
@@ -589,11 +593,14 @@
 	((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13))
 
 #define ETM_DEVARCH_ARCHID_ETMv4x		ETM_DEVARCH_MAKE_ARCHID(0x4)
+#define ETM_DEVARCH_ARCHID_ETE			ETM_DEVARCH_MAKE_ARCHID(0x5)
 
 #define ETM_DEVARCH_ID_MASK						\
 	(ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT)
 #define ETM_DEVARCH_ETMv4x_ARCH						\
 	(ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT)
+#define ETM_DEVARCH_ETE_ARCH						\
+	(ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT)
 
 #define TRCSTATR_IDLE_BIT		0
 #define TRCSTATR_PMSTABLE_BIT		1
@@ -683,6 +690,8 @@
 #define ETM_ARCH_MINOR_VERSION(arch)	((arch) & 0xfU)
 
 #define ETM_ARCH_V4	ETM_ARCH_VERSION(4, 0)
+#define ETM_ARCH_ETE	ETM_ARCH_VERSION(5, 0)
+
 /* Interpretation of resource numbers change at ETM v4.3 architecture */
 #define ETM_ARCH_V4_3	ETM_ARCH_VERSION(4, 3)
 
@@ -989,4 +998,9 @@ void etm4_config_trace_mode(struct etmv4_config *config);
 
 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit);
 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit);
+
+static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata)
+{
+	return drvdata->arch >= ETM_ARCH_ETE;
+}
 #endif
-- 
2.7.4


^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH V3 06/14] dts: bindings: Document device tree bindings for ETE
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
                   ` (4 preceding siblings ...)
  2021-01-27  8:55 ` [PATCH V3 05/14] coresight: ete: Add support for ETE tracing Anshuman Khandual
@ 2021-01-27  8:55 ` Anshuman Khandual
  2021-02-09 19:00   ` Rob Herring
  2021-01-27  8:55 ` [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles Anshuman Khandual
                   ` (9 subsequent siblings)
  15 siblings, 1 reply; 90+ messages in thread
From: Anshuman Khandual @ 2021-01-27  8:55 UTC (permalink / raw)
  To: linux-arm-kernel, coresight
  Cc: mathieu.poirier, suzuki.poulose, mike.leach, lcherian,
	linux-kernel, Anshuman Khandual, devicetree, Rob Herring

From: Suzuki K Poulose <suzuki.poulose@arm.com>

Document the device tree bindings for Embedded Trace Extensions.
ETE can be connected to legacy coresight components and thus
could optionally contain a connection graph as described by
the CoreSight bindings.

Cc: devicetree@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
Changes in V3:

- Fixed all DT yaml semantics problems

 Documentation/devicetree/bindings/arm/ete.yaml | 74 ++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/ete.yaml

diff --git a/Documentation/devicetree/bindings/arm/ete.yaml b/Documentation/devicetree/bindings/arm/ete.yaml
new file mode 100644
index 0000000..edc1fe2
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/ete.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+# Copyright 2021, Arm Ltd
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/ete.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: ARM Embedded Trace Extensions
+
+maintainers:
+  - Suzuki K Poulose <suzuki.poulose@arm.com>
+  - Mathieu Poirier <mathieu.poirier@linaro.org>
+
+description: |
+  Arm Embedded Trace Extension(ETE) is a per CPU trace component that
+  allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
+  architecture and has extended support for future architecture changes.
+  The trace generated by the ETE could be stored via legacy CoreSight
+  components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
+  Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
+  legacy CoreSight components, a node must be listed per instance, along
+  with any optional connection graph as per the coresight bindings.
+  See bindings/arm/coresight.txt.
+
+properties:
+  $nodename:
+    pattern: "^ete([0-9a-f]+)$"
+  compatible:
+    items:
+      - const: arm,embedded-trace-extension
+
+  cpu:
+    description: |
+      Handle to the cpu this ETE is bound to.
+    $ref: /schemas/types.yaml#/definitions/phandle
+
+  out-ports:
+    type: object
+    description: |
+      Output connections from the ETE to legacy CoreSight trace bus.
+    properties:
+      port:
+        $ref: /schemas/graph.yaml#/properties/port
+
+required:
+  - compatible
+  - cpu
+
+additionalProperties: false
+
+examples:
+
+# An ETE node without legacy CoreSight connections
+  - |
+    ete0 {
+      compatible = "arm,embedded-trace-extension";
+      cpu = <&cpu_0>;
+    };
+# An ETE node with legacy CoreSight connections
+  - |
+   ete1 {
+      compatible = "arm,embedded-trace-extension";
+      cpu = <&cpu_1>;
+
+      out-ports {        /* legacy coresight connection */
+         port {
+             ete1_out_port: endpoint {
+                remote-endpoint = <&funnel_in_port0>;
+             };
+         };
+      };
+   };
+
+...
-- 
2.7.4


^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
                   ` (5 preceding siblings ...)
  2021-01-27  8:55 ` [PATCH V3 06/14] dts: bindings: Document device tree bindings for ETE Anshuman Khandual
@ 2021-01-27  8:55 ` Anshuman Khandual
  2021-02-03 19:05   ` Mathieu Poirier
  2021-02-15 16:27   ` Mike Leach
  2021-01-27  8:55 ` [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual
                   ` (8 subsequent siblings)
  15 siblings, 2 replies; 90+ messages in thread
From: Anshuman Khandual @ 2021-01-27  8:55 UTC (permalink / raw)
  To: linux-arm-kernel, coresight
  Cc: mathieu.poirier, suzuki.poulose, mike.leach, lcherian,
	linux-kernel, Anshuman Khandual, Leo Yan

From: Suzuki K Poulose <suzuki.poulose@arm.com>

The context associated with an ETM for a given perf event
includes :
  - handle -> the perf output handle for the AUX buffer.
  - the path for the trace components
  - the buffer config for the sink.

The path and the buffer config are part of the "aux_priv" data
(etm_event_data) setup by the setup_aux() callback, and made available
via perf_get_aux(handle).

Now with a sink supporting IRQ, the sink could "end" an output
handle when the buffer reaches the programmed limit and would try
to restart a handle. This could fail if there is not enough
space left the AUX buffer (e.g, the userspace has not consumed
the data). This leaves the "handle" disconnected from the "event"
and also the "perf_get_aux()" cleared. This all happens within
the sink driver, without the etm_perf driver being aware.
Now when the event is actually stopped, etm_event_stop()
will need to access the "event_data". But since the handle
is not valid anymore, we loose the information to stop the
"trace" path. So, we need a reliable way to access the etm_event_data
even when the handle may not be active.

This patch replaces the per_cpu handle array with a per_cpu context
for the ETM, which tracks the "handle" as well as the "etm_event_data".
The context notes the etm_event_data at etm_event_start() and clears
it at etm_event_stop(). This makes sure that we don't access a
stale "etm_event_data" as we are guaranteed that it is not
freed by free_aux() as long as the event is active and tracing,
also provides us with access to the critical information
needed to wind up a session even in the absence of an active
output_handle.

This is not an issue for the legacy sinks as none of them supports
an IRQ and is centrally handled by the etm-perf.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 drivers/hwtracing/coresight/coresight-etm-perf.c | 45 +++++++++++++++++++++---
 1 file changed, 40 insertions(+), 5 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
index eb9e7e9..a3977b0 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -24,7 +24,26 @@
 static struct pmu etm_pmu;
 static bool etm_perf_up;
 
-static DEFINE_PER_CPU(struct perf_output_handle, ctx_handle);
+/*
+ * An ETM context for a running event includes the perf aux handle
+ * and aux_data. For ETM, the aux_data (etm_event_data), consists of
+ * the trace path and the sink configuration. The event data is accessible
+ * via perf_get_aux(handle). However, a sink could "end" a perf output
+ * handle via the IRQ handler. And if the "sink" encounters a failure
+ * to "begin" another session (e.g due to lack of space in the buffer),
+ * the handle will be cleared. Thus, the event_data may not be accessible
+ * from the handle when we get to the etm_event_stop(), which is required
+ * for stopping the trace path. The event_data is guaranteed to stay alive
+ * until "free_aux()", which cannot happen as long as the event is active on
+ * the ETM. Thus the event_data for the session must be part of the ETM context
+ * to make sure we can disable the trace path.
+ */
+struct etm_ctxt {
+	struct perf_output_handle handle;
+	struct etm_event_data *event_data;
+};
+
+static DEFINE_PER_CPU(struct etm_ctxt, etm_ctxt);
 static DEFINE_PER_CPU(struct coresight_device *, csdev_src);
 
 /* ETMv3.5/PTM's ETMCR is 'config' */
@@ -332,7 +351,8 @@ static void etm_event_start(struct perf_event *event, int flags)
 {
 	int cpu = smp_processor_id();
 	struct etm_event_data *event_data;
-	struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle);
+	struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
+	struct perf_output_handle *handle = &ctxt->handle;
 	struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
 	struct list_head *path;
 
@@ -374,6 +394,8 @@ static void etm_event_start(struct perf_event *event, int flags)
 	if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF))
 		goto fail_disable_path;
 
+	/* Save the event_data for this ETM */
+	ctxt->event_data = event_data;
 out:
 	return;
 
@@ -392,13 +414,20 @@ static void etm_event_stop(struct perf_event *event, int mode)
 	int cpu = smp_processor_id();
 	unsigned long size;
 	struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
-	struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle);
-	struct etm_event_data *event_data = perf_get_aux(handle);
+	struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
+	struct perf_output_handle *handle = &ctxt->handle;
+	struct etm_event_data *event_data = ctxt->event_data;
 	struct list_head *path;
 
+	/* Clear the event_data as this ETM is stopping the trace. */
+	ctxt->event_data = NULL;
 	if (event->hw.state == PERF_HES_STOPPED)
 		return;
 
+	/* We must have a valid event_data for a running event */
+	if (WARN_ON(!event_data))
+		return;
+
 	if (!csdev)
 		return;
 
@@ -416,7 +445,13 @@ static void etm_event_stop(struct perf_event *event, int mode)
 	/* tell the core */
 	event->hw.state = PERF_HES_STOPPED;
 
-	if (mode & PERF_EF_UPDATE) {
+	/*
+	 * If the handle is not bound to an event anymore
+	 * (e.g, the sink driver was unable to restart the
+	 * handle due to lack of buffer space), we don't
+	 * have to do anything here.
+	 */
+	if (handle->event && (mode & PERF_EF_UPDATE)) {
 		if (WARN_ON_ONCE(handle->event != event))
 			return;
 
-- 
2.7.4


^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
                   ` (6 preceding siblings ...)
  2021-01-27  8:55 ` [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles Anshuman Khandual
@ 2021-01-27  8:55 ` Anshuman Khandual
  2021-01-28  9:16   ` Suzuki K Poulose
  2021-02-15 16:27   ` Mike Leach
  2021-01-27  8:55 ` [PATCH V3 09/14] arm64: Add TRBE definitions Anshuman Khandual
                   ` (7 subsequent siblings)
  15 siblings, 2 replies; 90+ messages in thread
From: Anshuman Khandual @ 2021-01-27  8:55 UTC (permalink / raw)
  To: linux-arm-kernel, coresight
  Cc: mathieu.poirier, suzuki.poulose, mike.leach, lcherian,
	linux-kernel, Anshuman Khandual

Add support for dedicated sinks that are bound to individual CPUs. (e.g,
TRBE). To allow quicker access to the sink for a given CPU bound source,
keep a percpu array of the sink devices. Also, add support for building
a path to the CPU local sink from the ETM.

This adds a new percpu sink type CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM.
This new sink type is exclusively available and can only work with percpu
source type device CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC.

This defines a percpu structure that accommodates a single coresight_device
which can be used to store an initialized instance from a sink driver. As
these sinks are exclusively linked and dependent on corresponding percpu
sources devices, they should also be the default sink device during a perf
session.

Outwards device connections are scanned while establishing paths between a
source and a sink device. But such connections are not present for certain
percpu source and sink devices which are exclusively linked and dependent.
Build the path directly and skip connection scanning for such devices.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
Changes in V3:

- Updated coresight_find_default_sink()

 drivers/hwtracing/coresight/coresight-core.c | 16 ++++++++++++++--
 include/linux/coresight.h                    | 12 ++++++++++++
 2 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
index 0062c89..4795e28 100644
--- a/drivers/hwtracing/coresight/coresight-core.c
+++ b/drivers/hwtracing/coresight/coresight-core.c
@@ -23,6 +23,7 @@
 #include "coresight-priv.h"
 
 static DEFINE_MUTEX(coresight_mutex);
+DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
 
 /**
  * struct coresight_node - elements of a path, from source to sink
@@ -784,6 +785,13 @@ static int _coresight_build_path(struct coresight_device *csdev,
 	if (csdev == sink)
 		goto out;
 
+	if (coresight_is_percpu_source(csdev) && coresight_is_percpu_sink(sink) &&
+	    sink == per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev))) {
+		_coresight_build_path(sink, sink, path);
+		found = true;
+		goto out;
+	}
+
 	/* Not a sink - recursively explore each port found on this element */
 	for (i = 0; i < csdev->pdata->nr_outport; i++) {
 		struct coresight_device *child_dev;
@@ -999,8 +1007,12 @@ coresight_find_default_sink(struct coresight_device *csdev)
 	int depth = 0;
 
 	/* look for a default sink if we have not found for this device */
-	if (!csdev->def_sink)
-		csdev->def_sink = coresight_find_sink(csdev, &depth);
+	if (!csdev->def_sink) {
+		if (coresight_is_percpu_source(csdev))
+			csdev->def_sink = per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev));
+		if (!csdev->def_sink)
+			csdev->def_sink = coresight_find_sink(csdev, &depth);
+	}
 	return csdev->def_sink;
 }
 
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 976ec26..bc3a5ca 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -50,6 +50,7 @@ enum coresight_dev_subtype_sink {
 	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
 	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
 	CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
+	CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
 };
 
 enum coresight_dev_subtype_link {
@@ -428,6 +429,17 @@ static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 o
 		csa->write(val, offset, false, true);
 }
 
+static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
+{
+	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
+	       csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
+}
+
+static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
+{
+	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
+	       csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
+}
 #else	/* !CONFIG_64BIT */
 
 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
-- 
2.7.4


^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH V3 09/14] arm64: Add TRBE definitions
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
                   ` (7 preceding siblings ...)
  2021-01-27  8:55 ` [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual
@ 2021-01-27  8:55 ` Anshuman Khandual
  2021-01-28  9:31   ` Suzuki K Poulose
  2021-01-28 17:18   ` Catalin Marinas
  2021-01-27  8:55 ` [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1 Anshuman Khandual
                   ` (6 subsequent siblings)
  15 siblings, 2 replies; 90+ messages in thread
From: Anshuman Khandual @ 2021-01-27  8:55 UTC (permalink / raw)
  To: linux-arm-kernel, coresight
  Cc: mathieu.poirier, suzuki.poulose, mike.leach, lcherian,
	linux-kernel, Anshuman Khandual

This adds TRBE related registers and corresponding feature macros.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
Changes in V3:

- ID_AA64DFR0_TRBE_SHIFT has been moved here from the TRBE driver
- Changed TRBLIMITR_TRIG_MODE_SHIFT as 3

 arch/arm64/include/asm/sysreg.h | 50 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 4acff97..85ae4db 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -329,6 +329,55 @@
 
 /*** End of Statistical Profiling Extension ***/
 
+/*
+ * TRBE Registers
+ */
+#define SYS_TRBLIMITR_EL1		sys_reg(3, 0, 9, 11, 0)
+#define SYS_TRBPTR_EL1			sys_reg(3, 0, 9, 11, 1)
+#define SYS_TRBBASER_EL1		sys_reg(3, 0, 9, 11, 2)
+#define SYS_TRBSR_EL1			sys_reg(3, 0, 9, 11, 3)
+#define SYS_TRBMAR_EL1			sys_reg(3, 0, 9, 11, 4)
+#define SYS_TRBTRG_EL1			sys_reg(3, 0, 9, 11, 6)
+#define SYS_TRBIDR_EL1			sys_reg(3, 0, 9, 11, 7)
+
+#define TRBLIMITR_LIMIT_MASK		GENMASK_ULL(51, 0)
+#define TRBLIMITR_LIMIT_SHIFT		12
+#define TRBLIMITR_NVM			BIT(5)
+#define TRBLIMITR_TRIG_MODE_MASK	GENMASK(1, 0)
+#define TRBLIMITR_TRIG_MODE_SHIFT	3
+#define TRBLIMITR_FILL_MODE_MASK	GENMASK(1, 0)
+#define TRBLIMITR_FILL_MODE_SHIFT	1
+#define TRBLIMITR_ENABLE		BIT(0)
+#define TRBPTR_PTR_MASK			GENMASK_ULL(63, 0)
+#define TRBPTR_PTR_SHIFT		0
+#define TRBBASER_BASE_MASK		GENMASK_ULL(51, 0)
+#define TRBBASER_BASE_SHIFT		12
+#define TRBSR_EC_MASK			GENMASK(5, 0)
+#define TRBSR_EC_SHIFT			26
+#define TRBSR_IRQ			BIT(22)
+#define TRBSR_TRG			BIT(21)
+#define TRBSR_WRAP			BIT(20)
+#define TRBSR_ABORT			BIT(18)
+#define TRBSR_STOP			BIT(17)
+#define TRBSR_MSS_MASK			GENMASK(15, 0)
+#define TRBSR_MSS_SHIFT			0
+#define TRBSR_BSC_MASK			GENMASK(5, 0)
+#define TRBSR_BSC_SHIFT			0
+#define TRBSR_FSC_MASK			GENMASK(5, 0)
+#define TRBSR_FSC_SHIFT			0
+#define TRBMAR_SHARE_MASK		GENMASK(1, 0)
+#define TRBMAR_SHARE_SHIFT		8
+#define TRBMAR_OUTER_MASK		GENMASK(3, 0)
+#define TRBMAR_OUTER_SHIFT		4
+#define TRBMAR_INNER_MASK		GENMASK(3, 0)
+#define TRBMAR_INNER_SHIFT		0
+#define TRBTRG_TRG_MASK			GENMASK(31, 0)
+#define TRBTRG_TRG_SHIFT		0
+#define TRBIDR_FLAG			BIT(5)
+#define TRBIDR_PROG			BIT(4)
+#define TRBIDR_ALIGN_MASK		GENMASK(3, 0)
+#define TRBIDR_ALIGN_SHIFT		0
+
 #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
 #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
 
@@ -831,6 +880,7 @@
 #define ID_AA64MMFR2_CNP_SHIFT		0
 
 /* id_aa64dfr0 */
+#define ID_AA64DFR0_TRBE_SHIFT		44
 #define ID_AA64DFR0_TRACE_FILT_SHIFT	40
 #define ID_AA64DFR0_DOUBLELOCK_SHIFT	36
 #define ID_AA64DFR0_PMSVER_SHIFT	32
-- 
2.7.4


^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
                   ` (8 preceding siblings ...)
  2021-01-27  8:55 ` [PATCH V3 09/14] arm64: Add TRBE definitions Anshuman Khandual
@ 2021-01-27  8:55 ` Anshuman Khandual
  2021-01-27  9:58   ` Marc Zyngier
  2021-01-27  8:55 ` [PATCH V3 11/14] coresight: sink: Add TRBE driver Anshuman Khandual
                   ` (5 subsequent siblings)
  15 siblings, 1 reply; 90+ messages in thread
From: Anshuman Khandual @ 2021-01-27  8:55 UTC (permalink / raw)
  To: linux-arm-kernel, coresight
  Cc: mathieu.poirier, suzuki.poulose, mike.leach, lcherian,
	linux-kernel, Anshuman Khandual, Will Deacon, Catalin Marinas,
	Marc Zyngier, Mark Rutland

From: Suzuki K Poulose <suzuki.poulose@arm.com>

When the kernel is booted at EL2 in a nvhe configuration,
enable the TRBE access to the EL1. The EL1 still can't trace
EL2, unless EL2 permits explicitly via TRFCR_EL2.E2TRE.

Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
cc: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/include/asm/el2_setup.h | 19 +++++++++++++++++++
 arch/arm64/include/asm/kvm_arm.h   |  2 ++
 2 files changed, 21 insertions(+)

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index a7f5a1b..05ecce9 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -72,6 +72,25 @@
 .endif
 
 3:
+
+.ifeqs	"\mode", "nvhe"
+	/*
+	 * If the Trace Buffer is available, allow
+	 * the EL1 to own it. Note that EL1 cannot
+	 * trace the EL2, as it is prevented by
+	 * TRFCR_EL2.E2TRE == 0.
+	 */
+	ubfx	x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4
+	cbz	x0, 1f
+
+	mrs_s	x0, SYS_TRBIDR_EL1
+	and	x0, x0, TRBIDR_PROG
+	cbnz	x0, 1f
+	mov	x0, #(MDCR_EL2_E2TB_EL1_OWN << MDCR_EL2_E2TB_SHIFT)
+	orr	x2, x2, x0
+.endif
+
+1:
 	msr	mdcr_el2, x2			// Configure debug traps
 .endm
 
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 4e90c2d..ed8b789 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -281,6 +281,8 @@
 #define MDCR_EL2_TPMS		(1 << 14)
 #define MDCR_EL2_E2PB_MASK	(UL(0x3))
 #define MDCR_EL2_E2PB_SHIFT	(UL(12))
+#define MDCR_EL2_E2TB_EL1_OWN	(UL(0x3))
+#define MDCR_EL2_E2TB_SHIFT	(UL(24))
 #define MDCR_EL2_TDRA		(1 << 11)
 #define MDCR_EL2_TDOSA		(1 << 10)
 #define MDCR_EL2_TDA		(1 << 9)
-- 
2.7.4


^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
                   ` (9 preceding siblings ...)
  2021-01-27  8:55 ` [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1 Anshuman Khandual
@ 2021-01-27  8:55 ` Anshuman Khandual
       [not found]   ` <12cdc8ca-0a69-bfba-bbcd-fb392d6ca051@arm.com>
                     ` (4 more replies)
  2021-01-27  8:55 ` [PATCH V3 12/14] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual
                   ` (4 subsequent siblings)
  15 siblings, 5 replies; 90+ messages in thread
From: Anshuman Khandual @ 2021-01-27  8:55 UTC (permalink / raw)
  To: linux-arm-kernel, coresight
  Cc: mathieu.poirier, suzuki.poulose, mike.leach, lcherian,
	linux-kernel, Anshuman Khandual

Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
accessible via the system registers. The TRBE supports different addressing
modes including CPU virtual address and buffer modes including the circular
buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
access to the trace buffer could be prohibited by a higher exception level
(EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
private interrupt (PPI) on address translation errors and when the buffer
is full. Overall implementation here is inspired from the Arm SPE driver.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
Changes in V3:

- Added new DT bindings document TRBE.yaml
- Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3
- Dropped isb() from trbe_reset_local()
- Dropped gap between (void *) and buf->trbe_base
- Changed 'int' to 'unsigned int' in is_trbe_available()
- Dropped unused function set_trbe_running(), set_trbe_virtual_mode(),
  set_trbe_enabled() and set_trbe_limit_pointer()
- Changed get_trbe_flag_update(), is_trbe_programmable() and
  get_trbe_address_align() to accept TRBIDR value
- Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), is_trbe_trg(),
  is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value
- Dropped snapshot mode condition in arm_trbe_alloc_buffer()
- Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled
- Compute trbe_limit before trbe_write to get the updated handle
- Added trbe_stop_and_truncate_event()
- Dropped trbe_handle_fatal()

 Documentation/trace/coresight/coresight-trbe.rst |   39 +
 arch/arm64/include/asm/sysreg.h                  |    1 +
 drivers/hwtracing/coresight/Kconfig              |   11 +
 drivers/hwtracing/coresight/Makefile             |    1 +
 drivers/hwtracing/coresight/coresight-trbe.c     | 1023 ++++++++++++++++++++++
 drivers/hwtracing/coresight/coresight-trbe.h     |  160 ++++
 6 files changed, 1235 insertions(+)
 create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
 create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
 create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h

diff --git a/Documentation/trace/coresight/coresight-trbe.rst b/Documentation/trace/coresight/coresight-trbe.rst
new file mode 100644
index 0000000..1cbb819
--- /dev/null
+++ b/Documentation/trace/coresight/coresight-trbe.rst
@@ -0,0 +1,39 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+==============================
+Trace Buffer Extension (TRBE).
+==============================
+
+    :Author:   Anshuman Khandual <anshuman.khandual@arm.com>
+    :Date:     November 2020
+
+Hardware Description
+--------------------
+
+Trace Buffer Extension (TRBE) is a percpu hardware which captures in system
+memory, CPU traces generated from a corresponding percpu tracing unit. This
+gets plugged in as a coresight sink device because the corresponding trace
+genarators (ETE), are plugged in as source device.
+
+The TRBE is not compliant to CoreSight architecture specifications, but is
+driven via the CoreSight driver framework to support the ETE (which is
+CoreSight compliant) integration.
+
+Sysfs files and directories
+---------------------------
+
+The TRBE devices appear on the existing coresight bus alongside the other
+coresight devices::
+
+	>$ ls /sys/bus/coresight/devices
+	trbe0  trbe1  trbe2 trbe3
+
+The ``trbe<N>`` named TRBEs are associated with a CPU.::
+
+	>$ ls /sys/bus/coresight/devices/trbe0/
+        align dbm
+
+*Key file items are:-*
+   * ``align``: TRBE write pointer alignment
+   * ``dbm``: TRBE updates memory with access and dirty flags
+
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 85ae4db..9e2e9b7 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -97,6 +97,7 @@
 #define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
 #define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
 #define SET_PSTATE_TCO(x)		__emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
+#define TSB_CSYNC			__emit_inst(0xd503225f)
 
 #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
 #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index f154ae7..aa657ab 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -164,6 +164,17 @@ config CORESIGHT_CTI
 	  To compile this driver as a module, choose M here: the
 	  module will be called coresight-cti.
 
+config CORESIGHT_TRBE
+	bool "Trace Buffer Extension (TRBE) driver"
+	depends on ARM64
+	help
+	  This driver provides support for percpu Trace Buffer Extension (TRBE).
+	  TRBE always needs to be used along with it's corresponding percpu ETE
+	  component. ETE generates trace data which is then captured with TRBE.
+	  Unlike traditional sink devices, TRBE is a CPU feature accessible via
+	  system registers. But it's explicit dependency with trace unit (ETE)
+	  requires it to be plugged in as a coresight sink device.
+
 config CORESIGHT_CTI_INTEGRATION_REGS
 	bool "Access CTI CoreSight Integration Registers"
 	depends on CORESIGHT_CTI
diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
index f20e357..d608165 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -21,5 +21,6 @@ obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
 obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
 obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
 obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
+obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
 coresight-cti-y := coresight-cti-core.o	coresight-cti-platform.o \
 		   coresight-cti-sysfs.o
diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
new file mode 100644
index 0000000..1464d8b
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-trbe.c
@@ -0,0 +1,1023 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This driver enables Trace Buffer Extension (TRBE) as a per-cpu coresight
+ * sink device could then pair with an appropriate per-cpu coresight source
+ * device (ETE) thus generating required trace data. Trace can be enabled
+ * via the perf framework.
+ *
+ * Copyright (C) 2020 ARM Ltd.
+ *
+ * Author: Anshuman Khandual <anshuman.khandual@arm.com>
+ */
+#define DRVNAME "arm_trbe"
+
+#define pr_fmt(fmt) DRVNAME ": " fmt
+
+#include "coresight-trbe.h"
+
+#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
+
+/*
+ * A padding packet that will help the user space tools
+ * in skipping relevant sections in the captured trace
+ * data which could not be decoded. TRBE doesn't support
+ * formatting the trace data, unlike the legacy CoreSight
+ * sinks and thus we use ETE trace packets to pad the
+ * sections of the buffer.
+ */
+#define ETE_IGNORE_PACKET 		0x70
+
+/*
+ * Minimum amount of meaningful trace will contain:
+ * A-Sync, Trace Info, Trace On, Address, Atom.
+ * This is about 44bytes of ETE trace. To be on
+ * the safer side, we assume 64bytes is the minimum
+ * space required for a meaningful session, before
+ * we hit a "WRAP" event.
+ */
+#define TRBE_TRACE_MIN_BUF_SIZE		64
+
+enum trbe_fault_action {
+	TRBE_FAULT_ACT_WRAP,
+	TRBE_FAULT_ACT_SPURIOUS,
+	TRBE_FAULT_ACT_FATAL,
+};
+
+struct trbe_buf {
+	unsigned long trbe_base;
+	unsigned long trbe_limit;
+	unsigned long trbe_write;
+	int nr_pages;
+	void **pages;
+	bool snapshot;
+	struct trbe_cpudata *cpudata;
+};
+
+struct trbe_cpudata {
+	bool trbe_dbm;
+	u64 trbe_align;
+	int cpu;
+	enum cs_mode mode;
+	struct trbe_buf *buf;
+	struct trbe_drvdata *drvdata;
+};
+
+struct trbe_drvdata {
+	struct trbe_cpudata __percpu *cpudata;
+	struct perf_output_handle __percpu **handle;
+	struct hlist_node hotplug_node;
+	int irq;
+	cpumask_t supported_cpus;
+	enum cpuhp_state trbe_online;
+	struct platform_device *pdev;
+};
+
+static int trbe_alloc_node(struct perf_event *event)
+{
+	if (event->cpu == -1)
+		return NUMA_NO_NODE;
+	return cpu_to_node(event->cpu);
+}
+
+static void trbe_drain_buffer(void)
+{
+	asm(TSB_CSYNC);
+	dsb(nsh);
+}
+
+static void trbe_drain_and_disable_local(void)
+{
+	trbe_drain_buffer();
+	write_sysreg_s(0, SYS_TRBLIMITR_EL1);
+	isb();
+}
+
+static void trbe_reset_local(void)
+{
+	trbe_drain_and_disable_local();
+	write_sysreg_s(0, SYS_TRBPTR_EL1);
+	write_sysreg_s(0, SYS_TRBBASER_EL1);
+	write_sysreg_s(0, SYS_TRBSR_EL1);
+}
+
+static void trbe_stop_and_truncate_event(struct perf_output_handle *handle)
+{
+	struct trbe_buf *buf = etm_perf_sink_config(handle);
+
+	/*
+	 * We cannot proceed with the buffer collection and we
+	 * do not have any data for the current session. The
+	 * etm_perf driver expects to close out the aux_buffer
+	 * at event_stop(). So disable the TRBE here and leave
+	 * the update_buffer() to return a 0 size.
+	 */
+	trbe_drain_and_disable_local();
+	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+	*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
+}
+
+/*
+ * TRBE Buffer Management
+ *
+ * The TRBE buffer spans from the base pointer till the limit pointer. When enabled,
+ * it starts writing trace data from the write pointer onward till the limit pointer.
+ * When the write pointer reaches the address just before the limit pointer, it gets
+ * wrapped around again to the base pointer. This is called a TRBE wrap event, which
+ * generates a maintenance interrupt when operated in WRAP or FILL mode. This driver
+ * uses FILL mode, where the TRBE stops the trace collection at wrap event. The IRQ
+ * handler updates the AUX buffer and re-enables the TRBE with updated WRITE and
+ * LIMIT pointers.
+ *
+ *	Wrap around with an IRQ
+ *	------ < ------ < ------- < ----- < -----
+ *	|					|
+ *	------ > ------ > ------- > ----- > -----
+ *
+ *	+---------------+-----------------------+
+ *	|		|			|
+ *	+---------------+-----------------------+
+ *	Base Pointer	Write Pointer		Limit Pointer
+ *
+ * The base and limit pointers always needs to be PAGE_SIZE aligned. But the write
+ * pointer can be aligned to the implementation defined TRBE trace buffer alignment
+ * as captured in trbe_cpudata->trbe_align.
+ *
+ *
+ *		head		tail		wakeup
+ *	+---------------------------------------+----- ~ ~ ------
+ *	|$$$$$$$|################|$$$$$$$$$$$$$$|		|
+ *	+---------------------------------------+----- ~ ~ ------
+ *	Base Pointer	Write Pointer		Limit Pointer
+ *
+ * The perf_output_handle indices (head, tail, wakeup) are monotonically increasing
+ * values which tracks all the driver writes and user reads from the perf auxiliary
+ * buffer. Generally [head..tail] is the area where the driver can write into unless
+ * the wakeup is behind the tail. Enabled TRBE buffer span needs to be adjusted and
+ * configured depending on the perf_output_handle indices, so that the driver does
+ * not override into areas in the perf auxiliary buffer which is being or yet to be
+ * consumed from the user space. The enabled TRBE buffer area is a moving subset of
+ * the allocated perf auxiliary buffer.
+ */
+static void trbe_pad_buf(struct perf_output_handle *handle, int len)
+{
+	struct trbe_buf *buf = etm_perf_sink_config(handle);
+	u64 head = PERF_IDX2OFF(handle->head, buf);
+
+	memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
+	if (!buf->snapshot)
+		perf_aux_output_skip(handle, len);
+}
+
+static unsigned long trbe_snapshot_offset(struct perf_output_handle *handle)
+{
+	struct trbe_buf *buf = etm_perf_sink_config(handle);
+
+	/*
+	 * The ETE trace has alignment synchronization packets allowing
+	 * the decoder to reset in case of an overflow or corruption.
+	 * So we can use the entire buffer for the snapshot mode.
+	 */
+	return buf->nr_pages * PAGE_SIZE;
+}
+
+/*
+ * TRBE Limit Calculation
+ *
+ * The following markers are used to illustrate various TRBE buffer situations.
+ *
+ * $$$$ - Data area, unconsumed captured trace data, not to be overridden
+ * #### - Free area, enabled, trace will be written
+ * %%%% - Free area, disabled, trace will not be written
+ * ==== - Free area, padded with ETE_IGNORE_PACKET, trace will be skipped
+ */
+static unsigned long __trbe_normal_offset(struct perf_output_handle *handle)
+{
+	struct trbe_buf *buf = etm_perf_sink_config(handle);
+	struct trbe_cpudata *cpudata = buf->cpudata;
+	const u64 bufsize = buf->nr_pages * PAGE_SIZE;
+	u64 limit = bufsize;
+	u64 head, tail, wakeup;
+
+	head = PERF_IDX2OFF(handle->head, buf);
+
+	/*
+	 *		head
+	 *	------->|
+	 *	|
+	 *	head	TRBE align	tail
+	 * +----|-------|---------------|-------+
+	 * |$$$$|=======|###############|$$$$$$$|
+	 * +----|-------|---------------|-------+
+	 * trbe_base				trbe_base + nr_pages
+	 *
+	 * Perf aux buffer output head position can be misaligned depending on
+	 * various factors including user space reads. In case misaligned, head
+	 * needs to be aligned before TRBE can be configured. Pad the alignment
+	 * gap with ETE_IGNORE_PACKET bytes that will be ignored by user tools
+	 * and skip this section thus advancing the head.
+	 */
+	if (!IS_ALIGNED(head, cpudata->trbe_align)) {
+		unsigned long delta = roundup(head, cpudata->trbe_align) - head;
+
+		delta = min(delta, handle->size);
+		trbe_pad_buf(handle, delta);
+		head = PERF_IDX2OFF(handle->head, buf);
+	}
+
+	/*
+	 *	head = tail (size = 0)
+	 * +----|-------------------------------+
+	 * |$$$$|$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$	|
+	 * +----|-------------------------------+
+	 * trbe_base				trbe_base + nr_pages
+	 *
+	 * Perf aux buffer does not have any space for the driver to write into.
+	 * Just communicate trace truncation event to the user space by marking
+	 * it with PERF_AUX_FLAG_TRUNCATED.
+	 */
+	if (!handle->size) {
+		perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+		return 0;
+	}
+
+	/* Compute the tail and wakeup indices now that we've aligned head */
+	tail = PERF_IDX2OFF(handle->head + handle->size, buf);
+	wakeup = PERF_IDX2OFF(handle->wakeup, buf);
+
+	/*
+	 * Lets calculate the buffer area which TRBE could write into. There
+	 * are three possible scenarios here. Limit needs to be aligned with
+	 * PAGE_SIZE per the TRBE requirement. Always avoid clobbering the
+	 * unconsumed data.
+	 *
+	 * 1) head < tail
+	 *
+	 *	head			tail
+	 * +----|-----------------------|-------+
+	 * |$$$$|#######################|$$$$$$$|
+	 * +----|-----------------------|-------+
+	 * trbe_base			limit	trbe_base + nr_pages
+	 *
+	 * TRBE could write into [head..tail] area. Unless the tail is right at
+	 * the end of the buffer, neither an wrap around nor an IRQ is expected
+	 * while being enabled.
+	 *
+	 * 2) head == tail
+	 *
+	 *	head = tail (size > 0)
+	 * +----|-------------------------------+
+	 * |%%%%|###############################|
+	 * +----|-------------------------------+
+	 * trbe_base				limit = trbe_base + nr_pages
+	 *
+	 * TRBE should just write into [head..base + nr_pages] area even though
+	 * the entire buffer is empty. Reason being, when the trace reaches the
+	 * end of the buffer, it will just wrap around with an IRQ giving an
+	 * opportunity to reconfigure the buffer.
+	 *
+	 * 3) tail < head
+	 *
+	 *	tail			head
+	 * +----|-----------------------|-------+
+	 * |%%%%|$$$$$$$$$$$$$$$$$$$$$$$|#######|
+	 * +----|-----------------------|-------+
+	 * trbe_base				limit = trbe_base + nr_pages
+	 *
+	 * TRBE should just write into [head..base + nr_pages] area even though
+	 * the [trbe_base..tail] is also empty. Reason being, when the trace
+	 * reaches the end of the buffer, it will just wrap around with an IRQ
+	 * giving an opportunity to reconfigure the buffer.
+	 */
+	if (head < tail)
+		limit = round_down(tail, PAGE_SIZE);
+
+	/*
+	 * Wakeup may be arbitrarily far into the future. If it's not in the
+	 * current generation, either we'll wrap before hitting it, or it's
+	 * in the past and has been handled already.
+	 *
+	 * If there's a wakeup before we wrap, arrange to be woken up by the
+	 * page boundary following it. Keep the tail boundary if that's lower.
+	 *
+	 *	head		wakeup	tail
+	 * +----|---------------|-------|-------+
+	 * |$$$$|###############|%%%%%%%|$$$$$$$|
+	 * +----|---------------|-------|-------+
+	 * trbe_base		limit		trbe_base + nr_pages
+	 */
+	if (handle->wakeup < (handle->head + handle->size) && head <= wakeup)
+		limit = min(limit, round_up(wakeup, PAGE_SIZE));
+
+	/*
+	 * There are two situation when this can happen i.e limit is before
+	 * the head and hence TRBE cannot be configured.
+	 *
+	 * 1) head < tail (aligned down with PAGE_SIZE) and also they are both
+	 * within the same PAGE size range.
+	 *
+	 *			PAGE_SIZE
+	 *		|----------------------|
+	 *
+	 *		limit	head	tail
+	 * +------------|------|--------|-------+
+	 * |$$$$$$$$$$$$$$$$$$$|========|$$$$$$$|
+	 * +------------|------|--------|-------+
+	 * trbe_base				trbe_base + nr_pages
+	 *
+	 * 2) head < wakeup (aligned up with PAGE_SIZE) < tail and also both
+	 * head and wakeup are within same PAGE size range.
+	 *
+	 *		PAGE_SIZE
+	 *	|----------------------|
+	 *
+	 *	limit	head	wakeup  tail
+	 * +----|------|-------|--------|-------+
+	 * |$$$$$$$$$$$|=======|========|$$$$$$$|
+	 * +----|------|-------|--------|-------+
+	 * trbe_base				trbe_base + nr_pages
+	 */
+	if (limit > head)
+		return limit;
+
+	trbe_pad_buf(handle, handle->size);
+	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
+	return 0;
+}
+
+static unsigned long trbe_normal_offset(struct perf_output_handle *handle)
+{
+	struct trbe_buf *buf = perf_get_aux(handle);
+	u64 limit = __trbe_normal_offset(handle);
+	u64 head = PERF_IDX2OFF(handle->head, buf);
+
+	/*
+	 * If the head is too close to the limit and we don't
+	 * have space for a meaningful run, we rather pad it
+	 * and start fresh.
+	 */
+	if (limit && (limit - head < TRBE_TRACE_MIN_BUF_SIZE)) {
+		trbe_pad_buf(handle, limit - head);
+		limit = __trbe_normal_offset(handle);
+	}
+	return limit;
+}
+
+static unsigned long compute_trbe_buffer_limit(struct perf_output_handle *handle)
+{
+	struct trbe_buf *buf = etm_perf_sink_config(handle);
+	unsigned long offset;
+
+	if (buf->snapshot)
+		offset = trbe_snapshot_offset(handle);
+	else
+		offset = trbe_normal_offset(handle);
+	return buf->trbe_base + offset;
+}
+
+static void clr_trbe_status(void)
+{
+	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
+
+	WARN_ON(is_trbe_enabled());
+	trbsr &= ~TRBSR_IRQ;
+	trbsr &= ~TRBSR_TRG;
+	trbsr &= ~TRBSR_WRAP;
+	trbsr &= ~(TRBSR_EC_MASK << TRBSR_EC_SHIFT);
+	trbsr &= ~(TRBSR_BSC_MASK << TRBSR_BSC_SHIFT);
+	trbsr &= ~TRBSR_STOP;
+	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
+}
+
+static void set_trbe_limit_pointer_enabled(unsigned long addr)
+{
+	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
+
+	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
+	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
+
+	trblimitr &= ~TRBLIMITR_NVM;
+	trblimitr &= ~(TRBLIMITR_FILL_MODE_MASK << TRBLIMITR_FILL_MODE_SHIFT);
+	trblimitr &= ~(TRBLIMITR_TRIG_MODE_MASK << TRBLIMITR_TRIG_MODE_SHIFT);
+	trblimitr &= ~(TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT);
+
+	/*
+	 * Fill trace buffer mode is used here while configuring the
+	 * TRBE for trace capture. In this particular mode, the trace
+	 * collection is stopped and a maintenance interrupt is raised
+	 * when the current write pointer wraps. This pause in trace
+	 * collection gives the software an opportunity to capture the
+	 * trace data in the interrupt handler, before reconfiguring
+	 * the TRBE.
+	 */
+	trblimitr |= (TRBE_FILL_MODE_FILL & TRBLIMITR_FILL_MODE_MASK) << TRBLIMITR_FILL_MODE_SHIFT;
+
+	/*
+	 * Trigger mode is not used here while configuring the TRBE for
+	 * the trace capture. Hence just keep this in the ignore mode.
+	 */
+	trblimitr |= (TRBE_TRIG_MODE_IGNORE & TRBLIMITR_TRIG_MODE_MASK) << TRBLIMITR_TRIG_MODE_SHIFT;
+	trblimitr |= (addr & PAGE_MASK);
+
+	trblimitr |= TRBLIMITR_ENABLE;
+	write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
+}
+
+static void trbe_enable_hw(struct trbe_buf *buf)
+{
+	WARN_ON(buf->trbe_write < buf->trbe_base);
+	WARN_ON(buf->trbe_write >= buf->trbe_limit);
+	set_trbe_disabled();
+	isb();
+	clr_trbe_status();
+	set_trbe_base_pointer(buf->trbe_base);
+	set_trbe_write_pointer(buf->trbe_write);
+
+	/*
+	 * Synchronize all the register updates
+	 * till now before enabling the TRBE.
+	 */
+	isb();
+	set_trbe_limit_pointer_enabled(buf->trbe_limit);
+
+	/* Synchronize the TRBE enable event */
+	isb();
+}
+
+static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
+				   struct perf_event *event, void **pages,
+				   int nr_pages, bool snapshot)
+{
+	struct trbe_buf *buf;
+	struct page **pglist;
+	int i;
+
+	/*
+	 * TRBE LIMIT and TRBE WRITE pointers must be page aligned. But with
+	 * just a single page, there is not much room left while writing into
+	 * a partially filled TRBE buffer. Hence restrict the minimum buffer
+	 * size as two pages.
+	 */
+	if (nr_pages < 2)
+		return NULL;
+
+	buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
+	if (IS_ERR(buf))
+		return ERR_PTR(-ENOMEM);
+
+	pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
+	if (IS_ERR(pglist)) {
+		kfree(buf);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	for (i = 0; i < nr_pages; i++)
+		pglist[i] = virt_to_page(pages[i]);
+
+	buf->trbe_base = (unsigned long) vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
+	if (IS_ERR((void *)buf->trbe_base)) {
+		kfree(pglist);
+		kfree(buf);
+		return ERR_PTR(buf->trbe_base);
+	}
+	buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
+	buf->trbe_write = buf->trbe_base;
+	buf->snapshot = snapshot;
+	buf->nr_pages = nr_pages;
+	buf->pages = pages;
+	kfree(pglist);
+	return buf;
+}
+
+void arm_trbe_free_buffer(void *config)
+{
+	struct trbe_buf *buf = config;
+
+	vunmap((void *)buf->trbe_base);
+	kfree(buf);
+}
+
+static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
+					    struct perf_output_handle *handle,
+					    void *config)
+{
+	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
+	struct trbe_buf *buf = config;
+	unsigned long size, offset;
+
+	WARN_ON(buf->cpudata != cpudata);
+	WARN_ON(cpudata->cpu != smp_processor_id());
+	WARN_ON(cpudata->drvdata != drvdata);
+	if (cpudata->mode != CS_MODE_PERF)
+		return -EINVAL;
+
+	/*
+	 * If the TRBE was disabled due to lack of space in the AUX buffer or a
+	 * spurious fault, the driver leaves it disabled, truncating the buffer.
+	 * Since the etm_perf driver expects to close out the AUX buffer, the
+	 * driver skips it. Thus, just pass in 0 size here to indicate that the
+	 * buffer was truncated.
+	 */
+	if (!is_trbe_enabled())
+		return 0;
+	/*
+	 * perf handle structure needs to be shared with the TRBE IRQ handler for
+	 * capturing trace data and restarting the handle. There is a probability
+	 * of an undefined reference based crash when etm event is being stopped
+	 * while a TRBE IRQ also getting processed. This happens due the release
+	 * of perf handle via perf_aux_output_end() in etm_event_stop(). Stopping
+	 * the TRBE here will ensure that no IRQ could be generated when the perf
+	 * handle gets freed in etm_event_stop().
+	 */
+	trbe_drain_and_disable_local();
+	offset = get_trbe_write_pointer() - get_trbe_base_pointer();
+	size = offset - PERF_IDX2OFF(handle->head, buf);
+	if (buf->snapshot)
+		handle->head += size;
+	return size;
+}
+
+static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)
+{
+	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
+	struct perf_output_handle *handle = data;
+	struct trbe_buf *buf = etm_perf_sink_config(handle);
+
+	WARN_ON(cpudata->cpu != smp_processor_id());
+	WARN_ON(cpudata->drvdata != drvdata);
+	if (mode != CS_MODE_PERF)
+		return -EINVAL;
+
+	*this_cpu_ptr(drvdata->handle) = handle;
+	cpudata->buf = buf;
+	cpudata->mode = mode;
+	buf->cpudata = cpudata;
+	buf->trbe_limit = compute_trbe_buffer_limit(handle);
+	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
+	if (buf->trbe_limit == buf->trbe_base) {
+		trbe_stop_and_truncate_event(handle);
+		return 0;
+	}
+	trbe_enable_hw(buf);
+	return 0;
+}
+
+static int arm_trbe_disable(struct coresight_device *csdev)
+{
+	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
+	struct trbe_buf *buf = cpudata->buf;
+
+	WARN_ON(buf->cpudata != cpudata);
+	WARN_ON(cpudata->cpu != smp_processor_id());
+	WARN_ON(cpudata->drvdata != drvdata);
+	if (cpudata->mode != CS_MODE_PERF)
+		return -EINVAL;
+
+	trbe_drain_and_disable_local();
+	buf->cpudata = NULL;
+	cpudata->buf = NULL;
+	cpudata->mode = CS_MODE_DISABLED;
+	return 0;
+}
+
+static void trbe_handle_spurious(struct perf_output_handle *handle)
+{
+	struct trbe_buf *buf = etm_perf_sink_config(handle);
+
+	buf->trbe_limit = compute_trbe_buffer_limit(handle);
+	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
+	if (buf->trbe_limit == buf->trbe_base) {
+		trbe_drain_and_disable_local();
+		return;
+	}
+	trbe_enable_hw(buf);
+}
+
+static void trbe_handle_overflow(struct perf_output_handle *handle)
+{
+	struct perf_event *event = handle->event;
+	struct trbe_buf *buf = etm_perf_sink_config(handle);
+	unsigned long offset, size;
+	struct etm_event_data *event_data;
+
+	offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
+	size = offset - PERF_IDX2OFF(handle->head, buf);
+	if (buf->snapshot)
+		handle->head = offset;
+	perf_aux_output_end(handle, size);
+
+	event_data = perf_aux_output_begin(handle, event);
+	if (!event_data) {
+		trbe_drain_and_disable_local();
+		*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
+		return;
+	}
+	buf->trbe_limit = compute_trbe_buffer_limit(handle);
+	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
+	if (buf->trbe_limit == buf->trbe_base) {
+		trbe_stop_and_truncate_event(handle);
+		return;
+	}
+	*this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;
+	trbe_enable_hw(buf);
+}
+
+static bool is_perf_trbe(struct perf_output_handle *handle)
+{
+	struct trbe_buf *buf = etm_perf_sink_config(handle);
+	struct trbe_cpudata *cpudata = buf->cpudata;
+	struct trbe_drvdata *drvdata = cpudata->drvdata;
+	int cpu = smp_processor_id();
+
+	WARN_ON(buf->trbe_base != get_trbe_base_pointer());
+	WARN_ON(buf->trbe_limit != get_trbe_limit_pointer());
+
+	if (cpudata->mode != CS_MODE_PERF)
+		return false;
+
+	if (cpudata->cpu != cpu)
+		return false;
+
+	if (!cpumask_test_cpu(cpu, &drvdata->supported_cpus))
+		return false;
+
+	return true;
+}
+
+static enum trbe_fault_action trbe_get_fault_act(struct perf_output_handle *handle)
+{
+	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
+	int ec = get_trbe_ec(trbsr);
+	int bsc = get_trbe_bsc(trbsr);
+
+	WARN_ON(is_trbe_running(trbsr));
+	if (is_trbe_trg(trbsr) || is_trbe_abort(trbsr))
+		return TRBE_FAULT_ACT_FATAL;
+
+	if ((ec == TRBE_EC_STAGE1_ABORT) || (ec == TRBE_EC_STAGE2_ABORT))
+		return TRBE_FAULT_ACT_FATAL;
+
+	if (is_trbe_wrap(trbsr) && (ec == TRBE_EC_OTHERS) && (bsc == TRBE_BSC_FILLED)) {
+		if (get_trbe_write_pointer() == get_trbe_base_pointer())
+			return TRBE_FAULT_ACT_WRAP;
+	}
+	return TRBE_FAULT_ACT_SPURIOUS;
+}
+
+static irqreturn_t arm_trbe_irq_handler(int irq, void *dev)
+{
+	struct perf_output_handle **handle_ptr = dev;
+	struct perf_output_handle *handle = *handle_ptr;
+	enum trbe_fault_action act;
+
+	WARN_ON(!is_trbe_irq(read_sysreg_s(SYS_TRBSR_EL1)));
+	clr_trbe_irq();
+
+	/*
+	 * Ensure the trace is visible to the CPUs and
+	 * any external aborts have been resolved.
+	 */
+	trbe_drain_buffer();
+	isb();
+
+	if (!perf_get_aux(handle))
+		return IRQ_NONE;
+
+	if (!is_perf_trbe(handle))
+		return IRQ_NONE;
+
+	irq_work_run();
+
+	act = trbe_get_fault_act(handle);
+	switch (act) {
+	case TRBE_FAULT_ACT_WRAP:
+		trbe_handle_overflow(handle);
+		break;
+	case TRBE_FAULT_ACT_SPURIOUS:
+		trbe_handle_spurious(handle);
+		break;
+	case TRBE_FAULT_ACT_FATAL:
+		trbe_stop_and_truncate_event(handle);
+		break;
+	}
+	return IRQ_HANDLED;
+}
+
+static const struct coresight_ops_sink arm_trbe_sink_ops = {
+	.enable		= arm_trbe_enable,
+	.disable	= arm_trbe_disable,
+	.alloc_buffer	= arm_trbe_alloc_buffer,
+	.free_buffer	= arm_trbe_free_buffer,
+	.update_buffer	= arm_trbe_update_buffer,
+};
+
+static const struct coresight_ops arm_trbe_cs_ops = {
+	.sink_ops	= &arm_trbe_sink_ops,
+};
+
+static ssize_t align_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%llx\n", cpudata->trbe_align);
+}
+static DEVICE_ATTR_RO(align);
+
+static ssize_t dbm_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%d\n", cpudata->trbe_dbm);
+}
+static DEVICE_ATTR_RO(dbm);
+
+static struct attribute *arm_trbe_attrs[] = {
+	&dev_attr_align.attr,
+	&dev_attr_dbm.attr,
+	NULL,
+};
+
+static const struct attribute_group arm_trbe_group = {
+	.attrs = arm_trbe_attrs,
+};
+
+static const struct attribute_group *arm_trbe_groups[] = {
+	&arm_trbe_group,
+	NULL,
+};
+
+static void arm_trbe_probe_coresight_cpu(void *info)
+{
+	struct trbe_drvdata *drvdata = info;
+	struct coresight_desc desc = { 0 };
+	int cpu = smp_processor_id();
+	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
+	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
+	u64 trbidr = read_sysreg_s(SYS_TRBIDR_EL1);
+	struct device *dev;
+
+	if (WARN_ON(!cpudata))
+		goto cpu_clear;
+
+	if (trbe_csdev)
+		return;
+
+	cpudata->cpu = smp_processor_id();
+	cpudata->drvdata = drvdata;
+	dev = &cpudata->drvdata->pdev->dev;
+
+	if (!is_trbe_available()) {
+		pr_err("TRBE is not implemented on cpu %d\n", cpudata->cpu);
+		goto cpu_clear;
+	}
+
+	if (!is_trbe_programmable(trbidr)) {
+		pr_err("TRBE is owned in higher exception level on cpu %d\n", cpudata->cpu);
+		goto cpu_clear;
+	}
+	desc.name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", DRVNAME, smp_processor_id());
+	if (IS_ERR(desc.name))
+		goto cpu_clear;
+
+	desc.type = CORESIGHT_DEV_TYPE_SINK;
+	desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
+	desc.ops = &arm_trbe_cs_ops;
+	desc.pdata = dev_get_platdata(dev);
+	desc.groups = arm_trbe_groups;
+	desc.dev = dev;
+	trbe_csdev = coresight_register(&desc);
+	if (IS_ERR(trbe_csdev))
+		goto cpu_clear;
+
+	dev_set_drvdata(&trbe_csdev->dev, cpudata);
+	cpudata->trbe_dbm = get_trbe_flag_update(trbidr);
+	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
+	if (cpudata->trbe_align > SZ_2K) {
+		pr_err("Unsupported alignment on cpu %d\n", cpudata->cpu);
+		goto cpu_clear;
+	}
+	per_cpu(csdev_sink, cpu) = trbe_csdev;
+	trbe_reset_local();
+	enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
+	return;
+cpu_clear:
+	cpumask_clear_cpu(cpudata->cpu, &cpudata->drvdata->supported_cpus);
+}
+
+static void arm_trbe_remove_coresight_cpu(void *info)
+{
+	int cpu = smp_processor_id();
+	struct trbe_drvdata *drvdata = info;
+	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
+	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
+
+	if (trbe_csdev) {
+		coresight_unregister(trbe_csdev);
+		cpudata->drvdata = NULL;
+		per_cpu(csdev_sink, cpu) = NULL;
+	}
+	disable_percpu_irq(drvdata->irq);
+	trbe_reset_local();
+}
+
+static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata)
+{
+	drvdata->cpudata = alloc_percpu(typeof(*drvdata->cpudata));
+	if (IS_ERR(drvdata->cpudata))
+		return PTR_ERR(drvdata->cpudata);
+
+	arm_trbe_probe_coresight_cpu(drvdata);
+	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_probe_coresight_cpu, drvdata, 1);
+	return 0;
+}
+
+static int arm_trbe_remove_coresight(struct trbe_drvdata *drvdata)
+{
+	arm_trbe_remove_coresight_cpu(drvdata);
+	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_remove_coresight_cpu, drvdata, 1);
+	free_percpu(drvdata->cpudata);
+	return 0;
+}
+
+static int arm_trbe_cpu_startup(unsigned int cpu, struct hlist_node *node)
+{
+	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
+
+	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
+		if (!per_cpu(csdev_sink, cpu)) {
+			arm_trbe_probe_coresight_cpu(drvdata);
+		} else {
+			trbe_reset_local();
+			enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
+		}
+	}
+	return 0;
+}
+
+static int arm_trbe_cpu_teardown(unsigned int cpu, struct hlist_node *node)
+{
+	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
+
+	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
+		disable_percpu_irq(drvdata->irq);
+		trbe_reset_local();
+	}
+	return 0;
+}
+
+static int arm_trbe_probe_cpuhp(struct trbe_drvdata *drvdata)
+{
+	enum cpuhp_state trbe_online;
+
+	trbe_online = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
+					arm_trbe_cpu_startup, arm_trbe_cpu_teardown);
+	if (trbe_online < 0)
+		return -EINVAL;
+
+	if (cpuhp_state_add_instance(trbe_online, &drvdata->hotplug_node))
+		return -EINVAL;
+
+	drvdata->trbe_online = trbe_online;
+	return 0;
+}
+
+static void arm_trbe_remove_cpuhp(struct trbe_drvdata *drvdata)
+{
+	cpuhp_remove_multi_state(drvdata->trbe_online);
+}
+
+static int arm_trbe_probe_irq(struct platform_device *pdev,
+			      struct trbe_drvdata *drvdata)
+{
+	drvdata->irq = platform_get_irq(pdev, 0);
+	if (!drvdata->irq) {
+		pr_err("IRQ not found for the platform device\n");
+		return -ENXIO;
+	}
+
+	if (!irq_is_percpu(drvdata->irq)) {
+		pr_err("IRQ is not a PPI\n");
+		return -EINVAL;
+	}
+
+	if (irq_get_percpu_devid_partition(drvdata->irq, &drvdata->supported_cpus))
+		return -EINVAL;
+
+	drvdata->handle = alloc_percpu(typeof(*drvdata->handle));
+	if (!drvdata->handle)
+		return -ENOMEM;
+
+	if (request_percpu_irq(drvdata->irq, arm_trbe_irq_handler, DRVNAME, drvdata->handle)) {
+		free_percpu(drvdata->handle);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static void arm_trbe_remove_irq(struct trbe_drvdata *drvdata)
+{
+	free_percpu_irq(drvdata->irq, drvdata->handle);
+	free_percpu(drvdata->handle);
+}
+
+static int arm_trbe_device_probe(struct platform_device *pdev)
+{
+	struct coresight_platform_data *pdata;
+	struct trbe_drvdata *drvdata;
+	struct device *dev = &pdev->dev;
+	int ret;
+
+	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+	if (IS_ERR(drvdata))
+		return -ENOMEM;
+
+	pdata = coresight_get_platform_data(dev);
+	if (IS_ERR(pdata)) {
+		kfree(drvdata);
+		return -ENOMEM;
+	}
+
+	dev_set_drvdata(dev, drvdata);
+	dev->platform_data = pdata;
+	drvdata->pdev = pdev;
+	ret = arm_trbe_probe_irq(pdev, drvdata);
+	if (ret)
+		goto irq_failed;
+
+	ret = arm_trbe_probe_coresight(drvdata);
+	if (ret)
+		goto probe_failed;
+
+	ret = arm_trbe_probe_cpuhp(drvdata);
+	if (ret)
+		goto cpuhp_failed;
+
+	return 0;
+cpuhp_failed:
+	arm_trbe_remove_coresight(drvdata);
+probe_failed:
+	arm_trbe_remove_irq(drvdata);
+irq_failed:
+	kfree(pdata);
+	kfree(drvdata);
+	return ret;
+}
+
+static int arm_trbe_device_remove(struct platform_device *pdev)
+{
+	struct coresight_platform_data *pdata = dev_get_platdata(&pdev->dev);
+	struct trbe_drvdata *drvdata = platform_get_drvdata(pdev);
+
+	arm_trbe_remove_coresight(drvdata);
+	arm_trbe_remove_cpuhp(drvdata);
+	arm_trbe_remove_irq(drvdata);
+	kfree(pdata);
+	kfree(drvdata);
+	return 0;
+}
+
+static const struct of_device_id arm_trbe_of_match[] = {
+	{ .compatible = "arm,trace-buffer-extension"},
+	{},
+};
+MODULE_DEVICE_TABLE(of, arm_trbe_of_match);
+
+static struct platform_driver arm_trbe_driver = {
+	.driver	= {
+		.name = DRVNAME,
+		.of_match_table = of_match_ptr(arm_trbe_of_match),
+		.suppress_bind_attrs = true,
+	},
+	.probe	= arm_trbe_device_probe,
+	.remove	= arm_trbe_device_remove,
+};
+
+static int __init arm_trbe_init(void)
+{
+	int ret;
+
+	if (arm64_kernel_unmapped_at_el0()) {
+		pr_err("TRBE wouldn't work if kernel gets unmapped at EL0\n");
+		return -EOPNOTSUPP;
+	}
+
+	ret = platform_driver_register(&arm_trbe_driver);
+	if (!ret)
+		return 0;
+
+	pr_err("Error registering %s platform driver\n", DRVNAME);
+	return ret;
+}
+
+static void __exit arm_trbe_exit(void)
+{
+	platform_driver_unregister(&arm_trbe_driver);
+}
+module_init(arm_trbe_init);
+module_exit(arm_trbe_exit);
+
+MODULE_AUTHOR("Anshuman Khandual <anshuman.khandual@arm.com>");
+MODULE_DESCRIPTION("Arm Trace Buffer Extension (TRBE) driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h
new file mode 100644
index 0000000..43308bc
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-trbe.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This contains all required hardware related helper functions for
+ * Trace Buffer Extension (TRBE) driver in the coresight framework.
+ *
+ * Copyright (C) 2020 ARM Ltd.
+ *
+ * Author: Anshuman Khandual <anshuman.khandual@arm.com>
+ */
+#include <linux/coresight.h>
+#include <linux/device.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/smp.h>
+
+#include "coresight-etm-perf.h"
+
+DECLARE_PER_CPU(struct coresight_device *, csdev_sink);
+
+static inline bool is_trbe_available(void)
+{
+	u64 aa64dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
+	unsigned int trbe = cpuid_feature_extract_unsigned_field(aa64dfr0, ID_AA64DFR0_TRBE_SHIFT);
+
+	return trbe >= 0b0001;
+}
+
+static inline bool is_trbe_enabled(void)
+{
+	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
+
+	return trblimitr & TRBLIMITR_ENABLE;
+}
+
+#define TRBE_EC_OTHERS		0
+#define TRBE_EC_STAGE1_ABORT	36
+#define TRBE_EC_STAGE2_ABORT	37
+
+static inline int get_trbe_ec(u64 trbsr)
+{
+	return (trbsr >> TRBSR_EC_SHIFT) & TRBSR_EC_MASK;
+}
+
+#define TRBE_BSC_NOT_STOPPED	0
+#define	TRBE_BSC_FILLED		1
+#define TRBE_BSC_TRIGGERED	2
+
+static inline int get_trbe_bsc(u64 trbsr)
+{
+	return (trbsr >> TRBSR_BSC_SHIFT) & TRBSR_BSC_MASK;
+}
+
+static inline void clr_trbe_irq(void)
+{
+	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
+
+	trbsr &= ~TRBSR_IRQ;
+	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
+}
+
+static inline bool is_trbe_irq(u64 trbsr)
+{
+	return trbsr & TRBSR_IRQ;
+}
+
+static inline bool is_trbe_trg(u64 trbsr)
+{
+	return trbsr & TRBSR_TRG;
+}
+
+static inline bool is_trbe_wrap(u64 trbsr)
+{
+	return trbsr & TRBSR_WRAP;
+}
+
+static inline bool is_trbe_abort(u64 trbsr)
+{
+	return trbsr & TRBSR_ABORT;
+}
+
+static inline bool is_trbe_running(u64 trbsr)
+{
+	return !(trbsr & TRBSR_STOP);
+}
+
+#define TRBE_TRIG_MODE_STOP		0
+#define TRBE_TRIG_MODE_IRQ		1
+#define TRBE_TRIG_MODE_IGNORE		3
+
+#define TRBE_FILL_MODE_FILL		0
+#define TRBE_FILL_MODE_WRAP		1
+#define TRBE_FILL_MODE_CIRCULAR_BUFFER	3
+
+static inline void set_trbe_disabled(void)
+{
+	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
+
+	trblimitr &= ~TRBLIMITR_ENABLE;
+	write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
+}
+
+static inline bool get_trbe_flag_update(u64 trbidr)
+{
+	return trbidr & TRBIDR_FLAG;
+}
+
+static inline bool is_trbe_programmable(u64 trbidr)
+{
+	return !(trbidr & TRBIDR_PROG);
+}
+
+static inline int get_trbe_address_align(u64 trbidr)
+{
+	return (trbidr >> TRBIDR_ALIGN_SHIFT) & TRBIDR_ALIGN_MASK;
+}
+
+static inline unsigned long get_trbe_write_pointer(void)
+{
+	u64 trbptr = read_sysreg_s(SYS_TRBPTR_EL1);
+	unsigned long addr = (trbptr >> TRBPTR_PTR_SHIFT) & TRBPTR_PTR_MASK;
+
+	return addr;
+}
+
+static inline void set_trbe_write_pointer(unsigned long addr)
+{
+	WARN_ON(is_trbe_enabled());
+	addr = (addr >> TRBPTR_PTR_SHIFT) & TRBPTR_PTR_MASK;
+	write_sysreg_s(addr, SYS_TRBPTR_EL1);
+}
+
+static inline unsigned long get_trbe_limit_pointer(void)
+{
+	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
+	unsigned long limit = (trblimitr >> TRBLIMITR_LIMIT_SHIFT) & TRBLIMITR_LIMIT_MASK;
+	unsigned long addr = limit << TRBLIMITR_LIMIT_SHIFT;
+
+	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
+	return addr;
+}
+
+static inline unsigned long get_trbe_base_pointer(void)
+{
+	u64 trbbaser = read_sysreg_s(SYS_TRBBASER_EL1);
+	unsigned long addr = (trbbaser >> TRBBASER_BASE_SHIFT) & TRBBASER_BASE_MASK;
+
+	addr = addr << TRBBASER_BASE_SHIFT;
+	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
+	return addr;
+}
+
+static inline void set_trbe_base_pointer(unsigned long addr)
+{
+	WARN_ON(is_trbe_enabled());
+	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
+	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
+	write_sysreg_s(addr, SYS_TRBBASER_EL1);
+}
-- 
2.7.4


^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH V3 12/14] dts: bindings: Document device tree bindings for Arm TRBE
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
                   ` (10 preceding siblings ...)
  2021-01-27  8:55 ` [PATCH V3 11/14] coresight: sink: Add TRBE driver Anshuman Khandual
@ 2021-01-27  8:55 ` Anshuman Khandual
  2021-02-09 19:04   ` Rob Herring
  2021-01-27  8:55 ` [PATCH V3 13/14] perf: aux: Add flags for the buffer format Anshuman Khandual
                   ` (3 subsequent siblings)
  15 siblings, 1 reply; 90+ messages in thread
From: Anshuman Khandual @ 2021-01-27  8:55 UTC (permalink / raw)
  To: linux-arm-kernel, coresight
  Cc: mathieu.poirier, suzuki.poulose, mike.leach, lcherian,
	linux-kernel, Anshuman Khandual, Rob Herring, devicetree

From: Suzuki K Poulose <suzuki.poulose@arm.com>

Document the device tree bindings for Trace Buffer Extension (TRBE).

Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
Changes in V3:

- Added missing description for the TRBE hardware
- Fixed all DT yaml semantics problems

 Documentation/devicetree/bindings/arm/trbe.yaml | 49 +++++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/trbe.yaml

diff --git a/Documentation/devicetree/bindings/arm/trbe.yaml b/Documentation/devicetree/bindings/arm/trbe.yaml
new file mode 100644
index 0000000..4402d7b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/trbe.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+# Copyright 2021, Arm Ltd
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/trbe.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: ARM Trace Buffer Extensions
+
+maintainers:
+  - Anshuman Khandual <anshuman.khandual@arm.com>
+
+description: |
+  Arm Trace Buffer Extension (TRBE) is a per CPU component
+  for storing trace generated on the CPU to memory. It is
+  accessed via CPU system registers. The software can verify
+  if it is permitted to use the component by checking the
+  TRBIDR register.
+
+properties:
+  $nodename:
+    const: "trbe"
+  compatible:
+    items:
+      - const: arm,trace-buffer-extension
+
+  interrupts:
+    description: |
+       Exactly 1 PPI must be listed. For heterogeneous systems where
+       TRBE is only supported on a subset of the CPUs, please consult
+       the arm,gic-v3 binding for details on describing a PPI partition.
+    maxItems: 1
+
+required:
+  - compatible
+  - interrupts
+
+additionalProperties: false
+
+examples:
+
+  - |
+   #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+   trbe {
+     compatible = "arm,trace-buffer-extension";
+     interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+   };
+...
-- 
2.7.4


^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH V3 13/14] perf: aux: Add flags for the buffer format
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
                   ` (11 preceding siblings ...)
  2021-01-27  8:55 ` [PATCH V3 12/14] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual
@ 2021-01-27  8:55 ` Anshuman Khandual
  2021-01-27 12:51   ` Peter Zijlstra
  2021-02-16 10:59   ` Mike Leach
  2021-01-27  8:55 ` [PATCH V3 14/14] coresight: etm-perf: Add support for trace " Anshuman Khandual
                   ` (2 subsequent siblings)
  15 siblings, 2 replies; 90+ messages in thread
From: Anshuman Khandual @ 2021-01-27  8:55 UTC (permalink / raw)
  To: linux-arm-kernel, coresight
  Cc: mathieu.poirier, suzuki.poulose, mike.leach, lcherian,
	linux-kernel, Anshuman Khandual, Peter Ziljstra,
	alexander.shishkin, mingo, will, mark.rutland, acme, jolsa,
	Mathieu Poirier

From: Suzuki K Poulose <suzuki.poulose@arm.com>

Allocate a byte for advertising the PMU specific format type
of the given AUX record. A PMU could end up providing hardware
trace data in multiple format in a single session.

e.g, The format of hardware buffer produced by CoreSight ETM
PMU depends on the type of the "sink" device used for collection
for an event (Traditional TMC-ETR/Bs with formatting or
TRBEs without any formatting).

 # Boring story of why this is needed. Goto The_End_of_Story for skipping.

CoreSight ETM trace allows instruction level tracing of Arm CPUs.
The ETM generates the CPU excecution trace and pumps it into CoreSight
AMBA Trace Bus and is collected by a different CoreSight component
(traditionally CoreSight TMC-ETR /ETB/ETF), called "sink".
Important to note that there is no guarantee that every CPU has
a dedicated sink.  Thus multiple ETMs could pump the trace data
into the same "sink" and thus they apply additional formatting
of the trace data for the user to decode it properly and attribute
the trace data to the corresponding ETM.

However, with the introduction of Arm Trace buffer Extensions (TRBE),
we now have a dedicated per-CPU architected sink for collecting the
trace. Since the TRBE is always per-CPU, it doesn't apply any formatting
of the trace. The support for this driver is under review [1].

Now a system could have a per-cpu TRBE and one or more shared
TMC-ETRs on the system. A user could choose a "specific" sink
for a perf session (e.g, a TMC-ETR) or the driver could automatically
select the nearest sink for a given ETM. It is possible that
some ETMs could end up using TMC-ETR (e.g, if the TRBE is not
usable on the CPU) while the others using TRBE in a single
perf session. Thus we now have "formatted" trace collected
from TMC-ETR and "unformatted" trace collected from TRBE.
However, we don't get into a situation where a single event
could end up using TMC-ETR & TRBE. i.e, any AUX buffer is
guaranteed to be either RAW or FORMATTED, but not a mix
of both.

As for perf decoding, we need to know the type of the data
in the individual AUX buffers, so that it can set up the
"OpenCSD" (library for decoding CoreSight trace) decoder
instance appropriately. Thus the perf.data file must conatin
the hints for the tool to decode the data correctly.

Since this is a runtime variable, and perf tool doesn't have
a control on what sink gets used (in case of automatic sink
selection), we need this information made available from
the PMU driver for each AUX record.

 # The_End_of_Story

Cc: Peter Ziljstra <peterz@infradead.org>
Cc: alexander.shishkin@linux.intel.com
Cc: mingo@redhat.com
Cc: will@kernel.org
Cc: mark.rutland@arm.com
Cc: mike.leach@linaro.org
Cc: acme@kernel.org
Cc: jolsa@redhat.com
Cc: Mathieu Poirier <mathieu.poirer@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 include/uapi/linux/perf_event.h | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index b15e344..9a5ca45 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -1105,10 +1105,11 @@ enum perf_callchain_context {
 /**
  * PERF_RECORD_AUX::flags bits
  */
-#define PERF_AUX_FLAG_TRUNCATED		0x01	/* record was truncated to fit */
-#define PERF_AUX_FLAG_OVERWRITE		0x02	/* snapshot from overwrite mode */
-#define PERF_AUX_FLAG_PARTIAL		0x04	/* record contains gaps */
-#define PERF_AUX_FLAG_COLLISION		0x08	/* sample collided with another */
+#define PERF_AUX_FLAG_TRUNCATED			0x01	/* record was truncated to fit */
+#define PERF_AUX_FLAG_OVERWRITE			0x02	/* snapshot from overwrite mode */
+#define PERF_AUX_FLAG_PARTIAL			0x04	/* record contains gaps */
+#define PERF_AUX_FLAG_COLLISION			0x08	/* sample collided with another */
+#define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK	0xff00	/* PMU specific trace format type */
 
 #define PERF_FLAG_FD_NO_GROUP		(1UL << 0)
 #define PERF_FLAG_FD_OUTPUT		(1UL << 1)
-- 
2.7.4


^ permalink raw reply	[flat|nested] 90+ messages in thread

* [PATCH V3 14/14] coresight: etm-perf: Add support for trace buffer format
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
                   ` (12 preceding siblings ...)
  2021-01-27  8:55 ` [PATCH V3 13/14] perf: aux: Add flags for the buffer format Anshuman Khandual
@ 2021-01-27  8:55 ` Anshuman Khandual
  2021-01-27 12:54   ` Peter Zijlstra
  2021-02-16 11:01   ` Mike Leach
  2021-01-27 18:50 ` [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Mathieu Poirier
  2021-02-01 18:44 ` Mathieu Poirier
  15 siblings, 2 replies; 90+ messages in thread
From: Anshuman Khandual @ 2021-01-27  8:55 UTC (permalink / raw)
  To: linux-arm-kernel, coresight
  Cc: mathieu.poirier, suzuki.poulose, mike.leach, lcherian,
	linux-kernel, Anshuman Khandual, Peter Zijlstra, Leo Yan

From: Suzuki K Poulose <suzuki.poulose@arm.com>

CoreSight PMU supports aux-buffer for the ETM tracing. The trace
generated by the ETM (associated with individual CPUs, like Intel PT)
is captured by a separate IP (CoreSight TMC-ETR/ETF until now).

The TMC-ETR applies formatting of the raw ETM trace data, as it
can collect traces from multiple ETMs, with the TraceID to indicate
the source of a given trace packet.

Arm Trace Buffer Extension is new "sink" IP, attached to individual
CPUs and thus do not provide additional formatting, like TMC-ETR.

Additionally, a system could have both TRBE *and* TMC-ETR for
the trace collection. e.g, TMC-ETR could be used as a single
trace buffer to collect data from multiple ETMs to correlate
the traces from different CPUs. It is possible to have a
perf session where some events end up collecting the trace
in TMC-ETR while the others in TRBE. Thus we need a way
to identify the type of the trace for each AUX record.

Define the trace formats exported by the CoreSight PMU.
We don't define the flags following the "ETM" as this
information is available to the user when issuing
the session. What is missing is the additional
formatting applied by the "sink" which is decided
at the runtime and the user may not have a control on.

So we define :
 - CORESIGHT format (indicates the Frame format)
 - RAW format (indicates the format of the source)

The default value is CORESIGHT format for all the records
(i,e == 0). Add the RAW format for the TRBE sink driver.

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 drivers/hwtracing/coresight/coresight-trbe.c | 2 ++
 include/uapi/linux/perf_event.h              | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
index 1464d8b..7c0e691 100644
--- a/drivers/hwtracing/coresight/coresight-trbe.c
+++ b/drivers/hwtracing/coresight/coresight-trbe.c
@@ -511,6 +511,7 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
 	if (cpudata->mode != CS_MODE_PERF)
 		return -EINVAL;
 
+	perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW);
 	/*
 	 * If the TRBE was disabled due to lack of space in the AUX buffer or a
 	 * spurious fault, the driver leaves it disabled, truncating the buffer.
@@ -606,6 +607,7 @@ static void trbe_handle_overflow(struct perf_output_handle *handle)
 	size = offset - PERF_IDX2OFF(handle->head, buf);
 	if (buf->snapshot)
 		handle->head = offset;
+	perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW);
 	perf_aux_output_end(handle, size);
 
 	event_data = perf_aux_output_begin(handle, event);
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 9a5ca45..169e6b3 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -1111,6 +1111,10 @@ enum perf_callchain_context {
 #define PERF_AUX_FLAG_COLLISION			0x08	/* sample collided with another */
 #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK	0xff00	/* PMU specific trace format type */
 
+/* CoreSight PMU AUX buffer formats */
+#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT	0x0000 /* Default for backward compatibility */
+#define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW		0x0100 /* Raw format of the source */
+
 #define PERF_FLAG_FD_NO_GROUP		(1UL << 0)
 #define PERF_FLAG_FD_OUTPUT		(1UL << 1)
 #define PERF_FLAG_PID_CGROUP		(1UL << 2) /* pid=cgroup id, per-cpu mode only */
-- 
2.7.4


^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1
  2021-01-27  8:55 ` [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1 Anshuman Khandual
@ 2021-01-27  9:58   ` Marc Zyngier
  2021-01-28  9:34     ` Suzuki K Poulose
  0 siblings, 1 reply; 90+ messages in thread
From: Marc Zyngier @ 2021-01-27  9:58 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, mathieu.poirier, suzuki.poulose,
	mike.leach, lcherian, linux-kernel, Will Deacon, Catalin Marinas,
	Mark Rutland

On 2021-01-27 08:55, Anshuman Khandual wrote:
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> When the kernel is booted at EL2 in a nvhe configuration,
> enable the TRBE access to the EL1. The EL1 still can't trace
> EL2, unless EL2 permits explicitly via TRFCR_EL2.E2TRE.
> 
> Cc: Will Deacon <will@kernel.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> cc: Anshuman Khandual <anshuman.khandual@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>

Acked-by: Marc Zyngier <maz@kernel.org>

One comment below, though:

> ---
>  arch/arm64/include/asm/el2_setup.h | 19 +++++++++++++++++++
>  arch/arm64/include/asm/kvm_arm.h   |  2 ++
>  2 files changed, 21 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/el2_setup.h
> b/arch/arm64/include/asm/el2_setup.h
> index a7f5a1b..05ecce9 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -72,6 +72,25 @@
>  .endif
> 
>  3:
> +
> +.ifeqs	"\mode", "nvhe"
> +	/*
> +	 * If the Trace Buffer is available, allow
> +	 * the EL1 to own it. Note that EL1 cannot
> +	 * trace the EL2, as it is prevented by
> +	 * TRFCR_EL2.E2TRE == 0.
> +	 */
> +	ubfx	x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4
> +	cbz	x0, 1f
> +
> +	mrs_s	x0, SYS_TRBIDR_EL1
> +	and	x0, x0, TRBIDR_PROG
> +	cbnz	x0, 1f
> +	mov	x0, #(MDCR_EL2_E2TB_EL1_OWN << MDCR_EL2_E2TB_SHIFT)
> +	orr	x2, x2, x0
> +.endif
> +
> +1:

Note that this will (badly) conflict with the late-VHE patches[1],
where this code path has been reworked.

Thanks,

         M.

[1] https://lore.kernel.org/r/20210125105019.2946057-1-maz@kernel.org
-- 
Jazz is not dead. It just smells funny...

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 13/14] perf: aux: Add flags for the buffer format
  2021-01-27  8:55 ` [PATCH V3 13/14] perf: aux: Add flags for the buffer format Anshuman Khandual
@ 2021-01-27 12:51   ` Peter Zijlstra
  2021-02-16 10:59   ` Mike Leach
  1 sibling, 0 replies; 90+ messages in thread
From: Peter Zijlstra @ 2021-01-27 12:51 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, mathieu.poirier, suzuki.poulose,
	mike.leach, lcherian, linux-kernel, alexander.shishkin, mingo,
	will, mark.rutland, acme, jolsa, Mathieu Poirier

On Wed, Jan 27, 2021 at 02:25:37PM +0530, Anshuman Khandual wrote:
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> Allocate a byte for advertising the PMU specific format type
> of the given AUX record. A PMU could end up providing hardware
> trace data in multiple format in a single session.
> 
> e.g, The format of hardware buffer produced by CoreSight ETM
> PMU depends on the type of the "sink" device used for collection
> for an event (Traditional TMC-ETR/Bs with formatting or
> TRBEs without any formatting).

Acked-by: Peter Ziljstra <peterz@infradead.org>

> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  include/uapi/linux/perf_event.h | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
> index b15e344..9a5ca45 100644
> --- a/include/uapi/linux/perf_event.h
> +++ b/include/uapi/linux/perf_event.h
> @@ -1105,10 +1105,11 @@ enum perf_callchain_context {
>  /**
>   * PERF_RECORD_AUX::flags bits
>   */
> -#define PERF_AUX_FLAG_TRUNCATED		0x01	/* record was truncated to fit */
> -#define PERF_AUX_FLAG_OVERWRITE		0x02	/* snapshot from overwrite mode */
> -#define PERF_AUX_FLAG_PARTIAL		0x04	/* record contains gaps */
> -#define PERF_AUX_FLAG_COLLISION		0x08	/* sample collided with another */
> +#define PERF_AUX_FLAG_TRUNCATED			0x01	/* record was truncated to fit */
> +#define PERF_AUX_FLAG_OVERWRITE			0x02	/* snapshot from overwrite mode */
> +#define PERF_AUX_FLAG_PARTIAL			0x04	/* record contains gaps */
> +#define PERF_AUX_FLAG_COLLISION			0x08	/* sample collided with another */
> +#define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK	0xff00	/* PMU specific trace format type */
>  
>  #define PERF_FLAG_FD_NO_GROUP		(1UL << 0)
>  #define PERF_FLAG_FD_OUTPUT		(1UL << 1)
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 14/14] coresight: etm-perf: Add support for trace buffer format
  2021-01-27  8:55 ` [PATCH V3 14/14] coresight: etm-perf: Add support for trace " Anshuman Khandual
@ 2021-01-27 12:54   ` Peter Zijlstra
  2021-01-27 13:00     ` Al Grant
  2021-01-27 14:12     ` Suzuki K Poulose
  2021-02-16 11:01   ` Mike Leach
  1 sibling, 2 replies; 90+ messages in thread
From: Peter Zijlstra @ 2021-01-27 12:54 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, mathieu.poirier, suzuki.poulose,
	mike.leach, lcherian, linux-kernel, Leo Yan

On Wed, Jan 27, 2021 at 02:25:38PM +0530, Anshuman Khandual wrote:

> It is possible to have a
> perf session where some events end up collecting the trace
> in TMC-ETR while the others in TRBE. Thus we need a way
> to identify the type of the trace for each AUX record.

> diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
> index 9a5ca45..169e6b3 100644
> --- a/include/uapi/linux/perf_event.h
> +++ b/include/uapi/linux/perf_event.h
> @@ -1111,6 +1111,10 @@ enum perf_callchain_context {
>  #define PERF_AUX_FLAG_COLLISION			0x08	/* sample collided with another */
>  #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK	0xff00	/* PMU specific trace format type */
>  
> +/* CoreSight PMU AUX buffer formats */
> +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT	0x0000 /* Default for backward compatibility */
> +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW		0x0100 /* Raw format of the source */

Would CORESIGHT_FORMAT_ETR / CORESIGHT_FORMAT_TRBE be better names?

^ permalink raw reply	[flat|nested] 90+ messages in thread

* RE: [PATCH V3 14/14] coresight: etm-perf: Add support for trace buffer format
  2021-01-27 12:54   ` Peter Zijlstra
@ 2021-01-27 13:00     ` Al Grant
  2021-02-18  3:05       ` Anshuman Khandual
  2021-01-27 14:12     ` Suzuki K Poulose
  1 sibling, 1 reply; 90+ messages in thread
From: Al Grant @ 2021-01-27 13:00 UTC (permalink / raw)
  To: Peter Zijlstra, Anshuman Khandual
  Cc: coresight, linux-kernel, linux-arm-kernel, lcherian, mike.leach

> > +/* CoreSight PMU AUX buffer formats */
> > +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT	0x0000 /*
> Default for backward compatibility */
> > +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW		0x0100 /*
> Raw format of the source */
> 
> Would CORESIGHT_FORMAT_ETR / CORESIGHT_FORMAT_TRBE be better
> names?

Unformatted (raw) streams could be used any time you had a writer dedicated
to a single trace source. So in a situation where you had one ETR per CPU,
it would be appropriate to use an unformatted stream. A TRBE is always
dedicated to a single CPU, but potentially you (i.e. when designing the system)
can do this with any type of trace sink. So the raw/formatted distinction is
really about whether you are combining multiple streams in one buffer or not,
rather than the type of block that is writing into the buffer.

Al 


^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 14/14] coresight: etm-perf: Add support for trace buffer format
  2021-01-27 12:54   ` Peter Zijlstra
  2021-01-27 13:00     ` Al Grant
@ 2021-01-27 14:12     ` Suzuki K Poulose
  1 sibling, 0 replies; 90+ messages in thread
From: Suzuki K Poulose @ 2021-01-27 14:12 UTC (permalink / raw)
  To: Peter Zijlstra, Anshuman Khandual
  Cc: linux-arm-kernel, coresight, mathieu.poirier, mike.leach,
	lcherian, linux-kernel, Leo Yan

Hi Peter

On 1/27/21 12:54 PM, Peter Zijlstra wrote:
> On Wed, Jan 27, 2021 at 02:25:38PM +0530, Anshuman Khandual wrote:
> 
>> It is possible to have a
>> perf session where some events end up collecting the trace
>> in TMC-ETR while the others in TRBE. Thus we need a way
>> to identify the type of the trace for each AUX record.
> 
>> diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
>> index 9a5ca45..169e6b3 100644
>> --- a/include/uapi/linux/perf_event.h
>> +++ b/include/uapi/linux/perf_event.h
>> @@ -1111,6 +1111,10 @@ enum perf_callchain_context {
>>   #define PERF_AUX_FLAG_COLLISION			0x08	/* sample collided with another */
>>   #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK	0xff00	/* PMU specific trace format type */
>>   
>> +/* CoreSight PMU AUX buffer formats */
>> +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT	0x0000 /* Default for backward compatibility */
>> +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW		0x0100 /* Raw format of the source */
> 
> Would CORESIGHT_FORMAT_ETR / CORESIGHT_FORMAT_TRBE be better names?
> 

Not really. The format used by the ETR is CORESIGHT frame formatting. And
there are other sinks that uses the formatting. e.g, TMC-ETB (a sink with
internal memory), TMC-ETF (trace fifo with internal memory). So it is really
not tied to ETR.

As for TRBE, it simply pumps the data thrown at it to the memory. As such
calling it TRBE format would be confusing as the format of the buffer is
really Raw trace thrown at it. This can be inferred from the ETM/ETE
looking at the ID registers, which the userspace perf already captures
in the perf.data. So the decoder perf can look at the perf.data and the
AUX records to interpret the buffer correctly.

Suzuki

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
                   ` (13 preceding siblings ...)
  2021-01-27  8:55 ` [PATCH V3 14/14] coresight: etm-perf: Add support for trace " Anshuman Khandual
@ 2021-01-27 18:50 ` Mathieu Poirier
  2021-02-01 18:44 ` Mathieu Poirier
  15 siblings, 0 replies; 90+ messages in thread
From: Mathieu Poirier @ 2021-01-27 18:50 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, Coresight ML, Suzuki K. Poulose, Mike Leach,
	Linu Cherian, Linux Kernel Mailing List

Hi Anshuman,

I will start looking at your work later this week or early next week.

Mathieu

On Wed, 27 Jan 2021 at 01:55, Anshuman Khandual
<anshuman.khandual@arm.com> wrote:
>
> This series enables future IP trace features Embedded Trace Extension (ETE)
> and Trace Buffer Extension (TRBE). This series depends on the ETM system
> register instruction support series [0] which is available here [1]. This
> series which applies on [1] is avaialble here [2] for quick access.
>
> ETE is the PE (CPU) trace unit for CPUs, implementing future architecture
> extensions. ETE overlaps with the ETMv4 architecture, with additions to
> support the newer architecture features and some restrictions on the
> supported features w.r.t ETMv4. The ETE support is added by extending the
> ETMv4 driver to recognise the ETE and handle the features as exposed by the
> TRCIDRx registers. ETE only supports system instructions access from the
> host CPU. The ETE could be integrated with a TRBE (see below), or with the
> legacy CoreSight trace bus (e.g, ETRs). Thus the ETE follows same firmware
> description as the ETMs and requires a node per instance.
>
> Trace Buffer Extensions (TRBE) implements a per CPU trace buffer, which is
> accessible via the system registers and can be combined with the ETE to
> provide a 1x1 configuration of source & sink. TRBE is being represented
> here as a CoreSight sink. Primary reason is that the ETE source could work
> with other traditional CoreSight sink devices. As TRBE captures the trace
> data which is produced by ETE, it cannot work alone.
>
> TRBE representation here have some distinct deviations from a traditional
> CoreSight sink device. Coresight path between ETE and TRBE are not built
> during boot looking at respective DT or ACPI entries.
>
> Unlike traditional sinks, TRBE can generate interrupts to signal including
> many other things, buffer got filled. The interrupt is a PPI and should be
> communicated from the platform. DT or ACPI entry representing TRBE should
> have the PPI number for a given platform. During perf session, the TRBE IRQ
> handler should capture trace for perf auxiliary buffer before restarting it
> back. System registers being used here to configure ETE and TRBE could be
> referred in the link below.
>
> https://developer.arm.com/docs/ddi0601/g/aarch64-system-registers.
>
> Question:
>
> - Should we implement sysfs based trace sessions for TRBE ?
>
> [0] https://lore.kernel.org/linux-arm-kernel/20210110224850.1880240-1-suzuki.poulose@arm.com/
> [1] https://gitlab.arm.com/linux-arm/linux-skp/-/tree/coresight/etm/sysreg-v7
> [2] https://gitlab.arm.com/linux-arm/linux-anshuman/-/tree/coresight/ete_trbe_v3
>
> Changes in V3:
>
> - Rebased on coresight/next
> - Changed DT bindings for ETE
> - Included additional patches for arm64 nvhe, perf aux buffer flags etc
> - TRBE changes have been captured in the respective patches
>
> Changes in V2:
>
> https://lore.kernel.org/linux-arm-kernel/1610511498-4058-1-git-send-email-anshuman.khandual@arm.com/
>
> - Converted both ETE and TRBE DT bindings into Yaml
> - TRBE changes have been captured in the respective patches
>
> Changes in V1:
>
> https://lore.kernel.org/linux-arm-kernel/1608717823-18387-1-git-send-email-anshuman.khandual@arm.com/
>
> - There are not much ETE changes from Suzuki apart from splitting of the ETE DTS patch
> - TRBE changes have been captured in the respective patches
>
> Changes in RFC:
>
> https://lore.kernel.org/linux-arm-kernel/1605012309-24812-1-git-send-email-anshuman.khandual@arm.com/
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Linu Cherian <lcherian@marvell.com>
> Cc: coresight@lists.linaro.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
>
> Anshuman Khandual (3):
>   coresight: core: Add support for dedicated percpu sinks
>   arm64: Add TRBE definitions
>   coresight: sink: Add TRBE driver
>
> Suzuki K Poulose (11):
>   coresight: etm-perf: Allow an event to use different sinks
>   coresight: Do not scan for graph if none is present
>   coresight: etm4x: Add support for PE OS lock
>   coresight: ete: Add support for ETE sysreg access
>   coresight: ete: Add support for ETE tracing
>   dts: bindings: Document device tree bindings for ETE
>   coresight: etm-perf: Handle stale output handles
>   arm64: nvhe: Allow TRBE access at EL1
>   dts: bindings: Document device tree bindings for Arm TRBE
>   perf: aux: Add flags for the buffer format
>   coresight: etm-perf: Add support for trace buffer format
>
>  Documentation/devicetree/bindings/arm/ete.yaml     |   74 ++
>  Documentation/devicetree/bindings/arm/trbe.yaml    |   49 +
>  Documentation/trace/coresight/coresight-trbe.rst   |   39 +
>  arch/arm64/include/asm/el2_setup.h                 |   19 +
>  arch/arm64/include/asm/kvm_arm.h                   |    2 +
>  arch/arm64/include/asm/sysreg.h                    |   51 +
>  drivers/hwtracing/coresight/Kconfig                |   21 +-
>  drivers/hwtracing/coresight/Makefile               |    1 +
>  drivers/hwtracing/coresight/coresight-core.c       |   16 +-
>  drivers/hwtracing/coresight/coresight-etm-perf.c   |   93 +-
>  drivers/hwtracing/coresight/coresight-etm4x-core.c |  138 ++-
>  .../hwtracing/coresight/coresight-etm4x-sysfs.c    |   19 +-
>  drivers/hwtracing/coresight/coresight-etm4x.h      |   81 +-
>  drivers/hwtracing/coresight/coresight-platform.c   |    6 +
>  drivers/hwtracing/coresight/coresight-trbe.c       | 1025 ++++++++++++++++++++
>  drivers/hwtracing/coresight/coresight-trbe.h       |  160 +++
>  include/linux/coresight.h                          |   12 +
>  include/uapi/linux/perf_event.h                    |   13 +-
>  18 files changed, 1759 insertions(+), 60 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/ete.yaml
>  create mode 100644 Documentation/devicetree/bindings/arm/trbe.yaml
>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
>
> --
> 2.7.4
>

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks
  2021-01-27  8:55 ` [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual
@ 2021-01-28  9:16   ` Suzuki K Poulose
  2021-02-04 18:34     ` Mathieu Poirier
  2021-02-16 10:21     ` Anshuman Khandual
  2021-02-15 16:27   ` Mike Leach
  1 sibling, 2 replies; 90+ messages in thread
From: Suzuki K Poulose @ 2021-01-28  9:16 UTC (permalink / raw)
  To: Anshuman Khandual, linux-arm-kernel, coresight
  Cc: mathieu.poirier, mike.leach, lcherian, linux-kernel

On 1/27/21 8:55 AM, Anshuman Khandual wrote:
> Add support for dedicated sinks that are bound to individual CPUs. (e.g,
> TRBE). To allow quicker access to the sink for a given CPU bound source,
> keep a percpu array of the sink devices. Also, add support for building
> a path to the CPU local sink from the ETM.
> 
> This adds a new percpu sink type CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM.
> This new sink type is exclusively available and can only work with percpu
> source type device CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC.
> 
> This defines a percpu structure that accommodates a single coresight_device
> which can be used to store an initialized instance from a sink driver. As
> these sinks are exclusively linked and dependent on corresponding percpu
> sources devices, they should also be the default sink device during a perf
> session.
> 
> Outwards device connections are scanned while establishing paths between a
> source and a sink device. But such connections are not present for certain
> percpu source and sink devices which are exclusively linked and dependent.
> Build the path directly and skip connection scanning for such devices.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> Changes in V3:
> 
> - Updated coresight_find_default_sink()
> 
>   drivers/hwtracing/coresight/coresight-core.c | 16 ++++++++++++++--
>   include/linux/coresight.h                    | 12 ++++++++++++
>   2 files changed, 26 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index 0062c89..4795e28 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -23,6 +23,7 @@
>   #include "coresight-priv.h"
>   
>   static DEFINE_MUTEX(coresight_mutex);
> +DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
>   
>   /**
>    * struct coresight_node - elements of a path, from source to sink
> @@ -784,6 +785,13 @@ static int _coresight_build_path(struct coresight_device *csdev,
>   	if (csdev == sink)
>   		goto out;
>   
> +	if (coresight_is_percpu_source(csdev) && coresight_is_percpu_sink(sink) &&
> +	    sink == per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev))) {
> +		_coresight_build_path(sink, sink, path);
> +		found = true;
> +		goto out;
> +	}
> +
>   	/* Not a sink - recursively explore each port found on this element */
>   	for (i = 0; i < csdev->pdata->nr_outport; i++) {
>   		struct coresight_device *child_dev;
> @@ -999,8 +1007,12 @@ coresight_find_default_sink(struct coresight_device *csdev)
>   	int depth = 0;
>   
>   	/* look for a default sink if we have not found for this device */
> -	if (!csdev->def_sink)
> -		csdev->def_sink = coresight_find_sink(csdev, &depth);
> +	if (!csdev->def_sink) {
> +		if (coresight_is_percpu_source(csdev))
> +			csdev->def_sink = per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev));
> +		if (!csdev->def_sink)
> +			csdev->def_sink = coresight_find_sink(csdev, &depth);
> +	}
>   	return csdev->def_sink;
>   }
>   
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index 976ec26..bc3a5ca 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -50,6 +50,7 @@ enum coresight_dev_subtype_sink {
>   	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
>   	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
>   	CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
> +	CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
>   };
>   
>   enum coresight_dev_subtype_link {
> @@ -428,6 +429,17 @@ static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 o
>   		csa->write(val, offset, false, true);
>   }
>   
> +static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
> +{
> +	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
> +	       csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;

Please add () around the last line. Same below.

> +}
> +
> +static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
> +{
> +	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
> +	       csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
> +}
>   #else	/* !CONFIG_64BIT */
>   
>   static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
> 

With the above :

Tested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 09/14] arm64: Add TRBE definitions
  2021-01-27  8:55 ` [PATCH V3 09/14] arm64: Add TRBE definitions Anshuman Khandual
@ 2021-01-28  9:31   ` Suzuki K Poulose
  2021-01-28 17:18   ` Catalin Marinas
  1 sibling, 0 replies; 90+ messages in thread
From: Suzuki K Poulose @ 2021-01-28  9:31 UTC (permalink / raw)
  To: Anshuman Khandual, linux-arm-kernel, coresight
  Cc: mathieu.poirier, mike.leach, lcherian, linux-kernel, Will Deacon,
	Catalin Marinas, Mark Rutland

On 1/27/21 8:55 AM, Anshuman Khandual wrote:
> This adds TRBE related registers and corresponding feature macros.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>

> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>

Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>

> ---
> Changes in V3:
> 
> - ID_AA64DFR0_TRBE_SHIFT has been moved here from the TRBE driver
> - Changed TRBLIMITR_TRIG_MODE_SHIFT as 3
> 
>   arch/arm64/include/asm/sysreg.h | 50 +++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 50 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 4acff97..85ae4db 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -329,6 +329,55 @@
>   
>   /*** End of Statistical Profiling Extension ***/
>   
> +/*
> + * TRBE Registers
> + */
> +#define SYS_TRBLIMITR_EL1		sys_reg(3, 0, 9, 11, 0)
> +#define SYS_TRBPTR_EL1			sys_reg(3, 0, 9, 11, 1)
> +#define SYS_TRBBASER_EL1		sys_reg(3, 0, 9, 11, 2)
> +#define SYS_TRBSR_EL1			sys_reg(3, 0, 9, 11, 3)
> +#define SYS_TRBMAR_EL1			sys_reg(3, 0, 9, 11, 4)
> +#define SYS_TRBTRG_EL1			sys_reg(3, 0, 9, 11, 6)
> +#define SYS_TRBIDR_EL1			sys_reg(3, 0, 9, 11, 7)
> +
> +#define TRBLIMITR_LIMIT_MASK		GENMASK_ULL(51, 0)
> +#define TRBLIMITR_LIMIT_SHIFT		12
> +#define TRBLIMITR_NVM			BIT(5)
> +#define TRBLIMITR_TRIG_MODE_MASK	GENMASK(1, 0)
> +#define TRBLIMITR_TRIG_MODE_SHIFT	3
> +#define TRBLIMITR_FILL_MODE_MASK	GENMASK(1, 0)
> +#define TRBLIMITR_FILL_MODE_SHIFT	1
> +#define TRBLIMITR_ENABLE		BIT(0)
> +#define TRBPTR_PTR_MASK			GENMASK_ULL(63, 0)
> +#define TRBPTR_PTR_SHIFT		0
> +#define TRBBASER_BASE_MASK		GENMASK_ULL(51, 0)
> +#define TRBBASER_BASE_SHIFT		12
> +#define TRBSR_EC_MASK			GENMASK(5, 0)
> +#define TRBSR_EC_SHIFT			26
> +#define TRBSR_IRQ			BIT(22)
> +#define TRBSR_TRG			BIT(21)
> +#define TRBSR_WRAP			BIT(20)
> +#define TRBSR_ABORT			BIT(18)
> +#define TRBSR_STOP			BIT(17)
> +#define TRBSR_MSS_MASK			GENMASK(15, 0)
> +#define TRBSR_MSS_SHIFT			0
> +#define TRBSR_BSC_MASK			GENMASK(5, 0)
> +#define TRBSR_BSC_SHIFT			0
> +#define TRBSR_FSC_MASK			GENMASK(5, 0)
> +#define TRBSR_FSC_SHIFT			0
> +#define TRBMAR_SHARE_MASK		GENMASK(1, 0)
> +#define TRBMAR_SHARE_SHIFT		8
> +#define TRBMAR_OUTER_MASK		GENMASK(3, 0)
> +#define TRBMAR_OUTER_SHIFT		4
> +#define TRBMAR_INNER_MASK		GENMASK(3, 0)
> +#define TRBMAR_INNER_SHIFT		0
> +#define TRBTRG_TRG_MASK			GENMASK(31, 0)
> +#define TRBTRG_TRG_SHIFT		0
> +#define TRBIDR_FLAG			BIT(5)
> +#define TRBIDR_PROG			BIT(4)
> +#define TRBIDR_ALIGN_MASK		GENMASK(3, 0)
> +#define TRBIDR_ALIGN_SHIFT		0
> +
>   #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
>   #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
>   
> @@ -831,6 +880,7 @@
>   #define ID_AA64MMFR2_CNP_SHIFT		0
>   
>   /* id_aa64dfr0 */
> +#define ID_AA64DFR0_TRBE_SHIFT		44
>   #define ID_AA64DFR0_TRACE_FILT_SHIFT	40
>   #define ID_AA64DFR0_DOUBLELOCK_SHIFT	36
>   #define ID_AA64DFR0_PMSVER_SHIFT	32
> 


^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1
  2021-01-27  9:58   ` Marc Zyngier
@ 2021-01-28  9:34     ` Suzuki K Poulose
  2021-01-28  9:46       ` Marc Zyngier
  0 siblings, 1 reply; 90+ messages in thread
From: Suzuki K Poulose @ 2021-01-28  9:34 UTC (permalink / raw)
  To: Marc Zyngier, Anshuman Khandual
  Cc: linux-arm-kernel, coresight, mathieu.poirier, mike.leach,
	lcherian, linux-kernel, Will Deacon, Catalin Marinas,
	Mark Rutland

On 1/27/21 9:58 AM, Marc Zyngier wrote:
> On 2021-01-27 08:55, Anshuman Khandual wrote:
>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>
>> When the kernel is booted at EL2 in a nvhe configuration,
>> enable the TRBE access to the EL1. The EL1 still can't trace
>> EL2, unless EL2 permits explicitly via TRFCR_EL2.E2TRE.
>>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Marc Zyngier <maz@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> cc: Anshuman Khandual <anshuman.khandual@arm.com>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> 
> Acked-by: Marc Zyngier <maz@kernel.org>
> 
> One comment below, though:
> 
>> ---
>>  arch/arm64/include/asm/el2_setup.h | 19 +++++++++++++++++++
>>  arch/arm64/include/asm/kvm_arm.h   |  2 ++
>>  2 files changed, 21 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/el2_setup.h
>> b/arch/arm64/include/asm/el2_setup.h
>> index a7f5a1b..05ecce9 100644
>> --- a/arch/arm64/include/asm/el2_setup.h
>> +++ b/arch/arm64/include/asm/el2_setup.h
>> @@ -72,6 +72,25 @@
>>  .endif
>>
>>  3:
>> +
>> +.ifeqs    "\mode", "nvhe"
>> +    /*
>> +     * If the Trace Buffer is available, allow
>> +     * the EL1 to own it. Note that EL1 cannot
>> +     * trace the EL2, as it is prevented by
>> +     * TRFCR_EL2.E2TRE == 0.
>> +     */
>> +    ubfx    x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4
>> +    cbz    x0, 1f
>> +
>> +    mrs_s    x0, SYS_TRBIDR_EL1
>> +    and    x0, x0, TRBIDR_PROG
>> +    cbnz    x0, 1f
>> +    mov    x0, #(MDCR_EL2_E2TB_EL1_OWN << MDCR_EL2_E2TB_SHIFT)
>> +    orr    x2, x2, x0
>> +.endif
>> +
>> +1:
> 
> Note that this will (badly) conflict with the late-VHE patches[1],
> where this code path has been reworked.

Thanks for the heads up. We will need to see how things get merged.
Ideally this patch and the previous one (TRBE definitions could go
via the arm64 tree / kvm tree), in which case we could rebase these
two patches on the respective tree.

Cheers
Suzuki

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1
  2021-01-28  9:34     ` Suzuki K Poulose
@ 2021-01-28  9:46       ` Marc Zyngier
  2021-01-28  9:48         ` Suzuki K Poulose
  0 siblings, 1 reply; 90+ messages in thread
From: Marc Zyngier @ 2021-01-28  9:46 UTC (permalink / raw)
  To: Suzuki K Poulose
  Cc: Anshuman Khandual, linux-arm-kernel, coresight, mathieu.poirier,
	mike.leach, lcherian, linux-kernel, Will Deacon, Catalin Marinas,
	Mark Rutland

On 2021-01-28 09:34, Suzuki K Poulose wrote:
> On 1/27/21 9:58 AM, Marc Zyngier wrote:
>> On 2021-01-27 08:55, Anshuman Khandual wrote:
>>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>> 
>>> When the kernel is booted at EL2 in a nvhe configuration,
>>> enable the TRBE access to the EL1. The EL1 still can't trace
>>> EL2, unless EL2 permits explicitly via TRFCR_EL2.E2TRE.
>>> 
>>> Cc: Will Deacon <will@kernel.org>
>>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>>> Cc: Marc Zyngier <maz@kernel.org>
>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>> cc: Anshuman Khandual <anshuman.khandual@arm.com>
>>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> 
>> Acked-by: Marc Zyngier <maz@kernel.org>
>> 
>> One comment below, though:
>> 
>>> ---
>>>  arch/arm64/include/asm/el2_setup.h | 19 +++++++++++++++++++
>>>  arch/arm64/include/asm/kvm_arm.h   |  2 ++
>>>  2 files changed, 21 insertions(+)
>>> 
>>> diff --git a/arch/arm64/include/asm/el2_setup.h
>>> b/arch/arm64/include/asm/el2_setup.h
>>> index a7f5a1b..05ecce9 100644
>>> --- a/arch/arm64/include/asm/el2_setup.h
>>> +++ b/arch/arm64/include/asm/el2_setup.h
>>> @@ -72,6 +72,25 @@
>>>  .endif
>>> 
>>>  3:
>>> +
>>> +.ifeqs    "\mode", "nvhe"
>>> +    /*
>>> +     * If the Trace Buffer is available, allow
>>> +     * the EL1 to own it. Note that EL1 cannot
>>> +     * trace the EL2, as it is prevented by
>>> +     * TRFCR_EL2.E2TRE == 0.
>>> +     */
>>> +    ubfx    x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4
>>> +    cbz    x0, 1f
>>> +
>>> +    mrs_s    x0, SYS_TRBIDR_EL1
>>> +    and    x0, x0, TRBIDR_PROG
>>> +    cbnz    x0, 1f
>>> +    mov    x0, #(MDCR_EL2_E2TB_EL1_OWN << MDCR_EL2_E2TB_SHIFT)
>>> +    orr    x2, x2, x0
>>> +.endif
>>> +
>>> +1:
>> 
>> Note that this will (badly) conflict with the late-VHE patches[1],
>> where this code path has been reworked.
> 
> Thanks for the heads up. We will need to see how things get merged.
> Ideally this patch and the previous one (TRBE definitions could go
> via the arm64 tree / kvm tree), in which case we could rebase these
> two patches on the respective tree.

I think the current plan of action is to go via the arm64 tree,
given that there is nothing really KVM specific there. I'll respin
the series one last (hopefully!) time on Monday. Let me know if
you need a hand with the rebasing.

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1
  2021-01-28  9:46       ` Marc Zyngier
@ 2021-01-28  9:48         ` Suzuki K Poulose
  0 siblings, 0 replies; 90+ messages in thread
From: Suzuki K Poulose @ 2021-01-28  9:48 UTC (permalink / raw)
  To: Marc Zyngier
  Cc: Anshuman Khandual, linux-arm-kernel, coresight, mathieu.poirier,
	mike.leach, lcherian, linux-kernel, Will Deacon, Catalin Marinas,
	Mark Rutland

On 1/28/21 9:46 AM, Marc Zyngier wrote:
> On 2021-01-28 09:34, Suzuki K Poulose wrote:
>> On 1/27/21 9:58 AM, Marc Zyngier wrote:
>>> On 2021-01-27 08:55, Anshuman Khandual wrote:
>>>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>>>
>>>> When the kernel is booted at EL2 in a nvhe configuration,
>>>> enable the TRBE access to the EL1. The EL1 still can't trace
>>>> EL2, unless EL2 permits explicitly via TRFCR_EL2.E2TRE.
>>>>
>>>> Cc: Will Deacon <will@kernel.org>
>>>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>>>> Cc: Marc Zyngier <maz@kernel.org>
>>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>>> cc: Anshuman Khandual <anshuman.khandual@arm.com>
>>>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>>>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>>>
>>> Acked-by: Marc Zyngier <maz@kernel.org>
>>>
>>> One comment below, though:
>>>
>>>> ---
>>>>  arch/arm64/include/asm/el2_setup.h | 19 +++++++++++++++++++
>>>>  arch/arm64/include/asm/kvm_arm.h   |  2 ++
>>>>  2 files changed, 21 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/include/asm/el2_setup.h
>>>> b/arch/arm64/include/asm/el2_setup.h
>>>> index a7f5a1b..05ecce9 100644
>>>> --- a/arch/arm64/include/asm/el2_setup.h
>>>> +++ b/arch/arm64/include/asm/el2_setup.h
>>>> @@ -72,6 +72,25 @@
>>>>  .endif
>>>>
>>>>  3:
>>>> +
>>>> +.ifeqs    "\mode", "nvhe"
>>>> +    /*
>>>> +     * If the Trace Buffer is available, allow
>>>> +     * the EL1 to own it. Note that EL1 cannot
>>>> +     * trace the EL2, as it is prevented by
>>>> +     * TRFCR_EL2.E2TRE == 0.
>>>> +     */
>>>> +    ubfx    x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4
>>>> +    cbz    x0, 1f
>>>> +
>>>> +    mrs_s    x0, SYS_TRBIDR_EL1
>>>> +    and    x0, x0, TRBIDR_PROG
>>>> +    cbnz    x0, 1f
>>>> +    mov    x0, #(MDCR_EL2_E2TB_EL1_OWN << MDCR_EL2_E2TB_SHIFT)
>>>> +    orr    x2, x2, x0
>>>> +.endif
>>>> +
>>>> +1:
>>>
>>> Note that this will (badly) conflict with the late-VHE patches[1],
>>> where this code path has been reworked.
>>
>> Thanks for the heads up. We will need to see how things get merged.
>> Ideally this patch and the previous one (TRBE definitions could go
>> via the arm64 tree / kvm tree), in which case we could rebase these
>> two patches on the respective tree.
> 
> I think the current plan of action is to go via the arm64 tree,
> given that there is nothing really KVM specific there. I'll respin
> the series one last (hopefully!) time on Monday. Let me know if
> you need a hand with the rebasing.

Sounds good, will rebase it on top of that then.

Cheers
Suzuki

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 09/14] arm64: Add TRBE definitions
  2021-01-27  8:55 ` [PATCH V3 09/14] arm64: Add TRBE definitions Anshuman Khandual
  2021-01-28  9:31   ` Suzuki K Poulose
@ 2021-01-28 17:18   ` Catalin Marinas
  2021-02-15 18:06     ` Mike Leach
  1 sibling, 1 reply; 90+ messages in thread
From: Catalin Marinas @ 2021-01-28 17:18 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, mathieu.poirier, suzuki.poulose,
	linux-kernel, lcherian, mike.leach

On Wed, Jan 27, 2021 at 02:25:33PM +0530, Anshuman Khandual wrote:
> This adds TRBE related registers and corresponding feature macros.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>

Acked-by: Catalin Marinas <catalin.marinas@arm.com>

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE
  2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
                   ` (14 preceding siblings ...)
  2021-01-27 18:50 ` [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Mathieu Poirier
@ 2021-02-01 18:44 ` Mathieu Poirier
  2021-02-18  4:23   ` Anshuman Khandual
  15 siblings, 1 reply; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-01 18:44 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel

On Wed, Jan 27, 2021 at 02:25:24PM +0530, Anshuman Khandual wrote:
> This series enables future IP trace features Embedded Trace Extension (ETE)
> and Trace Buffer Extension (TRBE). This series depends on the ETM system
> register instruction support series [0] which is available here [1]. This
> series which applies on [1] is avaialble here [2] for quick access.
> 
> ETE is the PE (CPU) trace unit for CPUs, implementing future architecture
> extensions. ETE overlaps with the ETMv4 architecture, with additions to
> support the newer architecture features and some restrictions on the
> supported features w.r.t ETMv4. The ETE support is added by extending the
> ETMv4 driver to recognise the ETE and handle the features as exposed by the
> TRCIDRx registers. ETE only supports system instructions access from the
> host CPU. The ETE could be integrated with a TRBE (see below), or with the
> legacy CoreSight trace bus (e.g, ETRs). Thus the ETE follows same firmware
> description as the ETMs and requires a node per instance. 
> 
> Trace Buffer Extensions (TRBE) implements a per CPU trace buffer, which is
> accessible via the system registers and can be combined with the ETE to
> provide a 1x1 configuration of source & sink. TRBE is being represented
> here as a CoreSight sink. Primary reason is that the ETE source could work
> with other traditional CoreSight sink devices. As TRBE captures the trace
> data which is produced by ETE, it cannot work alone.
> 
> TRBE representation here have some distinct deviations from a traditional
> CoreSight sink device. Coresight path between ETE and TRBE are not built
> during boot looking at respective DT or ACPI entries.
> 
> Unlike traditional sinks, TRBE can generate interrupts to signal including
> many other things, buffer got filled. The interrupt is a PPI and should be
> communicated from the platform. DT or ACPI entry representing TRBE should
> have the PPI number for a given platform. During perf session, the TRBE IRQ
> handler should capture trace for perf auxiliary buffer before restarting it
> back. System registers being used here to configure ETE and TRBE could be
> referred in the link below.
> 
> https://developer.arm.com/docs/ddi0601/g/aarch64-system-registers.

This set is giving me several checkpatch.pl warnings...  Those about complex
macros and DT bindings are fine but everything else should have been addressed
by now.  Since this is your first patchset I will carry on but I expect future
submissions to be clean. 

> 
> Question:
> 
> - Should we implement sysfs based trace sessions for TRBE ?
> 
> [0] https://lore.kernel.org/linux-arm-kernel/20210110224850.1880240-1-suzuki.poulose@arm.com/
> [1] https://gitlab.arm.com/linux-arm/linux-skp/-/tree/coresight/etm/sysreg-v7
> [2] https://gitlab.arm.com/linux-arm/linux-anshuman/-/tree/coresight/ete_trbe_v3
> 
> Changes in V3:
> 
> - Rebased on coresight/next
> - Changed DT bindings for ETE
> - Included additional patches for arm64 nvhe, perf aux buffer flags etc
> - TRBE changes have been captured in the respective patches
> 
> Changes in V2:
> 
> https://lore.kernel.org/linux-arm-kernel/1610511498-4058-1-git-send-email-anshuman.khandual@arm.com/
> 
> - Converted both ETE and TRBE DT bindings into Yaml
> - TRBE changes have been captured in the respective patches
>  
> Changes in V1:
> 
> https://lore.kernel.org/linux-arm-kernel/1608717823-18387-1-git-send-email-anshuman.khandual@arm.com/
> 
> - There are not much ETE changes from Suzuki apart from splitting of the ETE DTS patch
> - TRBE changes have been captured in the respective patches
> 
> Changes in RFC:
> 
> https://lore.kernel.org/linux-arm-kernel/1605012309-24812-1-git-send-email-anshuman.khandual@arm.com/
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Linu Cherian <lcherian@marvell.com>
> Cc: coresight@lists.linaro.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> 
> Anshuman Khandual (3):
>   coresight: core: Add support for dedicated percpu sinks
>   arm64: Add TRBE definitions
>   coresight: sink: Add TRBE driver
> 
> Suzuki K Poulose (11):
>   coresight: etm-perf: Allow an event to use different sinks
>   coresight: Do not scan for graph if none is present
>   coresight: etm4x: Add support for PE OS lock
>   coresight: ete: Add support for ETE sysreg access
>   coresight: ete: Add support for ETE tracing
>   dts: bindings: Document device tree bindings for ETE
>   coresight: etm-perf: Handle stale output handles
>   arm64: nvhe: Allow TRBE access at EL1
>   dts: bindings: Document device tree bindings for Arm TRBE
>   perf: aux: Add flags for the buffer format
>   coresight: etm-perf: Add support for trace buffer format
> 
>  Documentation/devicetree/bindings/arm/ete.yaml     |   74 ++
>  Documentation/devicetree/bindings/arm/trbe.yaml    |   49 +
>  Documentation/trace/coresight/coresight-trbe.rst   |   39 +
>  arch/arm64/include/asm/el2_setup.h                 |   19 +
>  arch/arm64/include/asm/kvm_arm.h                   |    2 +
>  arch/arm64/include/asm/sysreg.h                    |   51 +
>  drivers/hwtracing/coresight/Kconfig                |   21 +-
>  drivers/hwtracing/coresight/Makefile               |    1 +
>  drivers/hwtracing/coresight/coresight-core.c       |   16 +-
>  drivers/hwtracing/coresight/coresight-etm-perf.c   |   93 +-
>  drivers/hwtracing/coresight/coresight-etm4x-core.c |  138 ++-
>  .../hwtracing/coresight/coresight-etm4x-sysfs.c    |   19 +-
>  drivers/hwtracing/coresight/coresight-etm4x.h      |   81 +-
>  drivers/hwtracing/coresight/coresight-platform.c   |    6 +
>  drivers/hwtracing/coresight/coresight-trbe.c       | 1025 ++++++++++++++++++++
>  drivers/hwtracing/coresight/coresight-trbe.h       |  160 +++
>  include/linux/coresight.h                          |   12 +
>  include/uapi/linux/perf_event.h                    |   13 +-
>  18 files changed, 1759 insertions(+), 60 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/ete.yaml
>  create mode 100644 Documentation/devicetree/bindings/arm/trbe.yaml
>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
> 
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks
  2021-01-27  8:55 ` [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
@ 2021-02-01 23:17   ` Mathieu Poirier
  2021-02-02  9:42     ` Suzuki K Poulose
  0 siblings, 1 reply; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-01 23:17 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel

Hi Anshuman,

I have started reviewing this set.  As it is quite voluminous comments will
come over serveral days.  I will let you know when I am done.

On Wed, Jan 27, 2021 at 02:25:25PM +0530, Anshuman Khandual wrote:
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> When there are multiple sinks on the system, in the absence
> of a specified sink, it is quite possible that a default sink
> for an ETM could be different from that of another ETM. However
> we do not support having multiple sinks for an event yet. This
> patch allows the event to use the default sinks on the ETMs
> where they are scheduled as long as the sinks are of the same
> type.
> 
> e.g, if we have 1x1 topology with per-CPU ETRs, the event can
> use the per-CPU ETR for the session. However, if the sinks
> are of different type, e.g TMC-ETR on one and a custom sink
> on another, the event will only trace on the first detected
> sink.
>

I found the above changelog very confusing - I read it several times and still
couldn't get all of it.  In the end this patch prevents sinks of different types
from being used for session, and this is what the text should reflect.
 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Tested-by: Linu Cherian <lcherian@marvell.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm-perf.c | 48 +++++++++++++++++++-----
>  1 file changed, 38 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
> index bdc34ca..eb9e7e9 100644
> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> @@ -204,6 +204,13 @@ static void etm_free_aux(void *data)
>  	schedule_work(&event_data->work);
>  }
>  
> +static bool sinks_match(struct coresight_device *a, struct coresight_device *b)
> +{
> +	if (!a || !b)
> +		return false;
> +	return (sink_ops(a) == sink_ops(b));

Yes

> +}
> +
>  static void *etm_setup_aux(struct perf_event *event, void **pages,
>  			   int nr_pages, bool overwrite)
>  {
> @@ -212,6 +219,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>  	cpumask_t *mask;
>  	struct coresight_device *sink = NULL;

        struct coresight_device *user_sink = NULL;

>  	struct etm_event_data *event_data = NULL;
> +	bool sink_forced = false;
>  
>  	event_data = alloc_event_data(cpu);
>  	if (!event_data)
> @@ -222,6 +230,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>  	if (event->attr.config2) {
>  		id = (u32)event->attr.config2;
>  		sink = coresight_get_sink_by_id(id);

                user_sink = coresight_get_sink_by_id(id);

> +		sink_forced = true;
>  	}
>  
>  	mask = &event_data->mask;
> @@ -235,7 +244,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>  	 */
>  	for_each_cpu(cpu, mask) {
>  		struct list_head *path;
> -		struct coresight_device *csdev;

                struct coresight_device *last_sink = NULL;

> +		struct coresight_device *csdev, *new_sink;
>  
>  		csdev = per_cpu(csdev_src, cpu);
>  		/*
> @@ -249,21 +258,35 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>  		}
>  
>  		/*
> -		 * No sink provided - look for a default sink for one of the
> -		 * devices. At present we only support topology where all CPUs
> -		 * use the same sink [N:1], so only need to find one sink. The
> -		 * coresight_build_path later will remove any CPU that does not
> -		 * attach to the sink, or if we have not found a sink.
> +		 * No sink provided - look for a default sink for all the devices.
> +		 * We only support multiple sinks, only if all the default sinks
> +		 * are of the same type, so that the sink buffer can be shared
> +		 * as the event moves around. We don't trace on a CPU if it can't

s/can't/can't./

> +		 *

Extra line

>  		 */
> -		if (!sink)
> -			sink = coresight_find_default_sink(csdev);
> +		if (!sink_forced) {
> +			new_sink = coresight_find_default_sink(csdev);
> +			if (!new_sink) {
> +				cpumask_clear_cpu(cpu, mask);
> +				continue;
> +			}
> +			/* Skip checks for the first sink */
> +			if (!sink) {
> +			       sink = new_sink;
> +			} else if (!sinks_match(new_sink, sink)) {
> +				cpumask_clear_cpu(cpu, mask);
> +				continue;
> +			}
> +		} else {
> +			new_sink = sink;
> +		}

                if (!user_sink) {
                        /* find default sink for this CPU */
                        sink = coresight_find_default_sink(csdev);
                        if (!sink) {
                                cpumask_clear_cpu(cpu, mask);
                                continue;
                        }

                        /* Chech new sink with last sink */
                        if (last_sink && !sink_match(last_sink, sink)) {
                                cpumask_clear_cpu(cpu, mask);
                                continue;
                        }

                        last_sink = sink;
                } else {
                        sink = user_sink;
                }

>  
>  		/*
>  		 * Building a path doesn't enable it, it simply builds a
>  		 * list of devices from source to sink that can be
>  		 * referenced later when the path is actually needed.
>  		 */
> -		path = coresight_build_path(csdev, sink);
> +		path = coresight_build_path(csdev, new_sink);
>  		if (IS_ERR(path)) {
>  			cpumask_clear_cpu(cpu, mask);
>  			continue;
> @@ -284,7 +307,12 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>  	if (!sink_ops(sink)->alloc_buffer || !sink_ops(sink)->free_buffer)
>  		goto err;
>  
> -	/* Allocate the sink buffer for this session */
> +	/*
> +	 * Allocate the sink buffer for this session. All the sinks
> +	 * where this event can be scheduled are ensured to be of the
> +	 * same type. Thus the same sink configuration is used by the
> +	 * sinks.
> +	 */
>  	event_data->snk_config =
>  			sink_ops(sink)->alloc_buffer(sink, event, pages,
>  						     nr_pages, overwrite);
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 02/14] coresight: Do not scan for graph if none is present
  2021-01-27  8:55 ` [PATCH V3 02/14] coresight: Do not scan for graph if none is present Anshuman Khandual
@ 2021-02-01 23:44   ` Mathieu Poirier
  2021-02-02 11:10   ` Mike Leach
  1 sibling, 0 replies; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-01 23:44 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel

On Wed, Jan 27, 2021 at 02:25:26PM +0530, Anshuman Khandual wrote:
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> If a graph node is not found for a given node, of_get_next_endpoint()
> will emit the following error message :
> 
>  OF: graph: no port node found in /<node_name>
> 
> If the given component doesn't have any explicit connections (e.g,
> ETE) we could simply ignore the graph parsing.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-platform.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c
> index 3629b78..c594f45 100644
> --- a/drivers/hwtracing/coresight/coresight-platform.c
> +++ b/drivers/hwtracing/coresight/coresight-platform.c
> @@ -90,6 +90,12 @@ static void of_coresight_get_ports_legacy(const struct device_node *node,
>  	struct of_endpoint endpoint;
>  	int in = 0, out = 0;
>  
> +	/*
> +	 * Avoid warnings in of_graph_get_next_endpoint()
> +	 * if the device doesn't have any graph connections
> +	 */
> +	if (!of_graph_is_present(node))
> +		return;

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

>  	do {
>  		ep = of_graph_get_next_endpoint(node, ep);
>  		if (!ep)
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
       [not found]   ` <12cdc8ca-0a69-bfba-bbcd-fb392d6ca051@arm.com>
@ 2021-02-02  5:55     ` Anshuman Khandual
  0 siblings, 0 replies; 90+ messages in thread
From: Anshuman Khandual @ 2021-02-02  5:55 UTC (permalink / raw)
  To: Suzuki K Poulose, linux-arm-kernel, coresight
  Cc: mathieu.poirier, mike.leach, lcherian, linux-kernel


On 1/29/21 3:53 PM, Suzuki K Poulose wrote:
> Hi Anshuman
> 
> On 1/27/21 8:55 AM, Anshuman Khandual wrote:
>> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
>> accessible via the system registers. The TRBE supports different addressing
>> modes including CPU virtual address and buffer modes including the circular
>> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
>> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
>> access to the trace buffer could be prohibited by a higher exception level
>> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
>> private interrupt (PPI) on address translation errors and when the buffer
>> is full. Overall implementation here is inspired from the Arm SPE driver.
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> 
> This version looks functionally correct to me. There are some minor
> issues with the devm_ allocated memory and some driver hardening comments.
> I ran this on a model and have tested this with various scenarios.

Okay.

> 
>> ---
>> Changes in V3:
>>
>> - Added new DT bindings document TRBE.yaml
>> - Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3
>> - Dropped isb() from trbe_reset_local()
>> - Dropped gap between (void *) and buf->trbe_base
>> - Changed 'int' to 'unsigned int' in is_trbe_available()
>> - Dropped unused function set_trbe_running(), set_trbe_virtual_mode(),
>>    set_trbe_enabled() and set_trbe_limit_pointer()
>> - Changed get_trbe_flag_update(), is_trbe_programmable() and
>>    get_trbe_address_align() to accept TRBIDR value
>> - Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), is_trbe_trg(),
>>    is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value
>> - Dropped snapshot mode condition in arm_trbe_alloc_buffer()
>> - Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled
>> - Compute trbe_limit before trbe_write to get the updated handle
>> - Added trbe_stop_and_truncate_event()
>> - Dropped trbe_handle_fatal()
>>
>>   Documentation/trace/coresight/coresight-trbe.rst |   39 +
>>   arch/arm64/include/asm/sysreg.h                  |    1 +
>>   drivers/hwtracing/coresight/Kconfig              |   11 +
>>   drivers/hwtracing/coresight/Makefile             |    1 +
>>   drivers/hwtracing/coresight/coresight-trbe.c     | 1023 ++++++++++++++++++++++
>>   drivers/hwtracing/coresight/coresight-trbe.h     |  160 ++++
>>   6 files changed, 1235 insertions(+)
>>   create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
>>   create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
>>   create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
>>
>> diff --git a/Documentation/trace/coresight/coresight-trbe.rst b/Documentation/trace/coresight/coresight-trbe.rst
>> new file mode 100644
>> index 0000000..1cbb819
>> --- /dev/null
>> +++ b/Documentation/trace/coresight/coresight-trbe.rst
>> @@ -0,0 +1,39 @@
>> +.. SPDX-License-Identifier: GPL-2.0
>> +
>> +==============================
>> +Trace Buffer Extension (TRBE).
>> +==============================
>> +
>> +    :Author:   Anshuman Khandual <anshuman.khandual@arm.com>
>> +    :Date:     November 2020
>> +
>> +Hardware Description
>> +--------------------
>> +
>> +Trace Buffer Extension (TRBE) is a percpu hardware which captures in system
>> +memory, CPU traces generated from a corresponding percpu tracing unit. This
>> +gets plugged in as a coresight sink device because the corresponding trace
>> +genarators (ETE), are plugged in as source device.
>> +
>> +The TRBE is not compliant to CoreSight architecture specifications, but is
>> +driven via the CoreSight driver framework to support the ETE (which is
>> +CoreSight compliant) integration.
>> +
>> +Sysfs files and directories
>> +---------------------------
>> +
>> +The TRBE devices appear on the existing coresight bus alongside the other
>> +coresight devices::
>> +
>> +    >$ ls /sys/bus/coresight/devices
>> +    trbe0  trbe1  trbe2 trbe3
>> +
>> +The ``trbe<N>`` named TRBEs are associated with a CPU.::
>> +
>> +    >$ ls /sys/bus/coresight/devices/trbe0/
>> +        align dbm
>> +
>> +*Key file items are:-*
>> +   * ``align``: TRBE write pointer alignment
>> +   * ``dbm``: TRBE updates memory with access and dirty flags
>> +
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 85ae4db..9e2e9b7 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -97,6 +97,7 @@
>>   #define SET_PSTATE_UAO(x)        __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
>>   #define SET_PSTATE_SSBS(x)        __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
>>   #define SET_PSTATE_TCO(x)        __emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
>> +#define TSB_CSYNC            __emit_inst(0xd503225f)
>>     #define set_pstate_pan(x)        asm volatile(SET_PSTATE_PAN(x))
>>   #define set_pstate_uao(x)        asm volatile(SET_PSTATE_UAO(x))
>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
>> index f154ae7..aa657ab 100644
>> --- a/drivers/hwtracing/coresight/Kconfig
>> +++ b/drivers/hwtracing/coresight/Kconfig
>> @@ -164,6 +164,17 @@ config CORESIGHT_CTI
>>         To compile this driver as a module, choose M here: the
>>         module will be called coresight-cti.
>>   +config CORESIGHT_TRBE
>> +    bool "Trace Buffer Extension (TRBE) driver"
>> +    depends on ARM64
>> +    help
>> +      This driver provides support for percpu Trace Buffer Extension (TRBE).
>> +      TRBE always needs to be used along with it's corresponding percpu ETE
>> +      component. ETE generates trace data which is then captured with TRBE.
>> +      Unlike traditional sink devices, TRBE is a CPU feature accessible via
>> +      system registers. But it's explicit dependency with trace unit (ETE)
>> +      requires it to be plugged in as a coresight sink device.
>> +
>>   config CORESIGHT_CTI_INTEGRATION_REGS
>>       bool "Access CTI CoreSight Integration Registers"
>>       depends on CORESIGHT_CTI
>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
>> index f20e357..d608165 100644
>> --- a/drivers/hwtracing/coresight/Makefile
>> +++ b/drivers/hwtracing/coresight/Makefile
>> @@ -21,5 +21,6 @@ obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
>>   obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
>>   obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
>>   obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
>> +obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
>>   coresight-cti-y := coresight-cti-core.o    coresight-cti-platform.o \
>>              coresight-cti-sysfs.o
>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
>> new file mode 100644
>> index 0000000..1464d8b
>> --- /dev/null
>> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
>> @@ -0,0 +1,1023 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * This driver enables Trace Buffer Extension (TRBE) as a per-cpu coresight
>> + * sink device could then pair with an appropriate per-cpu coresight source
>> + * device (ETE) thus generating required trace data. Trace can be enabled
>> + * via the perf framework.
>> + *
>> + * Copyright (C) 2020 ARM Ltd.
>> + *
>> + * Author: Anshuman Khandual <anshuman.khandual@arm.com>
>> + */
>> +#define DRVNAME "arm_trbe"
>> +
>> +#define pr_fmt(fmt) DRVNAME ": " fmt
>> +
>> +#include "coresight-trbe.h"
>> +
>> +#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
>> +
>> +/*
>> + * A padding packet that will help the user space tools
>> + * in skipping relevant sections in the captured trace
>> + * data which could not be decoded. TRBE doesn't support
>> + * formatting the trace data, unlike the legacy CoreSight
>> + * sinks and thus we use ETE trace packets to pad the
>> + * sections of the buffer.
>> + */
>> +#define ETE_IGNORE_PACKET         0x70
>> +
>> +/*
>> + * Minimum amount of meaningful trace will contain:
>> + * A-Sync, Trace Info, Trace On, Address, Atom.
>> + * This is about 44bytes of ETE trace. To be on
>> + * the safer side, we assume 64bytes is the minimum
>> + * space required for a meaningful session, before
>> + * we hit a "WRAP" event.
>> + */
>> +#define TRBE_TRACE_MIN_BUF_SIZE        64
>> +
>> +enum trbe_fault_action {
>> +    TRBE_FAULT_ACT_WRAP,
>> +    TRBE_FAULT_ACT_SPURIOUS,
>> +    TRBE_FAULT_ACT_FATAL,
>> +};
>> +
>> +struct trbe_buf {
>> +    unsigned long trbe_base;
>> +    unsigned long trbe_limit;
>> +    unsigned long trbe_write;
>> +    int nr_pages;
>> +    void **pages;
>> +    bool snapshot;
>> +    struct trbe_cpudata *cpudata;
>> +};
>> +
>> +struct trbe_cpudata {
>> +    bool trbe_dbm;
>> +    u64 trbe_align;
>> +    int cpu;
>> +    enum cs_mode mode;
>> +    struct trbe_buf *buf;
>> +    struct trbe_drvdata *drvdata;
>> +};
>> +
>> +struct trbe_drvdata {
>> +    struct trbe_cpudata __percpu *cpudata;
>> +    struct perf_output_handle __percpu **handle;
>> +    struct hlist_node hotplug_node;
>> +    int irq;
>> +    cpumask_t supported_cpus;
>> +    enum cpuhp_state trbe_online;
>> +    struct platform_device *pdev;
>> +};
>> +
>> +static int trbe_alloc_node(struct perf_event *event)
>> +{
>> +    if (event->cpu == -1)
>> +        return NUMA_NO_NODE;
>> +    return cpu_to_node(event->cpu);
>> +}
>> +
>> +static void trbe_drain_buffer(void)
>> +{
>> +    asm(TSB_CSYNC);
>> +    dsb(nsh);
>> +}
>> +
>> +static void trbe_drain_and_disable_local(void)
>> +{
>> +    trbe_drain_buffer();
>> +    write_sysreg_s(0, SYS_TRBLIMITR_EL1);
>> +    isb();
>> +}
>> +
>> +static void trbe_reset_local(void)
>> +{
>> +    trbe_drain_and_disable_local();
>> +    write_sysreg_s(0, SYS_TRBPTR_EL1);
>> +    write_sysreg_s(0, SYS_TRBBASER_EL1);
>> +    write_sysreg_s(0, SYS_TRBSR_EL1);
>> +}
>> +
>> +static void trbe_stop_and_truncate_event(struct perf_output_handle *handle)
>> +{
>> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +
>> +    /*
>> +     * We cannot proceed with the buffer collection and we
>> +     * do not have any data for the current session. The
>> +     * etm_perf driver expects to close out the aux_buffer
>> +     * at event_stop(). So disable the TRBE here and leave
>> +     * the update_buffer() to return a 0 size.
>> +     */
>> +    trbe_drain_and_disable_local();
>> +    perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
>> +    *this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
>> +}
>> +
>> +/*
>> + * TRBE Buffer Management
>> + *
>> + * The TRBE buffer spans from the base pointer till the limit pointer. When enabled,
>> + * it starts writing trace data from the write pointer onward till the limit pointer.
>> + * When the write pointer reaches the address just before the limit pointer, it gets
>> + * wrapped around again to the base pointer. This is called a TRBE wrap event, which
>> + * generates a maintenance interrupt when operated in WRAP or FILL mode. This driver
>> + * uses FILL mode, where the TRBE stops the trace collection at wrap event. The IRQ
>> + * handler updates the AUX buffer and re-enables the TRBE with updated WRITE and
>> + * LIMIT pointers.
>> + *
>> + *    Wrap around with an IRQ
>> + *    ------ < ------ < ------- < ----- < -----
>> + *    |                    |
>> + *    ------ > ------ > ------- > ----- > -----
>> + *
>> + *    +---------------+-----------------------+
>> + *    |        |            |
>> + *    +---------------+-----------------------+
>> + *    Base Pointer    Write Pointer        Limit Pointer
>> + *
>> + * The base and limit pointers always needs to be PAGE_SIZE aligned. But the write
>> + * pointer can be aligned to the implementation defined TRBE trace buffer alignment
>> + * as captured in trbe_cpudata->trbe_align.
>> + *
>> + *
>> + *        head        tail        wakeup
>> + *    +---------------------------------------+----- ~ ~ ------
>> + *    |$$$$$$$|################|$$$$$$$$$$$$$$|        |
>> + *    +---------------------------------------+----- ~ ~ ------
>> + *    Base Pointer    Write Pointer        Limit Pointer
>> + *
>> + * The perf_output_handle indices (head, tail, wakeup) are monotonically increasing
>> + * values which tracks all the driver writes and user reads from the perf auxiliary
>> + * buffer. Generally [head..tail] is the area where the driver can write into unless
>> + * the wakeup is behind the tail. Enabled TRBE buffer span needs to be adjusted and
>> + * configured depending on the perf_output_handle indices, so that the driver does
>> + * not override into areas in the perf auxiliary buffer which is being or yet to be
>> + * consumed from the user space. The enabled TRBE buffer area is a moving subset of
>> + * the allocated perf auxiliary buffer.
>> + */
>> +static void trbe_pad_buf(struct perf_output_handle *handle, int len)
>> +{
>> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +    u64 head = PERF_IDX2OFF(handle->head, buf);
>> +
>> +    memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
>> +    if (!buf->snapshot)
>> +        perf_aux_output_skip(handle, len);
>> +}
>> +
>> +static unsigned long trbe_snapshot_offset(struct perf_output_handle *handle)
>> +{
>> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +
>> +    /*
>> +     * The ETE trace has alignment synchronization packets allowing
>> +     * the decoder to reset in case of an overflow or corruption.
>> +     * So we can use the entire buffer for the snapshot mode.
>> +     */
>> +    return buf->nr_pages * PAGE_SIZE;
>> +}
>> +
>> +/*
>> + * TRBE Limit Calculation
>> + *
>> + * The following markers are used to illustrate various TRBE buffer situations.
>> + *
>> + * $$$$ - Data area, unconsumed captured trace data, not to be overridden
>> + * #### - Free area, enabled, trace will be written
>> + * %%%% - Free area, disabled, trace will not be written
>> + * ==== - Free area, padded with ETE_IGNORE_PACKET, trace will be skipped
>> + */
>> +static unsigned long __trbe_normal_offset(struct perf_output_handle *handle)
>> +{
>> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +    struct trbe_cpudata *cpudata = buf->cpudata;
>> +    const u64 bufsize = buf->nr_pages * PAGE_SIZE;
>> +    u64 limit = bufsize;
>> +    u64 head, tail, wakeup;
>> +
>> +    head = PERF_IDX2OFF(handle->head, buf);
>> +
>> +    /*
>> +     *        head
>> +     *    ------->|
>> +     *    |
>> +     *    head    TRBE align    tail
>> +     * +----|-------|---------------|-------+
>> +     * |$$$$|=======|###############|$$$$$$$|
>> +     * +----|-------|---------------|-------+
>> +     * trbe_base                trbe_base + nr_pages
>> +     *
>> +     * Perf aux buffer output head position can be misaligned depending on
>> +     * various factors including user space reads. In case misaligned, head
>> +     * needs to be aligned before TRBE can be configured. Pad the alignment
>> +     * gap with ETE_IGNORE_PACKET bytes that will be ignored by user tools
>> +     * and skip this section thus advancing the head.
>> +     */
>> +    if (!IS_ALIGNED(head, cpudata->trbe_align)) {
>> +        unsigned long delta = roundup(head, cpudata->trbe_align) - head;
>> +
>> +        delta = min(delta, handle->size);
>> +        trbe_pad_buf(handle, delta);
>> +        head = PERF_IDX2OFF(handle->head, buf);
>> +    }
>> +
>> +    /*
>> +     *    head = tail (size = 0)
>> +     * +----|-------------------------------+
>> +     * |$$$$|$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$    |
>> +     * +----|-------------------------------+
>> +     * trbe_base                trbe_base + nr_pages
>> +     *
>> +     * Perf aux buffer does not have any space for the driver to write into.
>> +     * Just communicate trace truncation event to the user space by marking
>> +     * it with PERF_AUX_FLAG_TRUNCATED.
>> +     */
>> +    if (!handle->size) {
>> +        perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
>> +        return 0;
>> +    }
>> +
>> +    /* Compute the tail and wakeup indices now that we've aligned head */
>> +    tail = PERF_IDX2OFF(handle->head + handle->size, buf);
>> +    wakeup = PERF_IDX2OFF(handle->wakeup, buf);
>> +
>> +    /*
>> +     * Lets calculate the buffer area which TRBE could write into. There
>> +     * are three possible scenarios here. Limit needs to be aligned with
>> +     * PAGE_SIZE per the TRBE requirement. Always avoid clobbering the
>> +     * unconsumed data.
>> +     *
>> +     * 1) head < tail
>> +     *
>> +     *    head            tail
>> +     * +----|-----------------------|-------+
>> +     * |$$$$|#######################|$$$$$$$|
>> +     * +----|-----------------------|-------+
>> +     * trbe_base            limit    trbe_base + nr_pages
>> +     *
>> +     * TRBE could write into [head..tail] area. Unless the tail is right at
>> +     * the end of the buffer, neither an wrap around nor an IRQ is expected
>> +     * while being enabled.
>> +     *
>> +     * 2) head == tail
>> +     *
>> +     *    head = tail (size > 0)
>> +     * +----|-------------------------------+
>> +     * |%%%%|###############################|
>> +     * +----|-------------------------------+
>> +     * trbe_base                limit = trbe_base + nr_pages
>> +     *
>> +     * TRBE should just write into [head..base + nr_pages] area even though
>> +     * the entire buffer is empty. Reason being, when the trace reaches the
>> +     * end of the buffer, it will just wrap around with an IRQ giving an
>> +     * opportunity to reconfigure the buffer.
>> +     *
>> +     * 3) tail < head
>> +     *
>> +     *    tail            head
>> +     * +----|-----------------------|-------+
>> +     * |%%%%|$$$$$$$$$$$$$$$$$$$$$$$|#######|
>> +     * +----|-----------------------|-------+
>> +     * trbe_base                limit = trbe_base + nr_pages
>> +     *
>> +     * TRBE should just write into [head..base + nr_pages] area even though
>> +     * the [trbe_base..tail] is also empty. Reason being, when the trace
>> +     * reaches the end of the buffer, it will just wrap around with an IRQ
>> +     * giving an opportunity to reconfigure the buffer.
>> +     */
>> +    if (head < tail)
>> +        limit = round_down(tail, PAGE_SIZE);
>> +
>> +    /*
>> +     * Wakeup may be arbitrarily far into the future. If it's not in the
>> +     * current generation, either we'll wrap before hitting it, or it's
>> +     * in the past and has been handled already.
>> +     *
>> +     * If there's a wakeup before we wrap, arrange to be woken up by the
>> +     * page boundary following it. Keep the tail boundary if that's lower.
>> +     *
>> +     *    head        wakeup    tail
>> +     * +----|---------------|-------|-------+
>> +     * |$$$$|###############|%%%%%%%|$$$$$$$|
>> +     * +----|---------------|-------|-------+
>> +     * trbe_base        limit        trbe_base + nr_pages
>> +     */
>> +    if (handle->wakeup < (handle->head + handle->size) && head <= wakeup)
>> +        limit = min(limit, round_up(wakeup, PAGE_SIZE));
>> +
>> +    /*
>> +     * There are two situation when this can happen i.e limit is before
>> +     * the head and hence TRBE cannot be configured.
>> +     *
>> +     * 1) head < tail (aligned down with PAGE_SIZE) and also they are both
>> +     * within the same PAGE size range.
>> +     *
>> +     *            PAGE_SIZE
>> +     *        |----------------------|
>> +     *
>> +     *        limit    head    tail
>> +     * +------------|------|--------|-------+
>> +     * |$$$$$$$$$$$$$$$$$$$|========|$$$$$$$|
>> +     * +------------|------|--------|-------+
>> +     * trbe_base                trbe_base + nr_pages
>> +     *
>> +     * 2) head < wakeup (aligned up with PAGE_SIZE) < tail and also both
>> +     * head and wakeup are within same PAGE size range.
>> +     *
>> +     *        PAGE_SIZE
>> +     *    |----------------------|
>> +     *
>> +     *    limit    head    wakeup  tail
>> +     * +----|------|-------|--------|-------+
>> +     * |$$$$$$$$$$$|=======|========|$$$$$$$|
>> +     * +----|------|-------|--------|-------+
>> +     * trbe_base                trbe_base + nr_pages
>> +     */
>> +    if (limit > head)
>> +        return limit;
>> +
>> +    trbe_pad_buf(handle, handle->size);
>> +    perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
>> +    return 0;
>> +}
>> +
>> +static unsigned long trbe_normal_offset(struct perf_output_handle *handle)
>> +{
>> +    struct trbe_buf *buf = perf_get_aux(handle);
>> +    u64 limit = __trbe_normal_offset(handle);
>> +    u64 head = PERF_IDX2OFF(handle->head, buf);
>> +
>> +    /*
>> +     * If the head is too close to the limit and we don't
>> +     * have space for a meaningful run, we rather pad it
>> +     * and start fresh.
>> +     */
>> +    if (limit && (limit - head < TRBE_TRACE_MIN_BUF_SIZE)) {
>> +        trbe_pad_buf(handle, limit - head);
>> +        limit = __trbe_normal_offset(handle);
>> +    }
>> +    return limit;
>> +}
>> +
>> +static unsigned long compute_trbe_buffer_limit(struct perf_output_handle *handle)
>> +{
>> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +    unsigned long offset;
>> +
>> +    if (buf->snapshot)
>> +        offset = trbe_snapshot_offset(handle);
>> +    else
>> +        offset = trbe_normal_offset(handle);
>> +    return buf->trbe_base + offset;
>> +}
>> +
>> +static void clr_trbe_status(void)
>> +{
>> +    u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
>> +
>> +    WARN_ON(is_trbe_enabled());
>> +    trbsr &= ~TRBSR_IRQ;
>> +    trbsr &= ~TRBSR_TRG;
>> +    trbsr &= ~TRBSR_WRAP;
>> +    trbsr &= ~(TRBSR_EC_MASK << TRBSR_EC_SHIFT);
>> +    trbsr &= ~(TRBSR_BSC_MASK << TRBSR_BSC_SHIFT);
>> +    trbsr &= ~TRBSR_STOP;
>> +    write_sysreg_s(trbsr, SYS_TRBSR_EL1);
>> +}
>> +
>> +static void set_trbe_limit_pointer_enabled(unsigned long addr)
>> +{
>> +    u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
>> +
>> +    WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
>> +    WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
>> +
>> +    trblimitr &= ~TRBLIMITR_NVM;
>> +    trblimitr &= ~(TRBLIMITR_FILL_MODE_MASK << TRBLIMITR_FILL_MODE_SHIFT);
>> +    trblimitr &= ~(TRBLIMITR_TRIG_MODE_MASK << TRBLIMITR_TRIG_MODE_SHIFT);
>> +    trblimitr &= ~(TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT);
>> +
>> +    /*
>> +     * Fill trace buffer mode is used here while configuring the
>> +     * TRBE for trace capture. In this particular mode, the trace
>> +     * collection is stopped and a maintenance interrupt is raised
>> +     * when the current write pointer wraps. This pause in trace
>> +     * collection gives the software an opportunity to capture the
>> +     * trace data in the interrupt handler, before reconfiguring
>> +     * the TRBE.
>> +     */
>> +    trblimitr |= (TRBE_FILL_MODE_FILL & TRBLIMITR_FILL_MODE_MASK) << TRBLIMITR_FILL_MODE_SHIFT;
>> +
>> +    /*
>> +     * Trigger mode is not used here while configuring the TRBE for
>> +     * the trace capture. Hence just keep this in the ignore mode.
>> +     */
>> +    trblimitr |= (TRBE_TRIG_MODE_IGNORE & TRBLIMITR_TRIG_MODE_MASK) << TRBLIMITR_TRIG_MODE_SHIFT;
>> +    trblimitr |= (addr & PAGE_MASK);
>> +
>> +    trblimitr |= TRBLIMITR_ENABLE;
>> +    write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);

> Personally, I prefer the isb() here rather than at the caller site, to make sure
> it is all contained here and more importantly we don't execute any other instruction
> before the "isb()" as the tracing may be enabled for the kernel.

Sure, will move the isb() here along with its comment.

> 
>> +}
>> +
>> +static void trbe_enable_hw(struct trbe_buf *buf)
>> +{
>> +    WARN_ON(buf->trbe_write < buf->trbe_base); > +    WARN_ON(buf->trbe_write >= buf->trbe_limit);
>> +    set_trbe_disabled();
>> +    isb();
>> +    clr_trbe_status();
>> +    set_trbe_base_pointer(buf->trbe_base);
>> +    set_trbe_write_pointer(buf->trbe_write);
>> +
>> +    /*
>> +     * Synchronize all the register updates
>> +     * till now before enabling the TRBE.
>> +     */
>> +    isb();
>> +    set_trbe_limit_pointer_enabled(buf->trbe_limit);
>> +
>> +    /* Synchronize the TRBE enable event */
>> +    isb();
>> +}
>> +
>> +static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
>> +                   struct perf_event *event, void **pages,
>> +                   int nr_pages, bool snapshot)
>> +{
>> +    struct trbe_buf *buf;
>> +    struct page **pglist;
>> +    int i;
>> +
>> +    /*
>> +     * TRBE LIMIT and TRBE WRITE pointers must be page aligned. But with
>> +     * just a single page, there is not much room left while writing into
>> +     * a partially filled TRBE buffer. Hence restrict the minimum buffer
>> +     * size as two pages.
>> +     */
>> +    if (nr_pages < 2)
>> +        return NULL;
>> +
>> +    buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
>> +    if (IS_ERR(buf))
>> +        return ERR_PTR(-ENOMEM);
>> +
>> +    pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
>> +    if (IS_ERR(pglist)) {
>> +        kfree(buf);
>> +        return ERR_PTR(-ENOMEM);
>> +    }
>> +
>> +    for (i = 0; i < nr_pages; i++)
>> +        pglist[i] = virt_to_page(pages[i]);
>> +
>> +    buf->trbe_base = (unsigned long) vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
> 
> minor nit: space after casting.

Will drop the space.

> 
>> +    if (IS_ERR((void *)buf->trbe_base)) {
>> +        kfree(pglist);
>> +        kfree(buf);
>> +        return ERR_PTR(buf->trbe_base);
>> +    }
>> +    buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
>> +    buf->trbe_write = buf->trbe_base;
>> +    buf->snapshot = snapshot;
>> +    buf->nr_pages = nr_pages;
>> +    buf->pages = pages;
>> +    kfree(pglist);
>> +    return buf;
>> +}
>> +
>> +void arm_trbe_free_buffer(void *config)
>> +{
>> +    struct trbe_buf *buf = config;
>> +
>> +    vunmap((void *)buf->trbe_base);
>> +    kfree(buf);
>> +}
>> +
>> +static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
>> +                        struct perf_output_handle *handle,
>> +                        void *config)
>> +{
>> +    struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> +    struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
>> +    struct trbe_buf *buf = config;
>> +    unsigned long size, offset;
>> +
>> +    WARN_ON(buf->cpudata != cpudata);
>> +    WARN_ON(cpudata->cpu != smp_processor_id());
>> +    WARN_ON(cpudata->drvdata != drvdata);
>> +    if (cpudata->mode != CS_MODE_PERF)
>> +        return -EINVAL;
> 
> Please return 0 here. As we are expected to pass an "unsigned" size.

Sure, will do.

> 
>> +
>> +    /*
>> +     * If the TRBE was disabled due to lack of space in the AUX buffer or a
>> +     * spurious fault, the driver leaves it disabled, truncating the buffer.
>> +     * Since the etm_perf driver expects to close out the AUX buffer, the
>> +     * driver skips it. Thus, just pass in 0 size here to indicate that the
>> +     * buffer was truncated.
>> +     */
>> +    if (!is_trbe_enabled())
>> +        return 0;
>> +    /*
>> +     * perf handle structure needs to be shared with the TRBE IRQ handler for
>> +     * capturing trace data and restarting the handle. There is a probability
>> +     * of an undefined reference based crash when etm event is being stopped
>> +     * while a TRBE IRQ also getting processed. This happens due the release
>> +     * of perf handle via perf_aux_output_end() in etm_event_stop(). Stopping
>> +     * the TRBE here will ensure that no IRQ could be generated when the perf
>> +     * handle gets freed in etm_event_stop().
>> +     */
>> +    trbe_drain_and_disable_local();
>> +    offset = get_trbe_write_pointer() - get_trbe_base_pointer();
>> +    size = offset - PERF_IDX2OFF(handle->head, buf);
> 
> It may be a good idea to verify that the size computation here doesn't overflow.
> e.g broken interrupt could potentially leave us with "write == base". I understand
> this is a hardware issue, but the software can be resilient to not send bogus
> results.

Okay, will do the necessary.

> 
>> +    if (buf->snapshot)
>> +        handle->head += size;
>> +    return size;
>> +}
>> +
>> +static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)
>> +{
>> +    struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> +    struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
>> +    struct perf_output_handle *handle = data;
>> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +
>> +    WARN_ON(cpudata->cpu != smp_processor_id());
>> +    WARN_ON(cpudata->drvdata != drvdata);
>> +    if (mode != CS_MODE_PERF)
>> +        return -EINVAL;
>> +
>> +    *this_cpu_ptr(drvdata->handle) = handle;
>> +    cpudata->buf = buf;
>> +    cpudata->mode = mode;
>> +    buf->cpudata = cpudata;
>> +    buf->trbe_limit = compute_trbe_buffer_limit(handle);
>> +    buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
>> +    if (buf->trbe_limit == buf->trbe_base) {
>> +        trbe_stop_and_truncate_event(handle);
>> +        return 0;
>> +    }
>> +    trbe_enable_hw(buf);
>> +    return 0;
>> +}
>> +
>> +static int arm_trbe_disable(struct coresight_device *csdev)
>> +{
>> +    struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> +    struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
>> +    struct trbe_buf *buf = cpudata->buf;
>> +
>> +    WARN_ON(buf->cpudata != cpudata);
>> +    WARN_ON(cpudata->cpu != smp_processor_id());
>> +    WARN_ON(cpudata->drvdata != drvdata);
>> +    if (cpudata->mode != CS_MODE_PERF)
>> +        return -EINVAL;
>> +
>> +    trbe_drain_and_disable_local();
>> +    buf->cpudata = NULL;
>> +    cpudata->buf = NULL;
>> +    cpudata->mode = CS_MODE_DISABLED;
>> +    return 0;
>> +}
>> +
>> +static void trbe_handle_spurious(struct perf_output_handle *handle)
>> +{
>> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +
>> +    buf->trbe_limit = compute_trbe_buffer_limit(handle);
>> +    buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
>> +    if (buf->trbe_limit == buf->trbe_base) {
>> +        trbe_drain_and_disable_local();
>> +        return;
>> +    }
>> +    trbe_enable_hw(buf);
>> +}
>> +
>> +static void trbe_handle_overflow(struct perf_output_handle *handle)
>> +{
>> +    struct perf_event *event = handle->event;
>> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +    unsigned long offset, size;
>> +    struct etm_event_data *event_data;
>> +
>> +    offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
>> +    size = offset - PERF_IDX2OFF(handle->head, buf);
>> +    if (buf->snapshot)
>> +        handle->head = offset;
>> +    perf_aux_output_end(handle, size);
>> +
>> +    event_data = perf_aux_output_begin(handle, event);
>> +    if (!event_data) {
> 
> We may add a comment here to explain how this would be handled ? e.g,
> 
>         /*
>          * We are unable to restart the trace collection,
>          * thus leave the TRBE disabled. The etm-perf driver
>          * is able to detect this with a disconnnected handle
>          * (handle->event = NULL).
>          */

Sure, will add the above.

> 
>> +        trbe_drain_and_disable_local();
>> +        *this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
>> +        return;
>> +    }
>> +    buf->trbe_limit = compute_trbe_buffer_limit(handle);
>> +    buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
>> +    if (buf->trbe_limit == buf->trbe_base) {
>> +        trbe_stop_and_truncate_event(handle);
>> +        return;
>> +    }
>> +    *this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;
>> +    trbe_enable_hw(buf);
>> +}
>> +
>> +static bool is_perf_trbe(struct perf_output_handle *handle)
>> +{
>> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +    struct trbe_cpudata *cpudata = buf->cpudata;
>> +    struct trbe_drvdata *drvdata = cpudata->drvdata;
>> +    int cpu = smp_processor_id();
>> +
>> +    WARN_ON(buf->trbe_base != get_trbe_base_pointer());
>> +    WARN_ON(buf->trbe_limit != get_trbe_limit_pointer());
>> +
>> +    if (cpudata->mode != CS_MODE_PERF)
>> +        return false;
>> +
>> +    if (cpudata->cpu != cpu)
>> +        return false;
>> +
>> +    if (!cpumask_test_cpu(cpu, &drvdata->supported_cpus))
>> +        return false;
>> +
>> +    return true;
>> +}
>> +
>> +static enum trbe_fault_action trbe_get_fault_act(struct perf_output_handle *handle)
>> +{
>> +    u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
>> +    int ec = get_trbe_ec(trbsr);
>> +    int bsc = get_trbe_bsc(trbsr);
>> +
>> +    WARN_ON(is_trbe_running(trbsr));
>> +    if (is_trbe_trg(trbsr) || is_trbe_abort(trbsr))
>> +        return TRBE_FAULT_ACT_FATAL;
>> +
>> +    if ((ec == TRBE_EC_STAGE1_ABORT) || (ec == TRBE_EC_STAGE2_ABORT))
>> +        return TRBE_FAULT_ACT_FATAL;
>> +
>> +    if (is_trbe_wrap(trbsr) && (ec == TRBE_EC_OTHERS) && (bsc == TRBE_BSC_FILLED)) {
>> +        if (get_trbe_write_pointer() == get_trbe_base_pointer())
>> +            return TRBE_FAULT_ACT_WRAP;
>> +    }
>> +    return TRBE_FAULT_ACT_SPURIOUS;
>> +}
>> +
>> +static irqreturn_t arm_trbe_irq_handler(int irq, void *dev)
>> +{
>> +    struct perf_output_handle **handle_ptr = dev;
>> +    struct perf_output_handle *handle = *handle_ptr;
>> +    enum trbe_fault_action act;
>> +
>> +    WARN_ON(!is_trbe_irq(read_sysreg_s(SYS_TRBSR_EL1)));
>> +    clr_trbe_irq();
>> +
>> +    /*
>> +     * Ensure the trace is visible to the CPUs and
>> +     * any external aborts have been resolved.
>> +     */
>> +    trbe_drain_buffer();
>> +    isb();
>> +
>> +    if (!perf_get_aux(handle))
> 
> We may want to ensure that handle is not NULL, which can only happen if the
> hardware is not following the software.
> 
>     if (WARN_ON_ONCE(!handle) || !perf_get_aux(handle))

Okay, will do the change.

> 
>> +        return IRQ_NONE;
>> +
>> +    if (!is_perf_trbe(handle))
>> +        return IRQ_NONE;
>> +
>> +    irq_work_run();
>> +
>> +    act = trbe_get_fault_act(handle);
>> +    switch (act) {
>> +    case TRBE_FAULT_ACT_WRAP:
>> +        trbe_handle_overflow(handle);
>> +        break;
>> +    case TRBE_FAULT_ACT_SPURIOUS:
>> +        trbe_handle_spurious(handle);
>> +        break;
>> +    case TRBE_FAULT_ACT_FATAL:
>> +        trbe_stop_and_truncate_event(handle);
>> +        break;
>> +    }
>> +    return IRQ_HANDLED;
>> +}
>> +
>> +static const struct coresight_ops_sink arm_trbe_sink_ops = {
>> +    .enable        = arm_trbe_enable,
>> +    .disable    = arm_trbe_disable,
>> +    .alloc_buffer    = arm_trbe_alloc_buffer,
>> +    .free_buffer    = arm_trbe_free_buffer,
>> +    .update_buffer    = arm_trbe_update_buffer,
>> +};
>> +
>> +static const struct coresight_ops arm_trbe_cs_ops = {
>> +    .sink_ops    = &arm_trbe_sink_ops,
>> +};
>> +
>> +static ssize_t align_show(struct device *dev, struct device_attribute *attr, char *buf)
>> +{
>> +    struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
>> +
>> +    return sprintf(buf, "%llx\n", cpudata->trbe_align);
>> +}
>> +static DEVICE_ATTR_RO(align);
>> +
>> +static ssize_t dbm_show(struct device *dev, struct device_attribute *attr, char *buf)
>> +{
>> +    struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
>> +
>> +    return sprintf(buf, "%d\n", cpudata->trbe_dbm);
>> +}
>> +static DEVICE_ATTR_RO(dbm);
>> +
>> +static struct attribute *arm_trbe_attrs[] = {
>> +    &dev_attr_align.attr,
>> +    &dev_attr_dbm.attr,
>> +    NULL,
>> +};
>> +
>> +static const struct attribute_group arm_trbe_group = {
>> +    .attrs = arm_trbe_attrs,
>> +};
>> +
>> +static const struct attribute_group *arm_trbe_groups[] = {
>> +    &arm_trbe_group,
>> +    NULL,
>> +};
>> +
>> +static void arm_trbe_probe_coresight_cpu(void *info)
>> +{
>> +    struct trbe_drvdata *drvdata = info;
>> +    struct coresight_desc desc = { 0 };
>> +    int cpu = smp_processor_id();
>> +    struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
>> +    struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
>> +    u64 trbidr = read_sysreg_s(SYS_TRBIDR_EL1);
> 
> This must be done only after the "is_trbe_available()". Otherwise
> we get an UNDEFINED instruction abort.

Okay, will move read_sysreg_s() after is_trbe_programmable() instead.

> 
>> +    struct device *dev;
>> +
>> +    if (WARN_ON(!cpudata))
>> +        goto cpu_clear;
>> +
>> +    if (trbe_csdev)
>> +        return;
>> +
>> +    cpudata->cpu = smp_processor_id();
>> +    cpudata->drvdata = drvdata;
>> +    dev = &cpudata->drvdata->pdev->dev;
>> +
>> +    if (!is_trbe_available()) {
>> +        pr_err("TRBE is not implemented on cpu %d\n", cpudata->cpu);
>> +        goto cpu_clear;
>> +    }
>> +
>> +    if (!is_trbe_programmable(trbidr)) {
>> +        pr_err("TRBE is owned in higher exception level on cpu %d\n", cpudata->cpu);
>> +        goto cpu_clear;
>> +    }
>> +    desc.name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", DRVNAME, smp_processor_id());
>> +    if (IS_ERR(desc.name))
>> +        goto cpu_clear;
>> +
>> +    desc.type = CORESIGHT_DEV_TYPE_SINK;
>> +    desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
>> +    desc.ops = &arm_trbe_cs_ops;
>> +    desc.pdata = dev_get_platdata(dev);
>> +    desc.groups = arm_trbe_groups;
>> +    desc.dev = dev;
>> +    trbe_csdev = coresight_register(&desc);
>> +    if (IS_ERR(trbe_csdev))
>> +        goto cpu_clear;
>> +
>> +    dev_set_drvdata(&trbe_csdev->dev, cpudata);
>> +    cpudata->trbe_dbm = get_trbe_flag_update(trbidr);
>> +    cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
>> +    if (cpudata->trbe_align > SZ_2K) {
>> +        pr_err("Unsupported alignment on cpu %d\n", cpudata->cpu);
>> +        goto cpu_clear;
> 
> Should we unregister the coresight device in this case ?  There is no point
> in having the device around if it is not supported.

Okay, will call coresight_unregister() in that case.

> 
>> +    }
>> +    per_cpu(csdev_sink, cpu) = trbe_csdev;
>> +    trbe_reset_local();
>> +    enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
>> +    return;
>> +cpu_clear:
>> +    cpumask_clear_cpu(cpudata->cpu, &cpudata->drvdata->supported_cpus);
>> +}
>> +
>> +static void arm_trbe_remove_coresight_cpu(void *info)
>> +{
>> +    int cpu = smp_processor_id();
>> +    struct trbe_drvdata *drvdata = info;
>> +    struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
>> +    struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
>> +
> 
> nit: Is it better to use this_cpu_ptr() every where above/below to make it explicit ?

csdev_sink is already a percpu pointer.

> 
>> +    if (trbe_csdev) {
>> +        coresight_unregister(trbe_csdev);
>> +        cpudata->drvdata = NULL;
>> +        per_cpu(csdev_sink, cpu) = NULL;
>> +    }
>> +    disable_percpu_irq(drvdata->irq);
>> +    trbe_reset_local();
>> +}
>> +
>> +static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata)
>> +{
>> +    drvdata->cpudata = alloc_percpu(typeof(*drvdata->cpudata));
>> +    if (IS_ERR(drvdata->cpudata))
>> +        return PTR_ERR(drvdata->cpudata);
>> +
>> +    arm_trbe_probe_coresight_cpu(drvdata);
>> +    smp_call_function_many(&drvdata->supported_cpus, arm_trbe_probe_coresight_cpu, drvdata, 1);
>> +    return 0;
>> +}
>> +
>> +static int arm_trbe_remove_coresight(struct trbe_drvdata *drvdata)
>> +{
>> +    arm_trbe_remove_coresight_cpu(drvdata);
>> +    smp_call_function_many(&drvdata->supported_cpus, arm_trbe_remove_coresight_cpu, drvdata, 1);
>> +    free_percpu(drvdata->cpudata);
>> +    return 0;
>> +}
>> +
>> +static int arm_trbe_cpu_startup(unsigned int cpu, struct hlist_node *node)
>> +{
>> +    struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
>> +
>> +    if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
> 
> nit: Add a comment ?
> 
>         /*
>          * If this CPU was not probed for TRBE, initialize
>          * it now.
>          */

Sure, will add the above.

> 
>> +        if (!per_cpu(csdev_sink, cpu)) {
>> +            arm_trbe_probe_coresight_cpu(drvdata);
>> +        } else {
>> +            trbe_reset_local();
>> +            enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
>> +        }
>> +    }
>> +    return 0;
>> +}
>> +
>> +static int arm_trbe_cpu_teardown(unsigned int cpu, struct hlist_node *node)
>> +{
>> +    struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
>> +
>> +    if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
>> +        disable_percpu_irq(drvdata->irq);
>> +        trbe_reset_local();
>> +    }
>> +    return 0;
>> +}
>> +
>> +static int arm_trbe_probe_cpuhp(struct trbe_drvdata *drvdata)
>> +{
>> +    enum cpuhp_state trbe_online;
>> +
>> +    trbe_online = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
>> +                    arm_trbe_cpu_startup, arm_trbe_cpu_teardown);
>> +    if (trbe_online < 0)
>> +        return -EINVAL;
>> +
>> +    if (cpuhp_state_add_instance(trbe_online, &drvdata->hotplug_node))
>> +        return -EINVAL;
>> +
>> +    drvdata->trbe_online = trbe_online;
>> +    return 0;
>> +}
>> +
>> +static void arm_trbe_remove_cpuhp(struct trbe_drvdata *drvdata)
>> +{
>> +    cpuhp_remove_multi_state(drvdata->trbe_online);
>> +}
>> +
>> +static int arm_trbe_probe_irq(struct platform_device *pdev,
>> +                  struct trbe_drvdata *drvdata)
>> +{
>> +    drvdata->irq = platform_get_irq(pdev, 0);
>> +    if (!drvdata->irq) {
>> +        pr_err("IRQ not found for the platform device\n");
>> +        return -ENXIO;
>> +    }
>> +
>> +    if (!irq_is_percpu(drvdata->irq)) {
>> +        pr_err("IRQ is not a PPI\n");
>> +        return -EINVAL;
>> +    }
>> +
>> +    if (irq_get_percpu_devid_partition(drvdata->irq, &drvdata->supported_cpus))
>> +        return -EINVAL;
>> +
>> +    drvdata->handle = alloc_percpu(typeof(*drvdata->handle));
>> +    if (!drvdata->handle)
>> +        return -ENOMEM;
>> +
>> +    if (request_percpu_irq(drvdata->irq, arm_trbe_irq_handler, DRVNAME, drvdata->handle)) {
>> +        free_percpu(drvdata->handle);
>> +        return -EINVAL;
>> +    }
>> +    return 0;
>> +}
>> +
>> +static void arm_trbe_remove_irq(struct trbe_drvdata *drvdata)
>> +{
>> +    free_percpu_irq(drvdata->irq, drvdata->handle);
>> +    free_percpu(drvdata->handle);
>> +}
>> +
>> +static int arm_trbe_device_probe(struct platform_device *pdev)
>> +{
>> +    struct coresight_platform_data *pdata;
>> +    struct trbe_drvdata *drvdata;
>> +    struct device *dev = &pdev->dev;
>> +    int ret;
>> +
>> +    drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
>> +    if (IS_ERR(drvdata))
>> +        return -ENOMEM;
>> +
>> +    pdata = coresight_get_platform_data(dev);
> 
> Not sure if this is necessary. We don't have any CoreSight specific
> data in the bindings.

Without desc.pdata which is dev_get_platdata(dev), coresight_register()
just fails. Do you see any other alternative for desc.pdata instead ?

[    1.465221] pc : coresight_register+0x1f0/0x338
[    1.465383] lr : coresight_register+0x144/0x338
[    1.465483] sp : ffff80001003ba80
[    1.465583] x29: ffff80001003ba80 x28: ffff000800286c10 
[    1.465712] x27: 0000000000000002 x26: ffff00087f7d6e88 
[    1.465883] x25: 0000000000000020 x24: ffff000802168b80 
[    1.465983] x23: ffff800011bd99c0 x22: ffff800011e6f000 
[    1.466183] x21: 0000000000000000 x20: ffff80001003bb28 
[    1.466286] x19: ffff00080217b400 x18: ffffffffffffffff 
[    1.466483] x17: 00000000000000c0 x16: fffffc0020085e40 
[    1.466613] x15: ffff800011bd9948 x14: ffff000802131a1c 
[    1.466783] x13: ffff00080213127d x12: 0000000000000000 
[    1.466883] x11: 0101010101010101 x10: 7f7f7f7f7f7f7f7f 
[    1.467083] x9 : 686260717376672e x8 : 7f7f7f7f7f7f7f7f 
[    1.467206] x7 : 72716475687162ff x6 : 8000000000000000 
[    1.467383] x5 : ffff000800090000 x4 : ffff000800090000 
[    1.467514] x3 : 0000000000000000 x2 : 0000000000000000 
[    1.467596] x1 : 0000000000000001 x0 : 0000000000000000 
[    1.467783] Call trace:
[    1.467883]  coresight_register+0x1f0/0x338
[    1.468006]  arm_trbe_probe_coresight_cpu+0x144/0x238
[    1.468088]  arm_trbe_device_probe+0xd0/0x200
[    1.468283]  platform_probe+0x68/0xe0
[    1.468383]  really_probe+0x118/0x3e0
[    1.468508]  driver_probe_device+0x5c/0xc0
[    1.468583]  device_driver_attach+0x74/0x80
[    1.468683]  __driver_attach+0x8c/0xd8
[    1.468825]  bus_for_each_dev+0x7c/0xd8
[    1.468907]  driver_attach+0x24/0x30
[    1.469071]  bus_add_driver+0x154/0x200
[    1.469183]  driver_register+0x64/0x120
[    1.469290]  __platform_driver_register+0x28/0x38
[    1.469399]  arm_trbe_init+0x58/0x88
[    1.469562]  do_one_initcall+0x60/0x1d8
[    1.469644]  kernel_init_freeable+0x1f4/0x24c
[    1.469783]  kernel_init+0x14/0x118
[    1.469890]  ret_from_fork+0x10/0x30
[    1.469983] Code: 17ffff98 92800173 17ffffef f9400262 (b9400440) 
[    1.470183] ---[ end trace 20f096c5ea194114 ]---
[    1.470300] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00

> 
>> +    if (IS_ERR(pdata)) {
>> +        kfree(drvdata);
> 
> This is not required. The cleanup should automatically free this up.
> In fact this will be problematic and will cause double free.

Okay.

> 
>> +        return -ENOMEM;
>> +    }
>> +
>> +    dev_set_drvdata(dev, drvdata);
>> +    dev->platform_data = pdata;
>> +    drvdata->pdev = pdev;
>> +    ret = arm_trbe_probe_irq(pdev, drvdata);
>> +    if (ret)
>> +        goto irq_failed;
>> +
>> +    ret = arm_trbe_probe_coresight(drvdata);
>> +    if (ret)
>> +        goto probe_failed;
>> +
>> +    ret = arm_trbe_probe_cpuhp(drvdata);
>> +    if (ret)
>> +        goto cpuhp_failed;
>> +
>> +    return 0;
>> +cpuhp_failed:
>> +    arm_trbe_remove_coresight(drvdata);
>> +probe_failed:
>> +    arm_trbe_remove_irq(drvdata);
>> +irq_failed:
>> +    kfree(pdata);
>> +    kfree(drvdata);
> 
> None of these "kfree" is needed. It will be automatically freed
> when the probe fails.

Will drop these kfree().

> 
>> +    return ret;
>> +}
>> +
>> +static int arm_trbe_device_remove(struct platform_device *pdev)
>> +{
>> +    struct coresight_platform_data *pdata = dev_get_platdata(&pdev->dev);
>> +    struct trbe_drvdata *drvdata = platform_get_drvdata(pdev);
>> +
>> +    arm_trbe_remove_coresight(drvdata);
>> +    arm_trbe_remove_cpuhp(drvdata);
>> +    arm_trbe_remove_irq(drvdata);
> 
>> +    kfree(pdata);
>> +    kfree(drvdata);
> 
> Same as above.

Will drop these kfree().

> 
>> +    return 0;
>> +}
>> +
>> +static const struct of_device_id arm_trbe_of_match[] = {
>> +    { .compatible = "arm,trace-buffer-extension"},
>> +    {},
>> +};
>> +MODULE_DEVICE_TABLE(of, arm_trbe_of_match);
>> +
>> +static struct platform_driver arm_trbe_driver = {
>> +    .driver    = {
>> +        .name = DRVNAME,
>> +        .of_match_table = of_match_ptr(arm_trbe_of_match),
>> +        .suppress_bind_attrs = true,
>> +    },
>> +    .probe    = arm_trbe_device_probe,
>> +    .remove    = arm_trbe_device_remove,
>> +};
>> +
>> +static int __init arm_trbe_init(void)
>> +{
>> +    int ret;
>> +
>> +    if (arm64_kernel_unmapped_at_el0()) {
>> +        pr_err("TRBE wouldn't work if kernel gets unmapped at EL0\n");
>> +        return -EOPNOTSUPP;
>> +    }
>> +
>> +    ret = platform_driver_register(&arm_trbe_driver);
>> +    if (!ret)
>> +        return 0;
>> +
>> +    pr_err("Error registering %s platform driver\n", DRVNAME);
>> +    return ret;
>> +}
>> +
>> +static void __exit arm_trbe_exit(void)
>> +{
>> +    platform_driver_unregister(&arm_trbe_driver);
>> +}
>> +module_init(arm_trbe_init);
>> +module_exit(arm_trbe_exit);
>> +
>> +MODULE_AUTHOR("Anshuman Khandual <anshuman.khandual@arm.com>");
>> +MODULE_DESCRIPTION("Arm Trace Buffer Extension (TRBE) driver");
>> +MODULE_LICENSE("GPL v2");
>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h
>> new file mode 100644
>> index 0000000..43308bc
>> --- /dev/null
>> +++ b/drivers/hwtracing/coresight/coresight-trbe.h
>> @@ -0,0 +1,160 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * This contains all required hardware related helper functions for
>> + * Trace Buffer Extension (TRBE) driver in the coresight framework.
>> + *
>> + * Copyright (C) 2020 ARM Ltd.
>> + *
>> + * Author: Anshuman Khandual <anshuman.khandual@arm.com>
>> + */
>> +#include <linux/coresight.h>
>> +#include <linux/device.h>
>> +#include <linux/irq.h>
>> +#include <linux/kernel.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/smp.h>
>> +
>> +#include "coresight-etm-perf.h"
>> +
>> +DECLARE_PER_CPU(struct coresight_device *, csdev_sink);
> 
> This belongs to coresight-priv.h.

Okay, will move.

> 
>> +
>> +static inline bool is_trbe_available(void)
>> +{
>> +    u64 aa64dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
>> +    unsigned int trbe = cpuid_feature_extract_unsigned_field(aa64dfr0, ID_AA64DFR0_TRBE_SHIFT);
>> +
>> +    return trbe >= 0b0001;
>> +}
>> +
>> +static inline bool is_trbe_enabled(void)
>> +{
>> +    u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
>> +
>> +    return trblimitr & TRBLIMITR_ENABLE;
>> +}
>> +
>> +#define TRBE_EC_OTHERS        0
>> +#define TRBE_EC_STAGE1_ABORT    36
>> +#define TRBE_EC_STAGE2_ABORT    37
>> +
>> +static inline int get_trbe_ec(u64 trbsr)
>> +{
>> +    return (trbsr >> TRBSR_EC_SHIFT) & TRBSR_EC_MASK;
>> +}
>> +
>> +#define TRBE_BSC_NOT_STOPPED    0
>> +#define    TRBE_BSC_FILLED        1
> 
> nit: Use space instead of TAB here.

Sure, will change.

> 
>> +#define TRBE_BSC_TRIGGERED    2
>> +
>> +static inline int get_trbe_bsc(u64 trbsr)
>> +{
>> +    return (trbsr >> TRBSR_BSC_SHIFT) & TRBSR_BSC_MASK;
>> +}
>> +
>> +static inline void clr_trbe_irq(void)
>> +{
>> +    u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
>> +
>> +    trbsr &= ~TRBSR_IRQ;
>> +    write_sysreg_s(trbsr, SYS_TRBSR_EL1);
>> +}
>> +
>> +static inline bool is_trbe_irq(u64 trbsr)
>> +{
>> +    return trbsr & TRBSR_IRQ;
>> +}
>> +
>> +static inline bool is_trbe_trg(u64 trbsr)
>> +{
>> +    return trbsr & TRBSR_TRG;
>> +}
>> +
>> +static inline bool is_trbe_wrap(u64 trbsr)
>> +{
>> +    return trbsr & TRBSR_WRAP;
>> +}
>> +
>> +static inline bool is_trbe_abort(u64 trbsr)
>> +{
>> +    return trbsr & TRBSR_ABORT;
>> +}
>> +
>> +static inline bool is_trbe_running(u64 trbsr)
>> +{
>> +    return !(trbsr & TRBSR_STOP);
>> +}
>> +
>> +#define TRBE_TRIG_MODE_STOP        0
>> +#define TRBE_TRIG_MODE_IRQ        1
>> +#define TRBE_TRIG_MODE_IGNORE        3
>> +
>> +#define TRBE_FILL_MODE_FILL        0
>> +#define TRBE_FILL_MODE_WRAP        1
>> +#define TRBE_FILL_MODE_CIRCULAR_BUFFER    3
>> +
>> +static inline void set_trbe_disabled(void)
>> +{
>> +    u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
>> +
>> +    trblimitr &= ~TRBLIMITR_ENABLE;
>> +    write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
>> +}
>> +
>> +static inline bool get_trbe_flag_update(u64 trbidr)
>> +{
>> +    return trbidr & TRBIDR_FLAG;
>> +}
>> +
>> +static inline bool is_trbe_programmable(u64 trbidr)
>> +{
>> +    return !(trbidr & TRBIDR_PROG);
>> +}
>> +
>> +static inline int get_trbe_address_align(u64 trbidr)
>> +{
>> +    return (trbidr >> TRBIDR_ALIGN_SHIFT) & TRBIDR_ALIGN_MASK;
>> +}
>> +
>> +static inline unsigned long get_trbe_write_pointer(void)
>> +{
>> +    u64 trbptr = read_sysreg_s(SYS_TRBPTR_EL1);
>> +    unsigned long addr = (trbptr >> TRBPTR_PTR_SHIFT) & TRBPTR_PTR_MASK;
> 
> You don't need this shifting and masking. trbptr_el1 is a whole 64bit register

Okay, will also drop TRBPTR_PTR_SHIFT and TRBPTR_PTR_MASK from here.

> 
>> +
>> +    return addr;
>> +}
>> +
>> +static inline void set_trbe_write_pointer(unsigned long addr)
>> +{
>> +    WARN_ON(is_trbe_enabled());
>> +    addr = (addr >> TRBPTR_PTR_SHIFT) & TRBPTR_PTR_MASK;
> 
> Same as above.
> 
>> +    write_sysreg_s(addr, SYS_TRBPTR_EL1);
>> +}
>> +
>> +static inline unsigned long get_trbe_limit_pointer(void)
>> +{
>> +    u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
>> +    unsigned long limit = (trblimitr >> TRBLIMITR_LIMIT_SHIFT) & TRBLIMITR_LIMIT_MASK;
>> +    unsigned long addr = limit << TRBLIMITR_LIMIT_SHIFT;
>> +
>> +    WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
>> +    return addr;
>> +}
>> +
>> +static inline unsigned long get_trbe_base_pointer(void)
>> +{
>> +    u64 trbbaser = read_sysreg_s(SYS_TRBBASER_EL1);
> 
> 
>> +    unsigned long addr = (trbbaser >> TRBBASER_BASE_SHIFT) & TRBBASER_BASE_MASK;
>> +
>> +    addr = addr << TRBBASER_BASE_SHIFT;
> 
> nit: Could we instead do :
> 
>     addr = trbbaser & (TRBBASER_BASE_MASK << TRBBASER_BASE_SHIFT); ?

Okay, will change.

> 
>> +    WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
>> +    return addr;
>> +}
>> +
>> +static inline void set_trbe_base_pointer(unsigned long addr)
>> +{
>> +    WARN_ON(is_trbe_enabled());
>> +    WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
> 
> TRBBASER_BASE_SHIFT ?

Right, will replace.

- Anshuman

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks
  2021-02-01 23:17   ` Mathieu Poirier
@ 2021-02-02  9:42     ` Suzuki K Poulose
  2021-02-02 16:33       ` Mike Leach
  2021-02-02 16:37       ` Mathieu Poirier
  0 siblings, 2 replies; 90+ messages in thread
From: Suzuki K Poulose @ 2021-02-02  9:42 UTC (permalink / raw)
  To: Mathieu Poirier, Anshuman Khandual
  Cc: linux-arm-kernel, coresight, mike.leach, lcherian, linux-kernel

On 2/1/21 11:17 PM, Mathieu Poirier wrote:
> Hi Anshuman,
> 
> I have started reviewing this set.  As it is quite voluminous comments will
> come over serveral days.  I will let you know when I am done.
> 
> On Wed, Jan 27, 2021 at 02:25:25PM +0530, Anshuman Khandual wrote:
>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>
>> When there are multiple sinks on the system, in the absence
>> of a specified sink, it is quite possible that a default sink
>> for an ETM could be different from that of another ETM. However
>> we do not support having multiple sinks for an event yet. This
>> patch allows the event to use the default sinks on the ETMs
>> where they are scheduled as long as the sinks are of the same
>> type.
>>
>> e.g, if we have 1x1 topology with per-CPU ETRs, the event can
>> use the per-CPU ETR for the session. However, if the sinks
>> are of different type, e.g TMC-ETR on one and a custom sink
>> on another, the event will only trace on the first detected
>> sink.
>>
> 
> I found the above changelog very confusing - I read it several times and still
> couldn't get all of it.  In the end this patch prevents sinks of different types
> from being used for session, and this is what the text should reflect.

Sorry about that. Your inference is correct, but it is only a side effect
of the primary motive. How about the following :

"When a sink is not specified by the user, the etm perf driver
finds a suitable sink automatically based on the first ETM, where
this event could be scheduled. Then we allocate the sink buffer based
on the selected sink. This is fine for a CPU bound event as the "sink"
is always guaranteed to be reachable from the ETM (as this is the only
ETM where the event is going to be scheduled). However, if we have a task
bound event, the event could be scheduled on any of the ETMs on the
system. In this case, currently we automatically select a sink and exclude
any ETMs that are not reachable from the selected sink. This is
problematic for 1x1 configurations as we end up in tracing the event
only on the "first" ETM, as the default sink is local to the first
ETM and unreachable from the rest.
However, we could allow the other ETMs to trace if they all have a
sink that is compatible with the "selected" sink and can use the
sink buffer. This can be easily done by verifying that they are
all driven by the same driver and matches the same subtype."


>   
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Tested-by: Linu Cherian <lcherian@marvell.com>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>   drivers/hwtracing/coresight/coresight-etm-perf.c | 48 +++++++++++++++++++-----
>>   1 file changed, 38 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
>> index bdc34ca..eb9e7e9 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
>> @@ -204,6 +204,13 @@ static void etm_free_aux(void *data)
>>   	schedule_work(&event_data->work);
>>   }
>>   
>> +static bool sinks_match(struct coresight_device *a, struct coresight_device *b)
>> +{
>> +	if (!a || !b)
>> +		return false;
>> +	return (sink_ops(a) == sink_ops(b));
> 
> Yes

I think we can tighten this by verifying the dev->sub_type matches too.

> 
>> +}
>> +
>>   static void *etm_setup_aux(struct perf_event *event, void **pages,
>>   			   int nr_pages, bool overwrite)
>>   {
>> @@ -212,6 +219,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>>   	cpumask_t *mask;
>>   	struct coresight_device *sink = NULL;
> 
>          struct coresight_device *user_sink = NULL;
> 
>>   	struct etm_event_data *event_data = NULL;
>> +	bool sink_forced = false;
>>   
>>   	event_data = alloc_event_data(cpu);
>>   	if (!event_data)
>> @@ -222,6 +230,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>>   	if (event->attr.config2) {
>>   		id = (u32)event->attr.config2;
>>   		sink = coresight_get_sink_by_id(id);
> 
>                  user_sink = coresight_get_sink_by_id(id);
> 
>> +		sink_forced = true;
>>   	}
>>   
>>   	mask = &event_data->mask;
>> @@ -235,7 +244,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>>   	 */
>>   	for_each_cpu(cpu, mask) {
>>   		struct list_head *path;
>> -		struct coresight_device *csdev;
> 
>                  struct coresight_device *last_sink = NULL;
> 
>> +		struct coresight_device *csdev, *new_sink;
>>   
>>   		csdev = per_cpu(csdev_src, cpu);
>>   		/*
>> @@ -249,21 +258,35 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>>   		}
>>   
>>   		/*
>> -		 * No sink provided - look for a default sink for one of the
>> -		 * devices. At present we only support topology where all CPUs
>> -		 * use the same sink [N:1], so only need to find one sink. The
>> -		 * coresight_build_path later will remove any CPU that does not
>> -		 * attach to the sink, or if we have not found a sink.
>> +		 * No sink provided - look for a default sink for all the devices.
>> +		 * We only support multiple sinks, only if all the default sinks
>> +		 * are of the same type, so that the sink buffer can be shared
>> +		 * as the event moves around. We don't trace on a CPU if it can't
> 
> s/can't/can't./
> 
>> +		 *
> 
> Extra line
> 

OK

>>   		 */
>> -		if (!sink)
>> -			sink = coresight_find_default_sink(csdev);
>> +		if (!sink_forced) {
>> +			new_sink = coresight_find_default_sink(csdev);
>> +			if (!new_sink) {
>> +				cpumask_clear_cpu(cpu, mask);
>> +				continue;
>> +			}
>> +			/* Skip checks for the first sink */
>> +			if (!sink) {
>> +			       sink = new_sink;
>> +			} else if (!sinks_match(new_sink, sink)) {
>> +				cpumask_clear_cpu(cpu, mask);
>> +				continue;
>> +			}
>> +		} else {
>> +			new_sink = sink;
>> +		}
> 
>                  if (!user_sink) {
>                          /* find default sink for this CPU */
>                          sink = coresight_find_default_sink(csdev);
>                          if (!sink) {
>                                  cpumask_clear_cpu(cpu, mask);
>                                  continue;
>                          }
> 
>                          /* Chech new sink with last sink */
>                          if (last_sink && !sink_match(last_sink, sink)) {
>                                  cpumask_clear_cpu(cpu, mask);
>                                  continue;
>                          }
> 
>                          last_sink = sink;
>                  } else {
>                          sink = user_sink;
>                  }
> 

Agreed, it is much better readable.

Suzuki

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 02/14] coresight: Do not scan for graph if none is present
  2021-01-27  8:55 ` [PATCH V3 02/14] coresight: Do not scan for graph if none is present Anshuman Khandual
  2021-02-01 23:44   ` Mathieu Poirier
@ 2021-02-02 11:10   ` Mike Leach
  2021-02-02 14:36     ` Suzuki K Poulose
  1 sibling, 1 reply; 90+ messages in thread
From: Mike Leach @ 2021-02-02 11:10 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, Coresight ML, Mathieu Poirier,
	Suzuki K. Poulose, Linu Cherian, Linux Kernel Mailing List

Hi Ansuman,

On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
<anshuman.khandual@arm.com> wrote:
>
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>
> If a graph node is not found for a given node, of_get_next_endpoint()
> will emit the following error message :
>
>  OF: graph: no port node found in /<node_name>
>
> If the given component doesn't have any explicit connections (e.g,
> ETE) we could simply ignore the graph parsing.
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-platform.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c
> index 3629b78..c594f45 100644
> --- a/drivers/hwtracing/coresight/coresight-platform.c
> +++ b/drivers/hwtracing/coresight/coresight-platform.c
> @@ -90,6 +90,12 @@ static void of_coresight_get_ports_legacy(const struct device_node *node,
>         struct of_endpoint endpoint;
>         int in = 0, out = 0;
>
> +       /*
> +        * Avoid warnings in of_graph_get_next_endpoint()
> +        * if the device doesn't have any graph connections
> +        */
> +       if (!of_graph_is_present(node))
> +         return;

The problem here is that you are masking genuine errors.
The solution is to either call this only if the device type is one
that ports are not required - i.e. ETE, or upgrade the .dts bindings
for the rest of the ETM devices to yaml so that the ports requirement
is checked and validated there.

Regards

Mike

>         do {
>                 ep = of_graph_get_next_endpoint(node, ep);
>                 if (!ep)
> --
> 2.7.4
>


-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 02/14] coresight: Do not scan for graph if none is present
  2021-02-02 11:10   ` Mike Leach
@ 2021-02-02 14:36     ` Suzuki K Poulose
  0 siblings, 0 replies; 90+ messages in thread
From: Suzuki K Poulose @ 2021-02-02 14:36 UTC (permalink / raw)
  To: Mike Leach, Anshuman Khandual
  Cc: linux-arm-kernel, Coresight ML, Mathieu Poirier, Linu Cherian,
	Linux Kernel Mailing List

Hi Mike

On 2/2/21 11:10 AM, Mike Leach wrote:
> Hi Ansuman,
> 
> On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
> <anshuman.khandual@arm.com> wrote:
>>
>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>
>> If a graph node is not found for a given node, of_get_next_endpoint()
>> will emit the following error message :
>>
>>   OF: graph: no port node found in /<node_name>
>>
>> If the given component doesn't have any explicit connections (e.g,
>> ETE) we could simply ignore the graph parsing.
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>   drivers/hwtracing/coresight/coresight-platform.c | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c
>> index 3629b78..c594f45 100644
>> --- a/drivers/hwtracing/coresight/coresight-platform.c
>> +++ b/drivers/hwtracing/coresight/coresight-platform.c
>> @@ -90,6 +90,12 @@ static void of_coresight_get_ports_legacy(const struct device_node *node,
>>          struct of_endpoint endpoint;
>>          int in = 0, out = 0;
>>
>> +       /*
>> +        * Avoid warnings in of_graph_get_next_endpoint()
>> +        * if the device doesn't have any graph connections
>> +        */
>> +       if (!of_graph_is_present(node))
>> +         return;
> 
> The problem here is that you are masking genuine errors.

If the graph is not described for a component, where it is
mandatory, it won't be usable by the driver and as such using
the devices will fail.

e.g, if an ETM misses the bindings, tracing will fail. (in either
mode).

> The solution is to either call this only if the device type is one
> that ports are not required - i.e. ETE, or upgrade the .dts bindings

The proposed change is too invasive and is not worth the benefit
that it brings.

The side effect of this patch is, if someone makes a mistake in the
bindings they don't see the "warning" in the dmesg. But will definitely
hit the issue when trying to use the system.

i.e, Functionally there is no change.

On the other hand issuing a warning message for ETE is confusing for
a well behaved user.

> for the rest of the ETM devices to yaml so that the ports requirement
> is checked and validated there.

This is a step that we must take, but in a separate series. And I
don't think this will solve handling non-compliant DTs *immediately*,
as there could be :
  a) DTS that are not upstream (Quite common for CoreSight)
  b) People are getting used to the schema and running schema checks.

So, personally I vote for :

1) Merge this patch in as is
2) Convert the bindings to Yaml in a separate series.

Suzuki


^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks
  2021-02-02  9:42     ` Suzuki K Poulose
@ 2021-02-02 16:33       ` Mike Leach
  2021-02-02 22:41         ` Suzuki K Poulose
  2021-02-02 16:37       ` Mathieu Poirier
  1 sibling, 1 reply; 90+ messages in thread
From: Mike Leach @ 2021-02-02 16:33 UTC (permalink / raw)
  To: Suzuki K Poulose
  Cc: Mathieu Poirier, Anshuman Khandual, linux-arm-kernel,
	Coresight ML, Linu Cherian, Linux Kernel Mailing List

Hi,

On Tue, 2 Feb 2021 at 09:42, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>
> On 2/1/21 11:17 PM, Mathieu Poirier wrote:
> > Hi Anshuman,
> >
> > I have started reviewing this set.  As it is quite voluminous comments will
> > come over serveral days.  I will let you know when I am done.
> >
> > On Wed, Jan 27, 2021 at 02:25:25PM +0530, Anshuman Khandual wrote:
> >> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> >>
> >> When there are multiple sinks on the system, in the absence
> >> of a specified sink, it is quite possible that a default sink
> >> for an ETM could be different from that of another ETM. However
> >> we do not support having multiple sinks for an event yet. This
> >> patch allows the event to use the default sinks on the ETMs
> >> where they are scheduled as long as the sinks are of the same
> >> type.
> >>
> >> e.g, if we have 1x1 topology with per-CPU ETRs, the event can
> >> use the per-CPU ETR for the session. However, if the sinks
> >> are of different type, e.g TMC-ETR on one and a custom sink
> >> on another, the event will only trace on the first detected
> >> sink.
> >>
> >
> > I found the above changelog very confusing - I read it several times and still
> > couldn't get all of it.  In the end this patch prevents sinks of different types
> > from being used for session, and this is what the text should reflect.
>
> Sorry about that. Your inference is correct, but it is only a side effect
> of the primary motive. How about the following :
>
> "When a sink is not specified by the user, the etm perf driver
> finds a suitable sink automatically based on the first ETM, where
> this event could be scheduled. Then we allocate the sink buffer based
> on the selected sink. This is fine for a CPU bound event as the "sink"
> is always guaranteed to be reachable from the ETM (as this is the only
> ETM where the event is going to be scheduled). However, if we have a task
> bound event, the event could be scheduled on any of the ETMs on the
> system. In this case, currently we automatically select a sink and exclude
> any ETMs that are not reachable from the selected sink. This is
> problematic for 1x1 configurations as we end up in tracing the event
> only on the "first" ETM, as the default sink is local to the first
> ETM and unreachable from the rest.
> However, we could allow the other ETMs to trace if they all have a
> sink that is compatible with the "selected" sink and can use the
> sink buffer. This can be easily done by verifying that they are
> all driven by the same driver and matches the same subtype."
>


Not sure that the logic here makes total sense - I can't see _why_
multiple sinks need to be of the same type.

1) This patch is designed to allow multiple sinks to be used in a 1:1
topology system - but there is no specific restriction here - and N:M
should work on the same basis
2) This implies that multiple sinks will work within the coresight
infrastucture.
3)  The sink interface -> struct coresight_ops_sink allows sinks to be
abstracted - therefore whichever sink is chosen the coresight
infrastructure calls the operations for the given sink.
4) Each individual sink, will have its own hardware buffer - copied
into the perf buffers at some appropriate point.

Thus if the users specifies a selected sink - we need to eliminate any
source that cannot reach it.
If not we need to find the relevant default sink for the source, which
might be a shared ETR, or per CPU TRBE / ETR, and the abstraction
logic ought to handle getting the captured data to the correct place.
If it doesn't then we are on shaky ground with any multiple sink
solution.

On the face of it - type is irrelevant. If I am missing something -
this patch needs a better explanation.


>
> >
> >> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> >> Cc: Mike Leach <mike.leach@linaro.org>
> >> Tested-by: Linu Cherian <lcherian@marvell.com>
> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> >> ---
> >>   drivers/hwtracing/coresight/coresight-etm-perf.c | 48 +++++++++++++++++++-----
> >>   1 file changed, 38 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
> >> index bdc34ca..eb9e7e9 100644
> >> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> >> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> >> @@ -204,6 +204,13 @@ static void etm_free_aux(void *data)
> >>      schedule_work(&event_data->work);
> >>   }
> >>
> >> +static bool sinks_match(struct coresight_device *a, struct coresight_device *b)
> >> +{
> >> +    if (!a || !b)
> >> +            return false;
> >> +    return (sink_ops(a) == sink_ops(b));
> >
> > Yes
>
> I think we can tighten this by verifying the dev->sub_type matches too.
>
> >
> >> +}
> >> +
> >>   static void *etm_setup_aux(struct perf_event *event, void **pages,
> >>                         int nr_pages, bool overwrite)
> >>   {
> >> @@ -212,6 +219,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
> >>      cpumask_t *mask;
> >>      struct coresight_device *sink = NULL;
> >
> >          struct coresight_device *user_sink = NULL;
> >
> >>      struct etm_event_data *event_data = NULL;
> >> +    bool sink_forced = false;
> >>
> >>      event_data = alloc_event_data(cpu);
> >>      if (!event_data)
> >> @@ -222,6 +230,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
> >>      if (event->attr.config2) {
> >>              id = (u32)event->attr.config2;
> >>              sink = coresight_get_sink_by_id(id);
> >
> >                  user_sink = coresight_get_sink_by_id(id);
> >
> >> +            sink_forced = true;

The comment for this block uses the term "selected sink", and the
functions use _default_sink . This may read better if we rename the
bool to "selected_sink" rather than "sink_forced"

Regards

Mike
> >>      }
> >>
> >>      mask = &event_data->mask;
> >> @@ -235,7 +244,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
> >>       */
> >>      for_each_cpu(cpu, mask) {
> >>              struct list_head *path;
> >> -            struct coresight_device *csdev;
> >
> >                  struct coresight_device *last_sink = NULL;
> >
> >> +            struct coresight_device *csdev, *new_sink;
> >>
> >>              csdev = per_cpu(csdev_src, cpu);
> >>              /*
> >> @@ -249,21 +258,35 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
> >>              }
> >>
> >>              /*
> >> -             * No sink provided - look for a default sink for one of the
> >> -             * devices. At present we only support topology where all CPUs
> >> -             * use the same sink [N:1], so only need to find one sink. The
> >> -             * coresight_build_path later will remove any CPU that does not
> >> -             * attach to the sink, or if we have not found a sink.
> >> +             * No sink provided - look for a default sink for all the devices.
> >> +             * We only support multiple sinks, only if all the default sinks
> >> +             * are of the same type, so that the sink buffer can be shared
> >> +             * as the event moves around. We don't trace on a CPU if it can't
> >
> > s/can't/can't./
> >
> >> +             *
> >
> > Extra line
> >
>
> OK
>
> >>               */
> >> -            if (!sink)
> >> -                    sink = coresight_find_default_sink(csdev);
> >> +            if (!sink_forced) {
> >> +                    new_sink = coresight_find_default_sink(csdev);
> >> +                    if (!new_sink) {
> >> +                            cpumask_clear_cpu(cpu, mask);
> >> +                            continue;
> >> +                    }
> >> +                    /* Skip checks for the first sink */
> >> +                    if (!sink) {
> >> +                           sink = new_sink;
> >> +                    } else if (!sinks_match(new_sink, sink)) {
> >> +                            cpumask_clear_cpu(cpu, mask);
> >> +                            continue;
> >> +                    }
> >> +            } else {
> >> +                    new_sink = sink;
> >> +            }
> >
> >                  if (!user_sink) {
> >                          /* find default sink for this CPU */
> >                          sink = coresight_find_default_sink(csdev);
> >                          if (!sink) {
> >                                  cpumask_clear_cpu(cpu, mask);
> >                                  continue;
> >                          }
> >
> >                          /* Chech new sink with last sink */
> >                          if (last_sink && !sink_match(last_sink, sink)) {
> >                                  cpumask_clear_cpu(cpu, mask);
> >                                  continue;
> >                          }
> >
> >                          last_sink = sink;
> >                  } else {
> >                          sink = user_sink;
> >                  }
> >
>
> Agreed, it is much better readable.
>
> Suzuki



--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks
  2021-02-02  9:42     ` Suzuki K Poulose
  2021-02-02 16:33       ` Mike Leach
@ 2021-02-02 16:37       ` Mathieu Poirier
  1 sibling, 0 replies; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-02 16:37 UTC (permalink / raw)
  To: Suzuki K Poulose
  Cc: Anshuman Khandual, linux-arm-kernel, coresight, mike.leach,
	lcherian, linux-kernel

On Tue, Feb 02, 2021 at 09:42:34AM +0000, Suzuki K Poulose wrote:
> On 2/1/21 11:17 PM, Mathieu Poirier wrote:
> > Hi Anshuman,
> > 
> > I have started reviewing this set.  As it is quite voluminous comments will
> > come over serveral days.  I will let you know when I am done.
> > 
> > On Wed, Jan 27, 2021 at 02:25:25PM +0530, Anshuman Khandual wrote:
> > > From: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > 
> > > When there are multiple sinks on the system, in the absence
> > > of a specified sink, it is quite possible that a default sink
> > > for an ETM could be different from that of another ETM. However
> > > we do not support having multiple sinks for an event yet. This
> > > patch allows the event to use the default sinks on the ETMs
> > > where they are scheduled as long as the sinks are of the same
> > > type.
> > > 
> > > e.g, if we have 1x1 topology with per-CPU ETRs, the event can
> > > use the per-CPU ETR for the session. However, if the sinks
> > > are of different type, e.g TMC-ETR on one and a custom sink
> > > on another, the event will only trace on the first detected
> > > sink.
> > > 
> > 
> > I found the above changelog very confusing - I read it several times and still
> > couldn't get all of it.  In the end this patch prevents sinks of different types
> > from being used for session, and this is what the text should reflect.
> 
> Sorry about that. Your inference is correct, but it is only a side effect
> of the primary motive. How about the following :
> 
> "When a sink is not specified by the user, the etm perf driver
> finds a suitable sink automatically based on the first ETM, where
> this event could be scheduled. Then we allocate the sink buffer based
> on the selected sink. This is fine for a CPU bound event as the "sink"
> is always guaranteed to be reachable from the ETM (as this is the only
> ETM where the event is going to be scheduled). However, if we have a task
> bound event, the event could be scheduled on any of the ETMs on the
> system. In this case, currently we automatically select a sink and exclude
> any ETMs that are not reachable from the selected sink. This is
> problematic for 1x1 configurations as we end up in tracing the event
> only on the "first" ETM, as the default sink is local to the first
> ETM and unreachable from the rest.
> However, we could allow the other ETMs to trace if they all have a
> sink that is compatible with the "selected" sink and can use the
> sink buffer. This can be easily done by verifying that they are
> all driven by the same driver and matches the same subtype."
>

Much better, thanks for the rework.
 
> 
> > > Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> > > Cc: Mike Leach <mike.leach@linaro.org>
> > > Tested-by: Linu Cherian <lcherian@marvell.com>
> > > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> > > ---
> > >   drivers/hwtracing/coresight/coresight-etm-perf.c | 48 +++++++++++++++++++-----
> > >   1 file changed, 38 insertions(+), 10 deletions(-)
> > > 
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
> > > index bdc34ca..eb9e7e9 100644
> > > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> > > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> > > @@ -204,6 +204,13 @@ static void etm_free_aux(void *data)
> > >   	schedule_work(&event_data->work);
> > >   }
> > > +static bool sinks_match(struct coresight_device *a, struct coresight_device *b)
> > > +{
> > > +	if (!a || !b)
> > > +		return false;
> > > +	return (sink_ops(a) == sink_ops(b));
> > 
> > Yes
> 
> I think we can tighten this by verifying the dev->sub_type matches too.
> 

We could do that but I'm not sure we need to.  I remember spending a few minutes
yesterday thinking about ways to make the test more stringent but in the end I
thought what you had was sufficient, at least for now.  I'll leave that one to
you - proceed as you see fit. 

> > 
> > > +}
> > > +
> > >   static void *etm_setup_aux(struct perf_event *event, void **pages,
> > >   			   int nr_pages, bool overwrite)
> > >   {
> > > @@ -212,6 +219,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
> > >   	cpumask_t *mask;
> > >   	struct coresight_device *sink = NULL;
> > 
> >          struct coresight_device *user_sink = NULL;
> > 
> > >   	struct etm_event_data *event_data = NULL;
> > > +	bool sink_forced = false;
> > >   	event_data = alloc_event_data(cpu);
> > >   	if (!event_data)
> > > @@ -222,6 +230,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
> > >   	if (event->attr.config2) {
> > >   		id = (u32)event->attr.config2;
> > >   		sink = coresight_get_sink_by_id(id);
> > 
> >                  user_sink = coresight_get_sink_by_id(id);
> > 
> > > +		sink_forced = true;
> > >   	}
> > >   	mask = &event_data->mask;
> > > @@ -235,7 +244,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
> > >   	 */
> > >   	for_each_cpu(cpu, mask) {
> > >   		struct list_head *path;
> > > -		struct coresight_device *csdev;
> > 
> >                  struct coresight_device *last_sink = NULL;
> > 
> > > +		struct coresight_device *csdev, *new_sink;
> > >   		csdev = per_cpu(csdev_src, cpu);
> > >   		/*
> > > @@ -249,21 +258,35 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
> > >   		}
> > >   		/*
> > > -		 * No sink provided - look for a default sink for one of the
> > > -		 * devices. At present we only support topology where all CPUs
> > > -		 * use the same sink [N:1], so only need to find one sink. The
> > > -		 * coresight_build_path later will remove any CPU that does not
> > > -		 * attach to the sink, or if we have not found a sink.
> > > +		 * No sink provided - look for a default sink for all the devices.
> > > +		 * We only support multiple sinks, only if all the default sinks
> > > +		 * are of the same type, so that the sink buffer can be shared
> > > +		 * as the event moves around. We don't trace on a CPU if it can't
> > 
> > s/can't/can't./
> > 
> > > +		 *
> > 
> > Extra line
> > 
> 
> OK
> 
> > >   		 */
> > > -		if (!sink)
> > > -			sink = coresight_find_default_sink(csdev);
> > > +		if (!sink_forced) {
> > > +			new_sink = coresight_find_default_sink(csdev);
> > > +			if (!new_sink) {
> > > +				cpumask_clear_cpu(cpu, mask);
> > > +				continue;
> > > +			}
> > > +			/* Skip checks for the first sink */
> > > +			if (!sink) {
> > > +			       sink = new_sink;
> > > +			} else if (!sinks_match(new_sink, sink)) {
> > > +				cpumask_clear_cpu(cpu, mask);
> > > +				continue;
> > > +			}
> > > +		} else {
> > > +			new_sink = sink;
> > > +		}
> > 
> >                  if (!user_sink) {
> >                          /* find default sink for this CPU */
> >                          sink = coresight_find_default_sink(csdev);
> >                          if (!sink) {
> >                                  cpumask_clear_cpu(cpu, mask);
> >                                  continue;
> >                          }
> > 
> >                          /* Chech new sink with last sink */
> >                          if (last_sink && !sink_match(last_sink, sink)) {
> >                                  cpumask_clear_cpu(cpu, mask);
> >                                  continue;
> >                          }
> > 
> >                          last_sink = sink;
> >                  } else {
> >                          sink = user_sink;
> >                  }
> > 
> 
> Agreed, it is much better readable.
> 
> Suzuki

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock
  2021-01-27  8:55 ` [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
@ 2021-02-02 17:40   ` Mathieu Poirier
  2021-02-02 18:03   ` Mathieu Poirier
  2021-02-15 14:08   ` Mike Leach
  2 siblings, 0 replies; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-02 17:40 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel

On Wed, Jan 27, 2021 at 02:25:27PM +0530, Anshuman Khandual wrote:
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> ETE may not implement the OS lock and instead could rely on
> the PE OS Lock for the trace unit access. This is indicated
> by the TRCOLSR.OSM == 0b100. Add support for handling the
> PE OS lock
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-core.c | 50 ++++++++++++++++++----
>  drivers/hwtracing/coresight/coresight-etm4x.h      | 15 +++++++
>  2 files changed, 56 insertions(+), 9 deletions(-)

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 473ab74..9edf8be 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -114,30 +114,59 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
>  	}
>  }
>  
> -static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa)
> +static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
> +			       struct csdev_access *csa)
>  {
> -	/* Writing 0 to TRCOSLAR unlocks the trace registers */
> -	etm4x_relaxed_write32(csa, 0x0, TRCOSLAR);
> -	drvdata->os_unlock = true;
> +	u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
> +
> +	drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
> +}
> +
> +static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
> +			      struct csdev_access *csa, u32 val)
> +{
> +	val = !!val;
> +
> +	switch (drvdata->os_lock_model) {
> +	case ETM_OSLOCK_PRESENT:
> +		etm4x_relaxed_write32(csa, val, TRCOSLAR);
> +		break;
> +	case ETM_OSLOCK_PE:
> +		write_sysreg_s(val, SYS_OSLAR_EL1);
> +		break;
> +	default:
> +		pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
> +			     smp_processor_id(), drvdata->os_lock_model);
> +		fallthrough;
> +	case ETM_OSLOCK_NI:
> +		return;
> +	}
>  	isb();
>  }
>  
> +static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
> +				      struct csdev_access *csa)
> +{
> +	WARN_ON(drvdata->cpu != smp_processor_id());
> +
> +	/* Writing 0 to OS Lock unlocks the trace unit registers */
> +	etm_write_os_lock(drvdata, csa, 0x0);
> +	drvdata->os_unlock = true;
> +}
> +
>  static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
>  {
>  	if (!WARN_ON(!drvdata->csdev))
>  		etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
> -
>  }
>  
>  static void etm4_os_lock(struct etmv4_drvdata *drvdata)
>  {
>  	if (WARN_ON(!drvdata->csdev))
>  		return;
> -
> -	/* Writing 0x1 to TRCOSLAR locks the trace registers */
> -	etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR);
> +	/* Writing 0x1 to OS Lock locks the trace registers */
> +	etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
>  	drvdata->os_unlock = false;
> -	isb();
>  }
>  
>  static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
> @@ -906,6 +935,9 @@ static void etm4_init_arch_data(void *info)
>  	if (!etm4_init_csdev_access(drvdata, csa))
>  		return;
>  
> +	/* Detect the support for OS Lock before we actuall use it */
> +	etm_detect_os_lock(drvdata, csa);
> +
>  	/* Make sure all registers are accessible */
>  	etm4_os_unlock_csa(drvdata, csa);
>  	etm4_cs_unlock(drvdata, csa);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 0af6057..0e86eba 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -506,6 +506,20 @@
>  					 ETM_MODE_EXCL_USER)
>  
>  /*
> + * TRCOSLSR.OSLM advertises the OS Lock model.
> + * OSLM[2:0] = TRCOSLSR[4:3,0]
> + *
> + *	0b000 - Trace OS Lock is not implemented.
> + *	0b010 - Trace OS Lock is implemented.
> + *	0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock.
> + */
> +#define ETM_OSLOCK_NI		0b000
> +#define ETM_OSLOCK_PRESENT	0b010
> +#define ETM_OSLOCK_PE		0b100
> +
> +#define ETM_OSLSR_OSLM(oslsr)	((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1))
> +
> +/*
>   * TRCDEVARCH Bit field definitions
>   * Bits[31:21]	- ARCHITECT = Always Arm Ltd.
>   *                * Bits[31:28] = 0x4
> @@ -897,6 +911,7 @@ struct etmv4_drvdata {
>  	u8				s_ex_level;
>  	u8				ns_ex_level;
>  	u8				q_support;
> +	u8				os_lock_model;
>  	bool				sticky_enable;
>  	bool				boot_enable;
>  	bool				os_unlock;
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access
  2021-01-27  8:55 ` [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access Anshuman Khandual
@ 2021-02-02 17:52   ` Mathieu Poirier
  2021-02-03 15:51     ` Suzuki K Poulose
  2021-02-15 14:08   ` Mike Leach
  1 sibling, 1 reply; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-02 17:52 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel

On Wed, Jan 27, 2021 at 02:25:28PM +0530, Anshuman Khandual wrote:
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> Add support for handling the system registers for Embedded Trace
> Extensions (ETE). ETE shares most of the registers with ETMv4 except
> for some and also adds some new registers. Re-arrange the ETMv4x list
> to share the common definitions and add the ETE sysreg support.
> 
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-core.c | 32 +++++++++++++
>  drivers/hwtracing/coresight/coresight-etm4x.h      | 52 ++++++++++++++++++----
>  2 files changed, 75 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 9edf8be..9e92d2a 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -114,6 +114,38 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
>  	}
>  }
>  
> +u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
> +{
> +	u64 res = 0;
> +
> +	switch (offset) {
> +	ETE_READ_CASES(res)
> +	default :
> +		WARN_ONCE(1, "ete: trying to read unsupported register @%x\n",
> +			 offset);

Alignment

> +	}
> +
> +	if (!_relaxed)
> +		__iormb(res);	/* Imitate the !relaxed I/O helpers */
> +
> +	return res;
> +}
> +
> +void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
> +{
> +	if (!_relaxed)
> +		__iowmb();	/* Imitate the !relaxed I/O helpers */
> +	if (!_64bit)
> +		val &= GENMASK(31, 0);
> +
> +	switch (offset) {
> +	ETE_WRITE_CASES(val)
> +	default :
> +		WARN_ONCE(1, "ete: trying to write to unsupported register @%x\n",
> +			offset);

Alignment

> +	}
> +}

The etm4x_sysreg_xyz() equivalent of these use a pr_warn_ratelimited() rather
than a WARN_ONE().  

With that:

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

> +
>  static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
>  			       struct csdev_access *csa)
>  {
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 0e86eba..ca24ac5 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -29,6 +29,7 @@
>  #define TRCAUXCTLR			0x018
>  #define TRCEVENTCTL0R			0x020
>  #define TRCEVENTCTL1R			0x024
> +#define TRCRSR				0x028
>  #define TRCSTALLCTLR			0x02C
>  #define TRCTSCTLR			0x030
>  #define TRCSYNCPR			0x034
> @@ -49,6 +50,7 @@
>  #define TRCSEQRSTEVR			0x118
>  #define TRCSEQSTR			0x11C
>  #define TRCEXTINSELR			0x120
> +#define TRCEXTINSELRn(n)		(0x120 + (n * 4)) /* n = 0-3 */
>  #define TRCCNTRLDVRn(n)			(0x140 + (n * 4)) /* n = 0-3 */
>  #define TRCCNTCTLRn(n)			(0x150 + (n * 4)) /* n = 0-3 */
>  #define TRCCNTVRn(n)			(0x160 + (n * 4)) /* n = 0-3 */
> @@ -160,10 +162,22 @@
>  #define CASE_NOP(__unused, x)					\
>  	case (x):	/* fall through */
>  
> +#define ETE_ONLY_SYSREG_LIST(op, val)		\
> +	CASE_##op((val), TRCRSR)		\
> +	CASE_##op((val), TRCEXTINSELRn(1))	\
> +	CASE_##op((val), TRCEXTINSELRn(2))	\
> +	CASE_##op((val), TRCEXTINSELRn(3))
> +
>  /* List of registers accessible via System instructions */
> -#define ETM_SYSREG_LIST(op, val)		\
> -	CASE_##op((val), TRCPRGCTLR)		\
> +#define ETM4x_ONLY_SYSREG_LIST(op, val)		\
>  	CASE_##op((val), TRCPROCSELR)		\
> +	CASE_##op((val), TRCVDCTLR)		\
> +	CASE_##op((val), TRCVDSACCTLR)		\
> +	CASE_##op((val), TRCVDARCCTLR)		\
> +	CASE_##op((val), TRCOSLAR)
> +
> +#define ETM_COMMON_SYSREG_LIST(op, val)		\
> +	CASE_##op((val), TRCPRGCTLR)		\
>  	CASE_##op((val), TRCSTATR)		\
>  	CASE_##op((val), TRCCONFIGR)		\
>  	CASE_##op((val), TRCAUXCTLR)		\
> @@ -180,9 +194,6 @@
>  	CASE_##op((val), TRCVIIECTLR)		\
>  	CASE_##op((val), TRCVISSCTLR)		\
>  	CASE_##op((val), TRCVIPCSSCTLR)		\
> -	CASE_##op((val), TRCVDCTLR)		\
> -	CASE_##op((val), TRCVDSACCTLR)		\
> -	CASE_##op((val), TRCVDARCCTLR)		\
>  	CASE_##op((val), TRCSEQEVRn(0))		\
>  	CASE_##op((val), TRCSEQEVRn(1))		\
>  	CASE_##op((val), TRCSEQEVRn(2))		\
> @@ -277,7 +288,6 @@
>  	CASE_##op((val), TRCSSPCICRn(5))	\
>  	CASE_##op((val), TRCSSPCICRn(6))	\
>  	CASE_##op((val), TRCSSPCICRn(7))	\
> -	CASE_##op((val), TRCOSLAR)		\
>  	CASE_##op((val), TRCOSLSR)		\
>  	CASE_##op((val), TRCACVRn(0))		\
>  	CASE_##op((val), TRCACVRn(1))		\
> @@ -369,12 +379,36 @@
>  	CASE_##op((val), TRCPIDR2)		\
>  	CASE_##op((val), TRCPIDR3)
>  
> -#define ETM4x_READ_SYSREG_CASES(res)	ETM_SYSREG_LIST(READ, (res))
> -#define ETM4x_WRITE_SYSREG_CASES(val)	ETM_SYSREG_LIST(WRITE, (val))
> +#define ETM4x_READ_SYSREG_CASES(res)		\
> +	ETM_COMMON_SYSREG_LIST(READ, (res))	\
> +	ETM4x_ONLY_SYSREG_LIST(READ, (res))
> +
> +#define ETM4x_WRITE_SYSREG_CASES(val)		\
> +	ETM_COMMON_SYSREG_LIST(WRITE, (val))	\
> +	ETM4x_ONLY_SYSREG_LIST(WRITE, (val))
> +
> +#define ETM_COMMON_SYSREG_LIST_CASES		\
> +	ETM_COMMON_SYSREG_LIST(NOP, __unused)
> +
> +#define ETM4x_SYSREG_LIST_CASES			\
> +	ETM_COMMON_SYSREG_LIST_CASES		\
> +	ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
>  
> -#define ETM4x_SYSREG_LIST_CASES		ETM_SYSREG_LIST(NOP, __unused)
>  #define ETM4x_MMAP_LIST_CASES		ETM_MMAP_LIST(NOP, __unused)
>  
> +/* ETE only supports system register access */
> +#define ETE_READ_CASES(res)			\
> +	ETM_COMMON_SYSREG_LIST(READ, (res))	\
> +	ETE_ONLY_SYSREG_LIST(READ, (res))
> +
> +#define ETE_WRITE_CASES(val)			\
> +	ETM_COMMON_SYSREG_LIST(WRITE, (val))	\
> +	ETE_ONLY_SYSREG_LIST(WRITE, (val))
> +
> +#define ETE_ONLY_SYSREG_LIST_CASES		\
> +	ETM_COMMON_SYSREG_LIST_CASES		\
> +	ETE_ONLY_SYSREG_LIST(NOP, __unused)
> +
>  #define read_etm4x_sysreg_offset(offset, _64bit)				\
>  	({									\
>  		u64 __val;							\
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock
  2021-01-27  8:55 ` [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
  2021-02-02 17:40   ` Mathieu Poirier
@ 2021-02-02 18:03   ` Mathieu Poirier
  2021-02-15 14:08   ` Mike Leach
  2 siblings, 0 replies; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-02 18:03 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel

On Wed, Jan 27, 2021 at 02:25:27PM +0530, Anshuman Khandual wrote:
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> ETE may not implement the OS lock and instead could rely on
> the PE OS Lock for the trace unit access. This is indicated
> by the TRCOLSR.OSM == 0b100. Add support for handling the
> PE OS lock
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-core.c | 50 ++++++++++++++++++----
>  drivers/hwtracing/coresight/coresight-etm4x.h      | 15 +++++++
>  2 files changed, 56 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 473ab74..9edf8be 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -114,30 +114,59 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
>  	}
>  }
>  
> -static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa)
> +static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
> +			       struct csdev_access *csa)
>  {
> -	/* Writing 0 to TRCOSLAR unlocks the trace registers */
> -	etm4x_relaxed_write32(csa, 0x0, TRCOSLAR);
> -	drvdata->os_unlock = true;
> +	u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
> +
> +	drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
> +}
> +
> +static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
> +			      struct csdev_access *csa, u32 val)
> +{
> +	val = !!val;
> +
> +	switch (drvdata->os_lock_model) {
> +	case ETM_OSLOCK_PRESENT:
> +		etm4x_relaxed_write32(csa, val, TRCOSLAR);
> +		break;
> +	case ETM_OSLOCK_PE:
> +		write_sysreg_s(val, SYS_OSLAR_EL1);
> +		break;
> +	default:
> +		pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
> +			     smp_processor_id(), drvdata->os_lock_model);
> +		fallthrough;
> +	case ETM_OSLOCK_NI:
> +		return;
> +	}
>  	isb();
>  }
>  
> +static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
> +				      struct csdev_access *csa)
> +{
> +	WARN_ON(drvdata->cpu != smp_processor_id());
> +
> +	/* Writing 0 to OS Lock unlocks the trace unit registers */
> +	etm_write_os_lock(drvdata, csa, 0x0);
> +	drvdata->os_unlock = true;
> +}
> +
>  static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
>  {
>  	if (!WARN_ON(!drvdata->csdev))
>  		etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
> -
>  }
>  
>  static void etm4_os_lock(struct etmv4_drvdata *drvdata)
>  {
>  	if (WARN_ON(!drvdata->csdev))
>  		return;
> -
> -	/* Writing 0x1 to TRCOSLAR locks the trace registers */
> -	etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR);
> +	/* Writing 0x1 to OS Lock locks the trace registers */
> +	etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
>  	drvdata->os_unlock = false;
> -	isb();
>  }
>  
>  static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
> @@ -906,6 +935,9 @@ static void etm4_init_arch_data(void *info)
>  	if (!etm4_init_csdev_access(drvdata, csa))
>  		return;
>  
> +	/* Detect the support for OS Lock before we actuall use it */

s/actuall/actually

> +	etm_detect_os_lock(drvdata, csa);
> +
>  	/* Make sure all registers are accessible */
>  	etm4_os_unlock_csa(drvdata, csa);
>  	etm4_cs_unlock(drvdata, csa);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 0af6057..0e86eba 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -506,6 +506,20 @@
>  					 ETM_MODE_EXCL_USER)
>  
>  /*
> + * TRCOSLSR.OSLM advertises the OS Lock model.
> + * OSLM[2:0] = TRCOSLSR[4:3,0]
> + *
> + *	0b000 - Trace OS Lock is not implemented.
> + *	0b010 - Trace OS Lock is implemented.
> + *	0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock.
> + */
> +#define ETM_OSLOCK_NI		0b000
> +#define ETM_OSLOCK_PRESENT	0b010
> +#define ETM_OSLOCK_PE		0b100
> +
> +#define ETM_OSLSR_OSLM(oslsr)	((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1))
> +
> +/*
>   * TRCDEVARCH Bit field definitions
>   * Bits[31:21]	- ARCHITECT = Always Arm Ltd.
>   *                * Bits[31:28] = 0x4
> @@ -897,6 +911,7 @@ struct etmv4_drvdata {
>  	u8				s_ex_level;
>  	u8				ns_ex_level;
>  	u8				q_support;
> +	u8				os_lock_model;
>  	bool				sticky_enable;
>  	bool				boot_enable;
>  	bool				os_unlock;
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 05/14] coresight: ete: Add support for ETE tracing
  2021-01-27  8:55 ` [PATCH V3 05/14] coresight: ete: Add support for ETE tracing Anshuman Khandual
@ 2021-02-02 18:56   ` Mathieu Poirier
  2021-02-02 22:50     ` Suzuki K Poulose
  2021-02-15 13:21     ` Mike Leach
  0 siblings, 2 replies; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-02 18:56 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel

On Wed, Jan 27, 2021 at 02:25:29PM +0530, Anshuman Khandual wrote:
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> Add ETE as one of the supported device types we support
> with ETM4x driver. The devices are named following the
> existing convention as ete<N>.
> 
> ETE mandates that the trace resource status register is programmed
> before the tracing is turned on. For the moment simply write to
> it indicating TraceActive.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  drivers/hwtracing/coresight/Kconfig                | 10 ++--
>  drivers/hwtracing/coresight/coresight-etm4x-core.c | 56 +++++++++++++++++-----
>  .../hwtracing/coresight/coresight-etm4x-sysfs.c    | 19 ++++++--
>  drivers/hwtracing/coresight/coresight-etm4x.h      | 16 ++++++-
>  4 files changed, 79 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> index 7b44ba2..f154ae7 100644
> --- a/drivers/hwtracing/coresight/Kconfig
> +++ b/drivers/hwtracing/coresight/Kconfig
> @@ -97,15 +97,15 @@ config CORESIGHT_SOURCE_ETM3X
>  	  module will be called coresight-etm3x.
>  
>  config CORESIGHT_SOURCE_ETM4X
> -	tristate "CoreSight Embedded Trace Macrocell 4.x driver"
> +	tristate "CoreSight ETMv4.x / ETE driver"
>  	depends on ARM64
>  	select CORESIGHT_LINKS_AND_SINKS
>  	select PID_IN_CONTEXTIDR
>  	help
> -	  This driver provides support for the ETM4.x tracer module, tracing the
> -	  instructions that a processor is executing. This is primarily useful
> -	  for instruction level tracing. Depending on the implemented version
> -	  data tracing may also be available.
> +	  This driver provides support for the CoreSight Embedded Trace Macrocell
> +	  version 4.x and the Embedded Trace Extensions (ETE). Both are CPU tracer
> +	  modules, tracing the instructions that a processor is executing. This is
> +	  primarily useful for instruction level tracing.
>  
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called coresight-etm4x.
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 9e92d2a..b40e3c2 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -431,6 +431,13 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
>  		etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
>  	}
>  
> +	/*
> +	 * ETE mandates that the TRCRSR is written to before
> +	 * enabling it.
> +	 */
> +	if (etm4x_is_ete(drvdata))
> +		etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
> +
>  	/* Enable the trace unit */
>  	etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
>  
> @@ -864,13 +871,24 @@ static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
>  	 * ETMs implementing sysreg access must implement TRCDEVARCH.
>  	 */
>  	devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
> -	if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH)
> +	switch (devarch & ETM_DEVARCH_ID_MASK) {
> +	case ETM_DEVARCH_ETMv4x_ARCH:
> +		*csa = (struct csdev_access) {
> +			.io_mem	= false,
> +			.read	= etm4x_sysreg_read,
> +			.write	= etm4x_sysreg_write,
> +		};
> +		break;
> +	case ETM_DEVARCH_ETE_ARCH:
> +		*csa = (struct csdev_access) {
> +			.io_mem	= false,
> +			.read	= ete_sysreg_read,
> +			.write	= ete_sysreg_write,
> +		};
> +		break;
> +	default:
>  		return false;
> -	*csa = (struct csdev_access) {
> -		.io_mem	= false,
> -		.read	= etm4x_sysreg_read,
> -		.write	= etm4x_sysreg_write,
> -	};
> +	}
>  
>  	drvdata->arch = etm_devarch_to_arch(devarch);
>  	return true;
> @@ -1808,6 +1826,8 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
>  	struct etmv4_drvdata *drvdata;
>  	struct coresight_desc desc = { 0 };
>  	struct etm4_init_arg init_arg = { 0 };
> +	u8 major, minor;
> +	char *type_name;
>  
>  	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
>  	if (!drvdata)
> @@ -1834,10 +1854,6 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
>  	if (drvdata->cpu < 0)
>  		return drvdata->cpu;
>  
> -	desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
> -	if (!desc.name)
> -		return -ENOMEM;
> -
>  	init_arg.drvdata = drvdata;
>  	init_arg.csa = &desc.access;
>  	init_arg.pid = etm_pid;
> @@ -1853,6 +1869,20 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
>  	if (!desc.access.io_mem ||
>  	    fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
>  		drvdata->skip_power_up = true;

Add a space here...

> +	major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
> +	minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);

And here too.  Othersiwe it makes a big blob in the middle of the function.

> +	if (etm4x_is_ete(drvdata)) {
> +		type_name = "ete";
> +		/* ETE v1 has major version == 5. Adjust this for logging.*/
> +		major -= 4;

I don't have the documentation for the ETE but I would not adjust @major.  I
would simply leave it to what the HW gives us since regardless of the name, the
major revision of the IP block is 5.

> +	} else {
> +		type_name = "etm";
> +	}
> +
> +	desc.name = devm_kasprintf(dev, GFP_KERNEL,
> +				   "%s%d", type_name, drvdata->cpu);
> +	if (!desc.name)
> +		return -ENOMEM;
>  
>  	etm4_init_trace_id(drvdata);
>  	etm4_set_default(&drvdata->config);
> @@ -1881,9 +1911,8 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
>  
>  	etmdrvdata[drvdata->cpu] = drvdata;
>  
> -	dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n",
> -		 drvdata->cpu, ETM_ARCH_MAJOR_VERSION(drvdata->arch),
> -		 ETM_ARCH_MINOR_VERSION(drvdata->arch));
> +	dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
> +		 drvdata->cpu, type_name, major, minor);
>  
>  	if (boot_enable) {
>  		coresight_enable(drvdata->csdev);
> @@ -2027,6 +2056,7 @@ static struct amba_driver etm4x_amba_driver = {
>  
>  static const struct of_device_id etm4_sysreg_match[] = {
>  	{ .compatible	= "arm,coresight-etm4x-sysreg" },
> +	{ .compatible	= "arm,embedded-trace-extension" },
>  	{}
>  };
>  
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index b646d53..1c490bc 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -2374,12 +2374,20 @@ static inline bool
>  etm4x_register_implemented(struct etmv4_drvdata *drvdata, u32 offset)
>  {
>  	switch (offset) {
> -	ETM4x_SYSREG_LIST_CASES
> +	ETM_COMMON_SYSREG_LIST_CASES
>  		/*
> -		 * Registers accessible via system instructions are always
> -		 * implemented.
> +		 * Common registers to ETE & ETM4x accessible via system
> +		 * instructions are always implemented.
>  		 */
>  		return true;
> +
> +	ETM4x_ONLY_SYSREG_LIST_CASES
> +		/*
> +		 * We only support etm4x and ete. So if the device is not
> +		 * ETE, it must be ETMv4x.
> +		 */
> +		return !etm4x_is_ete(drvdata);
> +
>  	ETM4x_MMAP_LIST_CASES
>  		/*
>  		 * Registers accessible only via memory-mapped registers
> @@ -2389,8 +2397,13 @@ etm4x_register_implemented(struct etmv4_drvdata *drvdata, u32 offset)
>  		 * coresight_register() and the csdev is not initialized
>  		 * until that is done. So rely on the drvdata->base to
>  		 * detect if we have a memory mapped access.
> +		 * Also ETE doesn't implement memory mapped access, thus
> +		 * it is sufficient to check that we are using mmio.
>  		 */
>  		return !!drvdata->base;
> +
> +	ETE_ONLY_SYSREG_LIST_CASES
> +		return etm4x_is_ete(drvdata);
>  	}
>  
>  	return false;
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index ca24ac5..8b90de5 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -128,6 +128,8 @@
>  #define TRCCIDR2			0xFF8
>  #define TRCCIDR3			0xFFC
>  
> +#define TRCRSR_TA			BIT(12)
> +
>  /*
>   * System instructions to access ETM registers.
>   * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
> @@ -390,6 +392,9 @@
>  #define ETM_COMMON_SYSREG_LIST_CASES		\
>  	ETM_COMMON_SYSREG_LIST(NOP, __unused)
>  
> +#define ETM4x_ONLY_SYSREG_LIST_CASES		\
> +	ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
> +
>  #define ETM4x_SYSREG_LIST_CASES			\
>  	ETM_COMMON_SYSREG_LIST_CASES		\
>  	ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
> @@ -406,7 +411,6 @@
>  	ETE_ONLY_SYSREG_LIST(WRITE, (val))
>  
>  #define ETE_ONLY_SYSREG_LIST_CASES		\
> -	ETM_COMMON_SYSREG_LIST_CASES		\

This goes in patch 04.

With the above:

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

>  	ETE_ONLY_SYSREG_LIST(NOP, __unused)
>  
>  #define read_etm4x_sysreg_offset(offset, _64bit)				\
> @@ -589,11 +593,14 @@
>  	((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13))
>  
>  #define ETM_DEVARCH_ARCHID_ETMv4x		ETM_DEVARCH_MAKE_ARCHID(0x4)
> +#define ETM_DEVARCH_ARCHID_ETE			ETM_DEVARCH_MAKE_ARCHID(0x5)
>  
>  #define ETM_DEVARCH_ID_MASK						\
>  	(ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT)
>  #define ETM_DEVARCH_ETMv4x_ARCH						\
>  	(ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT)
> +#define ETM_DEVARCH_ETE_ARCH						\
> +	(ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT)
>  
>  #define TRCSTATR_IDLE_BIT		0
>  #define TRCSTATR_PMSTABLE_BIT		1
> @@ -683,6 +690,8 @@
>  #define ETM_ARCH_MINOR_VERSION(arch)	((arch) & 0xfU)
>  
>  #define ETM_ARCH_V4	ETM_ARCH_VERSION(4, 0)
> +#define ETM_ARCH_ETE	ETM_ARCH_VERSION(5, 0)
> +
>  /* Interpretation of resource numbers change at ETM v4.3 architecture */
>  #define ETM_ARCH_V4_3	ETM_ARCH_VERSION(4, 3)
>  
> @@ -989,4 +998,9 @@ void etm4_config_trace_mode(struct etmv4_config *config);
>  
>  u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit);
>  void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit);
> +
> +static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata)
> +{
> +	return drvdata->arch >= ETM_ARCH_ETE;
> +}
>  #endif
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks
  2021-02-02 16:33       ` Mike Leach
@ 2021-02-02 22:41         ` Suzuki K Poulose
  2021-02-04 12:27           ` Mike Leach
  0 siblings, 1 reply; 90+ messages in thread
From: Suzuki K Poulose @ 2021-02-02 22:41 UTC (permalink / raw)
  To: Mike Leach
  Cc: Mathieu Poirier, Anshuman Khandual, linux-arm-kernel,
	Coresight ML, Linu Cherian, Linux Kernel Mailing List

On 2/2/21 4:33 PM, Mike Leach wrote:
> Hi,
> 
> On Tue, 2 Feb 2021 at 09:42, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>>
>> On 2/1/21 11:17 PM, Mathieu Poirier wrote:
>>> Hi Anshuman,
>>>
>>> I have started reviewing this set.  As it is quite voluminous comments will
>>> come over serveral days.  I will let you know when I am done.
>>>
>>> On Wed, Jan 27, 2021 at 02:25:25PM +0530, Anshuman Khandual wrote:
>>>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>>>
>>>> When there are multiple sinks on the system, in the absence
>>>> of a specified sink, it is quite possible that a default sink
>>>> for an ETM could be different from that of another ETM. However
>>>> we do not support having multiple sinks for an event yet. This
>>>> patch allows the event to use the default sinks on the ETMs
>>>> where they are scheduled as long as the sinks are of the same
>>>> type.
>>>>
>>>> e.g, if we have 1x1 topology with per-CPU ETRs, the event can
>>>> use the per-CPU ETR for the session. However, if the sinks
>>>> are of different type, e.g TMC-ETR on one and a custom sink
>>>> on another, the event will only trace on the first detected
>>>> sink.
>>>>
>>>
>>> I found the above changelog very confusing - I read it several times and still
>>> couldn't get all of it.  In the end this patch prevents sinks of different types
>>> from being used for session, and this is what the text should reflect.
>>
>> Sorry about that. Your inference is correct, but it is only a side effect
>> of the primary motive. How about the following :
>>
>> "When a sink is not specified by the user, the etm perf driver
>> finds a suitable sink automatically based on the first ETM, where
>> this event could be scheduled. Then we allocate the sink buffer based
>> on the selected sink. This is fine for a CPU bound event as the "sink"
>> is always guaranteed to be reachable from the ETM (as this is the only
>> ETM where the event is going to be scheduled). However, if we have a task
>> bound event, the event could be scheduled on any of the ETMs on the
>> system. In this case, currently we automatically select a sink and exclude
>> any ETMs that are not reachable from the selected sink. This is
>> problematic for 1x1 configurations as we end up in tracing the event
>> only on the "first" ETM, as the default sink is local to the first
>> ETM and unreachable from the rest.
>> However, we could allow the other ETMs to trace if they all have a
>> sink that is compatible with the "selected" sink and can use the
>> sink buffer. This can be easily done by verifying that they are
>> all driven by the same driver and matches the same subtype."
>>
> 
> 
> Not sure that the logic here makes total sense - I can't see _why_
> multiple sinks need to be of the same type.

Because we have a single "sink_config" (read, single sink specific
buffer) for an event. i.e, we do the sink_ops->alloc_buffer() only once
and rightly so. This allocates any buffers that is used by a given sink.
e.g, for ETR it allocates an etr_perf_buffer. Now if we wanted the same
event to run on an ETM with TRBE, the TRBE doesn't have any buffer set up to
collect the trace and cant make any sense of etr_perf_buffer.
However, if there is another ETM with a different ETR, the second
ETR can make sense of the sink_config (etr_perf_buffer) and trace the event.
Please remember that this only applies to task bound events where
the event can be scheduled on different ETMs.

> 
> 1) This patch is designed to allow multiple sinks to be used in a 1:1
> topology system - but there is no specific restriction here - and N:M
> should work on the same basis

Yes, this should work in any topology.

> 2) This implies that multiple sinks will work within the coresight
> infrastucture.

I am afraid I don't understand the context here.

> 3)  The sink interface -> struct coresight_ops_sink allows sinks to be
> abstracted - therefore whichever sink is chosen the coresight
> infrastructure calls the operations for the given sink.

Correct. The patch is trying to ensure that a private data
setup by one driver is not interpreted by another driver as
its own private data. (the private data being sink_config)

> 4) Each individual sink, will have its own hardware buffer - copied
> into the perf buffers at some appropriate point.

Correct. Supporting multiple types of sinks for a single event
is complex and not worth the benefit of the extra complexity.
Moreover we don't expect sane systems to have such a
configuration.

> 
> Thus if the users specifies a selected sink - we need to eliminate any
> source that cannot reach it.

Yes, we do that now.

> If not we need to find the relevant default sink for the source, which
> might be a shared ETR, or per CPU TRBE / ETR, and the abstraction
> logic ought to handle getting the captured data to the correct place.

The abstraction logic works fine, but the per-event private data is
something that makes this complex.

> If it doesn't then we are on shaky ground with any multiple sink
> solution.
> 
> On the face of it - type is irrelevant. If I am missing something -
> this patch needs a better explanation.

I hope the explanation above makes it clear. Please let me know
otherwise.

>>>> +}
>>>> +
>>>>    static void *etm_setup_aux(struct perf_event *event, void **pages,
>>>>                          int nr_pages, bool overwrite)
>>>>    {
>>>> @@ -212,6 +219,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>>>>       cpumask_t *mask;
>>>>       struct coresight_device *sink = NULL;
>>>
>>>           struct coresight_device *user_sink = NULL;
>>>
>>>>       struct etm_event_data *event_data = NULL;
>>>> +    bool sink_forced = false;
>>>>
>>>>       event_data = alloc_event_data(cpu);
>>>>       if (!event_data)
>>>> @@ -222,6 +230,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>>>>       if (event->attr.config2) {
>>>>               id = (u32)event->attr.config2;
>>>>               sink = coresight_get_sink_by_id(id);
>>>
>>>                   user_sink = coresight_get_sink_by_id(id);
>>>
>>>> +            sink_forced = true;
> 
> The comment for this block uses the term "selected sink", and the
> functions use _default_sink . This may read better if we rename the
> bool to "selected_sink" rather than "sink_forced"

I have removed the bool and replaced with the user_sink as Mathieu
suggested.

Thanks for the review
Suzuki

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 05/14] coresight: ete: Add support for ETE tracing
  2021-02-02 18:56   ` Mathieu Poirier
@ 2021-02-02 22:50     ` Suzuki K Poulose
  2021-02-15 13:21     ` Mike Leach
  1 sibling, 0 replies; 90+ messages in thread
From: Suzuki K Poulose @ 2021-02-02 22:50 UTC (permalink / raw)
  To: Mathieu Poirier, Anshuman Khandual
  Cc: linux-arm-kernel, coresight, mike.leach, lcherian, linux-kernel

On 2/2/21 6:56 PM, Mathieu Poirier wrote:
> On Wed, Jan 27, 2021 at 02:25:29PM +0530, Anshuman Khandual wrote:
>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>
>> Add ETE as one of the supported device types we support
>> with ETM4x driver. The devices are named following the
>> existing convention as ete<N>.
>>
>> ETE mandates that the trace resource status register is programmed
>> before the tracing is turned on. For the moment simply write to
>> it indicating TraceActive.
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---

...

>> @@ -1834,10 +1854,6 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
>>   	if (drvdata->cpu < 0)
>>   		return drvdata->cpu;
>>   
>> -	desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
>> -	if (!desc.name)
>> -		return -ENOMEM;
>> -
>>   	init_arg.drvdata = drvdata;
>>   	init_arg.csa = &desc.access;
>>   	init_arg.pid = etm_pid;
>> @@ -1853,6 +1869,20 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
>>   	if (!desc.access.io_mem ||
>>   	    fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
>>   		drvdata->skip_power_up = true;
> 
> Add a space here...
> 
>> +	major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
>> +	minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
> 
> And here too.  Othersiwe it makes a big blob in the middle of the function.
> 
>> +	if (etm4x_is_ete(drvdata)) {
>> +		type_name = "ete";
>> +		/* ETE v1 has major version == 5. Adjust this for logging.*/
>> +		major -= 4;
> 
> I don't have the documentation for the ETE but I would not adjust @major.  I
> would simply leave it to what the HW gives us since regardless of the name, the
> major revision of the IP block is 5.
> 

At the moment only register definitions are public and can be found here :

https://developer.arm.com/docs/ddi0601/g/aarch64-system-registers/trcdevarch

The ETE is natural extension of the ETM architecture to support future
architecture changes and is designed in a way that the same software
can driver both ETM and ETE without much changes.

>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
>> index ca24ac5..8b90de5 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
>> @@ -128,6 +128,8 @@
>>   #define TRCCIDR2			0xFF8
>>   #define TRCCIDR3			0xFFC
>>   
>> +#define TRCRSR_TA			BIT(12)
>> +
>>   /*
>>    * System instructions to access ETM registers.
>>    * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
>> @@ -390,6 +392,9 @@
>>   #define ETM_COMMON_SYSREG_LIST_CASES		\
>>   	ETM_COMMON_SYSREG_LIST(NOP, __unused)
>>   
>> +#define ETM4x_ONLY_SYSREG_LIST_CASES		\
>> +	ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
>> +
>>   #define ETM4x_SYSREG_LIST_CASES			\
>>   	ETM_COMMON_SYSREG_LIST_CASES		\
>>   	ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
>> @@ -406,7 +411,6 @@
>>   	ETE_ONLY_SYSREG_LIST(WRITE, (val))
>>   
>>   #define ETE_ONLY_SYSREG_LIST_CASES		\
>> -	ETM_COMMON_SYSREG_LIST_CASES		\
> 
> This goes in patch 04.
> 

Sure, will move it.

> With the above:
> 
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

Thanks for the review

Suzuki

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access
  2021-02-02 17:52   ` Mathieu Poirier
@ 2021-02-03 15:51     ` Suzuki K Poulose
  0 siblings, 0 replies; 90+ messages in thread
From: Suzuki K Poulose @ 2021-02-03 15:51 UTC (permalink / raw)
  To: Mathieu Poirier, Anshuman Khandual
  Cc: linux-arm-kernel, coresight, mike.leach, lcherian, linux-kernel

On 2/2/21 5:52 PM, Mathieu Poirier wrote:
> On Wed, Jan 27, 2021 at 02:25:28PM +0530, Anshuman Khandual wrote:
>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>
>> Add support for handling the system registers for Embedded Trace
>> Extensions (ETE). ETE shares most of the registers with ETMv4 except
>> for some and also adds some new registers. Re-arrange the ETMv4x list
>> to share the common definitions and add the ETE sysreg support.
>>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>   drivers/hwtracing/coresight/coresight-etm4x-core.c | 32 +++++++++++++
>>   drivers/hwtracing/coresight/coresight-etm4x.h      | 52 ++++++++++++++++++----
>>   2 files changed, 75 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> index 9edf8be..9e92d2a 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> @@ -114,6 +114,38 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
>>   	}
>>   }
>>   
>> +u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
>> +{
>> +	u64 res = 0;
>> +
>> +	switch (offset) {
>> +	ETE_READ_CASES(res)
>> +	default :
>> +		WARN_ONCE(1, "ete: trying to read unsupported register @%x\n",
>> +			 offset);
> 
> Alignment
> 
>> +	}
>> +
>> +	if (!_relaxed)
>> +		__iormb(res);	/* Imitate the !relaxed I/O helpers */
>> +
>> +	return res;
>> +}
>> +
>> +void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
>> +{
>> +	if (!_relaxed)
>> +		__iowmb();	/* Imitate the !relaxed I/O helpers */
>> +	if (!_64bit)
>> +		val &= GENMASK(31, 0);
>> +
>> +	switch (offset) {
>> +	ETE_WRITE_CASES(val)
>> +	default :
>> +		WARN_ONCE(1, "ete: trying to write to unsupported register @%x\n",
>> +			offset);
> 
> Alignment
> 
>> +	}
>> +}
> 
> The etm4x_sysreg_xyz() equivalent of these use a pr_warn_ratelimited() rather
> than a WARN_ONE().
> 
> With that:
> 
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

Converted to pr_warn_ratelimited() to both instances and fixed Alignment

Cheers
Suzuki


^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles
  2021-01-27  8:55 ` [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles Anshuman Khandual
@ 2021-02-03 19:05   ` Mathieu Poirier
  2021-02-03 23:36     ` Suzuki K Poulose
  2021-02-15 16:27   ` Mike Leach
  1 sibling, 1 reply; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-03 19:05 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel, Leo Yan

On Wed, Jan 27, 2021 at 02:25:31PM +0530, Anshuman Khandual wrote:
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> The context associated with an ETM for a given perf event
> includes :
>   - handle -> the perf output handle for the AUX buffer.
>   - the path for the trace components
>   - the buffer config for the sink.
> 
> The path and the buffer config are part of the "aux_priv" data
> (etm_event_data) setup by the setup_aux() callback, and made available
> via perf_get_aux(handle).
> 
> Now with a sink supporting IRQ, the sink could "end" an output
> handle when the buffer reaches the programmed limit and would try
> to restart a handle. This could fail if there is not enough
> space left the AUX buffer (e.g, the userspace has not consumed
> the data). This leaves the "handle" disconnected from the "event"
> and also the "perf_get_aux()" cleared. This all happens within
> the sink driver, without the etm_perf driver being aware.
> Now when the event is actually stopped, etm_event_stop()
> will need to access the "event_data". But since the handle
> is not valid anymore, we loose the information to stop the
> "trace" path. So, we need a reliable way to access the etm_event_data
> even when the handle may not be active.
> 
> This patch replaces the per_cpu handle array with a per_cpu context
> for the ETM, which tracks the "handle" as well as the "etm_event_data".
> The context notes the etm_event_data at etm_event_start() and clears
> it at etm_event_stop(). This makes sure that we don't access a
> stale "etm_event_data" as we are guaranteed that it is not
> freed by free_aux() as long as the event is active and tracing,
> also provides us with access to the critical information
> needed to wind up a session even in the absence of an active
> output_handle.
> 
> This is not an issue for the legacy sinks as none of them supports
> an IRQ and is centrally handled by the etm-perf.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
> Cc: Leo Yan <leo.yan@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm-perf.c | 45 +++++++++++++++++++++---
>  1 file changed, 40 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
> index eb9e7e9..a3977b0 100644
> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> @@ -24,7 +24,26 @@
>  static struct pmu etm_pmu;
>  static bool etm_perf_up;
>  
> -static DEFINE_PER_CPU(struct perf_output_handle, ctx_handle);
> +/*
> + * An ETM context for a running event includes the perf aux handle
> + * and aux_data. For ETM, the aux_data (etm_event_data), consists of
> + * the trace path and the sink configuration. The event data is accessible
> + * via perf_get_aux(handle). However, a sink could "end" a perf output
> + * handle via the IRQ handler. And if the "sink" encounters a failure
> + * to "begin" another session (e.g due to lack of space in the buffer),
> + * the handle will be cleared. Thus, the event_data may not be accessible
> + * from the handle when we get to the etm_event_stop(), which is required
> + * for stopping the trace path. The event_data is guaranteed to stay alive
> + * until "free_aux()", which cannot happen as long as the event is active on
> + * the ETM. Thus the event_data for the session must be part of the ETM context
> + * to make sure we can disable the trace path.
> + */
> +struct etm_ctxt {
> +	struct perf_output_handle handle;
> +	struct etm_event_data *event_data;
> +};
> +
> +static DEFINE_PER_CPU(struct etm_ctxt, etm_ctxt);
>  static DEFINE_PER_CPU(struct coresight_device *, csdev_src);
>  
>  /* ETMv3.5/PTM's ETMCR is 'config' */
> @@ -332,7 +351,8 @@ static void etm_event_start(struct perf_event *event, int flags)
>  {
>  	int cpu = smp_processor_id();
>  	struct etm_event_data *event_data;
> -	struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle);
> +	struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
> +	struct perf_output_handle *handle = &ctxt->handle;
>  	struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
>  	struct list_head *path;
> 
        if (!csdev)
                goto fail;

        /*
         * Something went wrong if an event data is already associated
         * with a context.
         */
        if (WARN_ONE(ctxt->event_data))
                goto fail;
 
> @@ -374,6 +394,8 @@ static void etm_event_start(struct perf_event *event, int flags)
>  	if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF))
>  		goto fail_disable_path;
>  
> +	/* Save the event_data for this ETM */
> +	ctxt->event_data = event_data;
>  out:
>  	return;
>  
> @@ -392,13 +414,20 @@ static void etm_event_stop(struct perf_event *event, int mode)
>  	int cpu = smp_processor_id();
>  	unsigned long size;
>  	struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
> -	struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle);
> -	struct etm_event_data *event_data = perf_get_aux(handle);
> +	struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
> +	struct perf_output_handle *handle = &ctxt->handle;

	struct etm_event_data *event_data = perf_get_aux(handle);
>  	struct list_head *path;
>

        if (WARN_ON(event_data && event_data != ctxt->event_data))
                return;

        event_data = ctxt->event_data;       
	/* Clear the event_data as this ETM is stopping the trace. */
	ctxt->event_data = NULL;

With the above:

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
  
>  	if (event->hw.state == PERF_HES_STOPPED)
>  		return;
>  
> +	/* We must have a valid event_data for a running event */
> +	if (WARN_ON(!event_data))
> +		return;
> +
>  	if (!csdev)
>  		return;
>  
> @@ -416,7 +445,13 @@ static void etm_event_stop(struct perf_event *event, int mode)
>  	/* tell the core */
>  	event->hw.state = PERF_HES_STOPPED;
>  
> -	if (mode & PERF_EF_UPDATE) {
> +	/*
> +	 * If the handle is not bound to an event anymore
> +	 * (e.g, the sink driver was unable to restart the
> +	 * handle due to lack of buffer space), we don't
> +	 * have to do anything here.
> +	 */
> +	if (handle->event && (mode & PERF_EF_UPDATE)) {
>  		if (WARN_ON_ONCE(handle->event != event))
>  			return;
>  
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles
  2021-02-03 19:05   ` Mathieu Poirier
@ 2021-02-03 23:36     ` Suzuki K Poulose
  0 siblings, 0 replies; 90+ messages in thread
From: Suzuki K Poulose @ 2021-02-03 23:36 UTC (permalink / raw)
  To: Mathieu Poirier, Anshuman Khandual
  Cc: linux-arm-kernel, coresight, mike.leach, lcherian, linux-kernel, Leo Yan

On 2/3/21 7:05 PM, Mathieu Poirier wrote:
> On Wed, Jan 27, 2021 at 02:25:31PM +0530, Anshuman Khandual wrote:
>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>
>> The context associated with an ETM for a given perf event
>> includes :
>>    - handle -> the perf output handle for the AUX buffer.
>>    - the path for the trace components
>>    - the buffer config for the sink.
>>
>> The path and the buffer config are part of the "aux_priv" data
>> (etm_event_data) setup by the setup_aux() callback, and made available
>> via perf_get_aux(handle).
>>
>> Now with a sink supporting IRQ, the sink could "end" an output
>> handle when the buffer reaches the programmed limit and would try
>> to restart a handle. This could fail if there is not enough
>> space left the AUX buffer (e.g, the userspace has not consumed
>> the data). This leaves the "handle" disconnected from the "event"
>> and also the "perf_get_aux()" cleared. This all happens within
>> the sink driver, without the etm_perf driver being aware.
>> Now when the event is actually stopped, etm_event_stop()
>> will need to access the "event_data". But since the handle
>> is not valid anymore, we loose the information to stop the
>> "trace" path. So, we need a reliable way to access the etm_event_data
>> even when the handle may not be active.
>>
>> This patch replaces the per_cpu handle array with a per_cpu context
>> for the ETM, which tracks the "handle" as well as the "etm_event_data".
>> The context notes the etm_event_data at etm_event_start() and clears
>> it at etm_event_stop(). This makes sure that we don't access a
>> stale "etm_event_data" as we are guaranteed that it is not
>> freed by free_aux() as long as the event is active and tracing,
>> also provides us with access to the critical information
>> needed to wind up a session even in the absence of an active
>> output_handle.
>>
>> This is not an issue for the legacy sinks as none of them supports
>> an IRQ and is centrally handled by the etm-perf.
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
>> Cc: Leo Yan <leo.yan@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>   drivers/hwtracing/coresight/coresight-etm-perf.c | 45 +++++++++++++++++++++---
>>   1 file changed, 40 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
>> index eb9e7e9..a3977b0 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
>> @@ -24,7 +24,26 @@
>>   static struct pmu etm_pmu;
>>   static bool etm_perf_up;
>>   
>> -static DEFINE_PER_CPU(struct perf_output_handle, ctx_handle);
>> +/*
>> + * An ETM context for a running event includes the perf aux handle
>> + * and aux_data. For ETM, the aux_data (etm_event_data), consists of
>> + * the trace path and the sink configuration. The event data is accessible
>> + * via perf_get_aux(handle). However, a sink could "end" a perf output
>> + * handle via the IRQ handler. And if the "sink" encounters a failure
>> + * to "begin" another session (e.g due to lack of space in the buffer),
>> + * the handle will be cleared. Thus, the event_data may not be accessible
>> + * from the handle when we get to the etm_event_stop(), which is required
>> + * for stopping the trace path. The event_data is guaranteed to stay alive
>> + * until "free_aux()", which cannot happen as long as the event is active on
>> + * the ETM. Thus the event_data for the session must be part of the ETM context
>> + * to make sure we can disable the trace path.
>> + */
>> +struct etm_ctxt {
>> +	struct perf_output_handle handle;
>> +	struct etm_event_data *event_data;
>> +};
>> +
>> +static DEFINE_PER_CPU(struct etm_ctxt, etm_ctxt);
>>   static DEFINE_PER_CPU(struct coresight_device *, csdev_src);
>>   
>>   /* ETMv3.5/PTM's ETMCR is 'config' */
>> @@ -332,7 +351,8 @@ static void etm_event_start(struct perf_event *event, int flags)
>>   {
>>   	int cpu = smp_processor_id();
>>   	struct etm_event_data *event_data;
>> -	struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle);
>> +	struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
>> +	struct perf_output_handle *handle = &ctxt->handle;
>>   	struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
>>   	struct list_head *path;
>>
>          if (!csdev)
>                  goto fail;
> 
>          /*
>           * Something went wrong if an event data is already associated
>           * with a context.
>           */
>          if (WARN_ONE(ctxt->event_data))
>                  goto fail;
>   
>> @@ -374,6 +394,8 @@ static void etm_event_start(struct perf_event *event, int flags)
>>   	if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF))
>>   		goto fail_disable_path;
>>   
>> +	/* Save the event_data for this ETM */
>> +	ctxt->event_data = event_data;
>>   out:
>>   	return;
>>   
>> @@ -392,13 +414,20 @@ static void etm_event_stop(struct perf_event *event, int mode)
>>   	int cpu = smp_processor_id();
>>   	unsigned long size;
>>   	struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
>> -	struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle);
>> -	struct etm_event_data *event_data = perf_get_aux(handle);
>> +	struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
>> +	struct perf_output_handle *handle = &ctxt->handle;
> 
> 	struct etm_event_data *event_data = perf_get_aux(handle);
>>   	struct list_head *path;
>>
> 
>          if (WARN_ON(event_data && event_data != ctxt->event_data))
>                  return;
> 
>          event_data = ctxt->event_data;
> 	/* Clear the event_data as this ETM is stopping the trace. */
> 	ctxt->event_data = NULL;
> 
> With the above:


I have folded the following changes in :

diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c 
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index cf0b0c2d5eed..9f85bf28a82f 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -375,6 +375,10 @@ static void etm_event_start(struct perf_event *event, int flags)
  	if (!csdev)
  		goto fail;

+	/* Have we messed up our tracking ? */
+	if (WARN_ON(ctxt->event_data))
+		goto fail;
+
  	/*
  	 * Deal with the ring buffer API and get a handle on the
  	 * session's information.
@@ -432,11 +436,21 @@ static void etm_event_stop(struct perf_event *event, int mode)
  	struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
  	struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
  	struct perf_output_handle *handle = &ctxt->handle;
-	struct etm_event_data *event_data = ctxt->event_data;
+	struct etm_event_data *event_data;
  	struct list_head *path;

+	/*
+	 * If we still have access to the event_data via handle,
+	 * confirm that we haven't messed up the tracking.
+	 */
+	if (handle->event &&
+	    WARN_ON(perf_get_aux(handle) != ctxt->event_data))
+		return;
+
+	event_data = ctxt->event_data;
  	/* Clear the event_data as this ETM is stopping the trace. */
  	ctxt->event_data = NULL;
+
  	if (event->hw.state == PERF_HES_STOPPED)
  		return;

> 
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

Thanks
Suzuki

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks
  2021-02-02 22:41         ` Suzuki K Poulose
@ 2021-02-04 12:27           ` Mike Leach
  0 siblings, 0 replies; 90+ messages in thread
From: Mike Leach @ 2021-02-04 12:27 UTC (permalink / raw)
  To: Suzuki K Poulose
  Cc: Mathieu Poirier, Anshuman Khandual, linux-arm-kernel,
	Coresight ML, Linu Cherian, Linux Kernel Mailing List

Hi Suzuki,.

On Tue, 2 Feb 2021 at 22:42, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>
> On 2/2/21 4:33 PM, Mike Leach wrote:
> > Hi,
> >
> > On Tue, 2 Feb 2021 at 09:42, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
> >>
> >> On 2/1/21 11:17 PM, Mathieu Poirier wrote:
> >>> Hi Anshuman,
> >>>
> >>> I have started reviewing this set.  As it is quite voluminous comments will
> >>> come over serveral days.  I will let you know when I am done.
> >>>
> >>> On Wed, Jan 27, 2021 at 02:25:25PM +0530, Anshuman Khandual wrote:
> >>>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> >>>>
> >>>> When there are multiple sinks on the system, in the absence
> >>>> of a specified sink, it is quite possible that a default sink
> >>>> for an ETM could be different from that of another ETM. However
> >>>> we do not support having multiple sinks for an event yet. This
> >>>> patch allows the event to use the default sinks on the ETMs
> >>>> where they are scheduled as long as the sinks are of the same
> >>>> type.
> >>>>
> >>>> e.g, if we have 1x1 topology with per-CPU ETRs, the event can
> >>>> use the per-CPU ETR for the session. However, if the sinks
> >>>> are of different type, e.g TMC-ETR on one and a custom sink
> >>>> on another, the event will only trace on the first detected
> >>>> sink.
> >>>>
> >>>
> >>> I found the above changelog very confusing - I read it several times and still
> >>> couldn't get all of it.  In the end this patch prevents sinks of different types
> >>> from being used for session, and this is what the text should reflect.
> >>
> >> Sorry about that. Your inference is correct, but it is only a side effect
> >> of the primary motive. How about the following :
> >>
> >> "When a sink is not specified by the user, the etm perf driver
> >> finds a suitable sink automatically based on the first ETM, where
> >> this event could be scheduled. Then we allocate the sink buffer based
> >> on the selected sink. This is fine for a CPU bound event as the "sink"
> >> is always guaranteed to be reachable from the ETM (as this is the only
> >> ETM where the event is going to be scheduled). However, if we have a task
> >> bound event, the event could be scheduled on any of the ETMs on the
> >> system. In this case, currently we automatically select a sink and exclude
> >> any ETMs that are not reachable from the selected sink. This is
> >> problematic for 1x1 configurations as we end up in tracing the event
> >> only on the "first" ETM, as the default sink is local to the first
> >> ETM and unreachable from the rest.
> >> However, we could allow the other ETMs to trace if they all have a
> >> sink that is compatible with the "selected" sink and can use the
> >> sink buffer. This can be easily done by verifying that they are
> >> all driven by the same driver and matches the same subtype."
> >>
> >
> >
> > Not sure that the logic here makes total sense - I can't see _why_
> > multiple sinks need to be of the same type.
>
> Because we have a single "sink_config" (read, single sink specific
> buffer) for an event. i.e, we do the sink_ops->alloc_buffer() only once
> and rightly so. This allocates any buffers that is used by a given sink.
> e.g, for ETR it allocates an etr_perf_buffer. Now if we wanted the same
> event to run on an ETM with TRBE, the TRBE doesn't have any buffer set up to
> collect the trace and cant make any sense of etr_perf_buffer.
> However, if there is another ETM with a different ETR, the second
> ETR can make sense of the sink_config (etr_perf_buffer) and trace the event.
> Please remember that this only applies to task bound events where
> the event can be scheduled on different ETMs.
>

I have had a look around the ETR driver and can see the issue -
something very sink specific is being bound to the more generic event,
which does undermine the abstraction a little bit!
The ETR drivers refer to per-thread and cpu-wide - not cpu-bound /
task-bound - could do to get consistent terminology here. The cpu-wide
version is designed to be called multiple times - but obviously only
allocates a single buffer.

This implies that for the cpu-wide case, we could tolerate sinks of
differing types, as setup_aux will be called once per CPU. Whether we
want to is another question.

Given we don't yet have any systems that sport differing sink types,
its probably not worth allowing.
A short comment explaining the type matching is needed due to
underlying private data structure incompatibility would be useful
though.

Regards

Mike



> >
> > 1) This patch is designed to allow multiple sinks to be used in a 1:1
> > topology system - but there is no specific restriction here - and N:M
> > should work on the same basis
>
> Yes, this should work in any topology.
>
> > 2) This implies that multiple sinks will work within the coresight
> > infrastucture.
>
> I am afraid I don't understand the context here.
>
> > 3)  The sink interface -> struct coresight_ops_sink allows sinks to be
> > abstracted - therefore whichever sink is chosen the coresight
> > infrastructure calls the operations for the given sink.
>
> Correct. The patch is trying to ensure that a private data
> setup by one driver is not interpreted by another driver as
> its own private data. (the private data being sink_config)
>
> > 4) Each individual sink, will have its own hardware buffer - copied
> > into the perf buffers at some appropriate point.
>
> Correct. Supporting multiple types of sinks for a single event
> is complex and not worth the benefit of the extra complexity.
> Moreover we don't expect sane systems to have such a
> configuration.
>
> >
> > Thus if the users specifies a selected sink - we need to eliminate any
> > source that cannot reach it.
>
> Yes, we do that now.
>
> > If not we need to find the relevant default sink for the source, which
> > might be a shared ETR, or per CPU TRBE / ETR, and the abstraction
> > logic ought to handle getting the captured data to the correct place.
>
> The abstraction logic works fine, but the per-event private data is
> something that makes this complex.
>
> > If it doesn't then we are on shaky ground with any multiple sink
> > solution.
> >
> > On the face of it - type is irrelevant. If I am missing something -
> > this patch needs a better explanation.
>
> I hope the explanation above makes it clear. Please let me know
> otherwise.
>
> >>>> +}
> >>>> +
> >>>>    static void *etm_setup_aux(struct perf_event *event, void **pages,
> >>>>                          int nr_pages, bool overwrite)
> >>>>    {
> >>>> @@ -212,6 +219,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
> >>>>       cpumask_t *mask;
> >>>>       struct coresight_device *sink = NULL;
> >>>
> >>>           struct coresight_device *user_sink = NULL;
> >>>
> >>>>       struct etm_event_data *event_data = NULL;
> >>>> +    bool sink_forced = false;
> >>>>
> >>>>       event_data = alloc_event_data(cpu);
> >>>>       if (!event_data)
> >>>> @@ -222,6 +230,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
> >>>>       if (event->attr.config2) {
> >>>>               id = (u32)event->attr.config2;
> >>>>               sink = coresight_get_sink_by_id(id);
> >>>
> >>>                   user_sink = coresight_get_sink_by_id(id);
> >>>
> >>>> +            sink_forced = true;
> >
> > The comment for this block uses the term "selected sink", and the
> > functions use _default_sink . This may read better if we rename the
> > bool to "selected_sink" rather than "sink_forced"
>
> I have removed the bool and replaced with the user_sink as Mathieu
> suggested.
>
> Thanks for the review
> Suzuki



--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks
  2021-01-28  9:16   ` Suzuki K Poulose
@ 2021-02-04 18:34     ` Mathieu Poirier
  2021-02-16 10:40       ` Anshuman Khandual
  2021-02-16 10:21     ` Anshuman Khandual
  1 sibling, 1 reply; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-04 18:34 UTC (permalink / raw)
  To: Suzuki K Poulose
  Cc: Anshuman Khandual, linux-arm-kernel, coresight, mike.leach,
	lcherian, linux-kernel

On Thu, Jan 28, 2021 at 09:16:34AM +0000, Suzuki K Poulose wrote:
> On 1/27/21 8:55 AM, Anshuman Khandual wrote:
> > Add support for dedicated sinks that are bound to individual CPUs. (e.g,
> > TRBE). To allow quicker access to the sink for a given CPU bound source,
> > keep a percpu array of the sink devices. Also, add support for building
> > a path to the CPU local sink from the ETM.
> > 
> > This adds a new percpu sink type CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM.
> > This new sink type is exclusively available and can only work with percpu
> > source type device CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC.
> > 
> > This defines a percpu structure that accommodates a single coresight_device
> > which can be used to store an initialized instance from a sink driver. As
> > these sinks are exclusively linked and dependent on corresponding percpu
> > sources devices, they should also be the default sink device during a perf
> > session.
> > 
> > Outwards device connections are scanned while establishing paths between a
> > source and a sink device. But such connections are not present for certain
> > percpu source and sink devices which are exclusively linked and dependent.
> > Build the path directly and skip connection scanning for such devices.
> > 
> > Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Cc: Mike Leach <mike.leach@linaro.org>
> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> > ---
> > Changes in V3:
> > 
> > - Updated coresight_find_default_sink()
> > 
> >   drivers/hwtracing/coresight/coresight-core.c | 16 ++++++++++++++--
> >   include/linux/coresight.h                    | 12 ++++++++++++
> >   2 files changed, 26 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> > index 0062c89..4795e28 100644
> > --- a/drivers/hwtracing/coresight/coresight-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-core.c
> > @@ -23,6 +23,7 @@
> >   #include "coresight-priv.h"
> >   static DEFINE_MUTEX(coresight_mutex);
> > +DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
> >   /**
> >    * struct coresight_node - elements of a path, from source to sink
> > @@ -784,6 +785,13 @@ static int _coresight_build_path(struct coresight_device *csdev,
> >   	if (csdev == sink)
> >   		goto out;
> > +	if (coresight_is_percpu_source(csdev) && coresight_is_percpu_sink(sink) &&
> > +	    sink == per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev))) {
> > +		_coresight_build_path(sink, sink, path);

The return value for _coresight_build_path() needs to be checked.  Otherwise a
failure to allocate a node for the sink will go unoticed and make for a very
hard problem to debug.

> > +		found = true;
> > +		goto out;
> > +	}
> > +
> >   	/* Not a sink - recursively explore each port found on this element */
> >   	for (i = 0; i < csdev->pdata->nr_outport; i++) {
> >   		struct coresight_device *child_dev;
> > @@ -999,8 +1007,12 @@ coresight_find_default_sink(struct coresight_device *csdev)
> >   	int depth = 0;
> >   	/* look for a default sink if we have not found for this device */
> > -	if (!csdev->def_sink)
> > -		csdev->def_sink = coresight_find_sink(csdev, &depth);
> > +	if (!csdev->def_sink) {
> > +		if (coresight_is_percpu_source(csdev))
> > +			csdev->def_sink = per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev));
> > +		if (!csdev->def_sink)
> > +			csdev->def_sink = coresight_find_sink(csdev, &depth);
> > +	}
> >   	return csdev->def_sink;
> >   }
> > diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> > index 976ec26..bc3a5ca 100644
> > --- a/include/linux/coresight.h
> > +++ b/include/linux/coresight.h
> > @@ -50,6 +50,7 @@ enum coresight_dev_subtype_sink {
> >   	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
> >   	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
> >   	CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
> > +	CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,

Do we absolutely need to add a new sink type?  It is only used in
_coresight_build_path() and that code could be: 

	if (coresight_is_percpu_source(csdev)) {
	    sink == per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev));
            if (sink && sink == csdev) {
		_coresight_build_path(sink, sink, path);

> >   };
> >   enum coresight_dev_subtype_link {
> > @@ -428,6 +429,17 @@ static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 o
> >   		csa->write(val, offset, false, true);
> >   }
> > +static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
> > +{
> > +	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
> > +	       csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
> 
> Please add () around the last line. Same below.
> 
> > +}
> > +
> > +static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
> > +{
> > +	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
> > +	       csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
> > +}
> >   #else	/* !CONFIG_64BIT */
> >   static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
> > 
> 
> With the above :
> 
> Tested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-01-27  8:55 ` [PATCH V3 11/14] coresight: sink: Add TRBE driver Anshuman Khandual
       [not found]   ` <12cdc8ca-0a69-bfba-bbcd-fb392d6ca051@arm.com>
@ 2021-02-05 17:53   ` Mathieu Poirier
  2021-02-08  4:20     ` Anshuman Khandual
  2021-02-09 17:39     ` Mathieu Poirier
  2021-02-10 19:00   ` Mathieu Poirier
                     ` (2 subsequent siblings)
  4 siblings, 2 replies; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-05 17:53 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel

On Wed, Jan 27, 2021 at 02:25:35PM +0530, Anshuman Khandual wrote:
> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
> accessible via the system registers. The TRBE supports different addressing
> modes including CPU virtual address and buffer modes including the circular
> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
> access to the trace buffer could be prohibited by a higher exception level
> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
> private interrupt (PPI) on address translation errors and when the buffer
> is full. Overall implementation here is inspired from the Arm SPE driver.
>

I got this message when applying the patch: 

Applying: coresight: sink: Add TRBE driver
.git/rebase-apply/patch:76: new blank line at EOF.
+
warning: 1 line adds whitespace errors.
 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> Changes in V3:
> 
> - Added new DT bindings document TRBE.yaml
> - Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3
> - Dropped isb() from trbe_reset_local()
> - Dropped gap between (void *) and buf->trbe_base
> - Changed 'int' to 'unsigned int' in is_trbe_available()
> - Dropped unused function set_trbe_running(), set_trbe_virtual_mode(),
>   set_trbe_enabled() and set_trbe_limit_pointer()
> - Changed get_trbe_flag_update(), is_trbe_programmable() and
>   get_trbe_address_align() to accept TRBIDR value
> - Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), is_trbe_trg(),
>   is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value
> - Dropped snapshot mode condition in arm_trbe_alloc_buffer()
> - Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled
> - Compute trbe_limit before trbe_write to get the updated handle
> - Added trbe_stop_and_truncate_event()
> - Dropped trbe_handle_fatal()
> 
>  Documentation/trace/coresight/coresight-trbe.rst |   39 +
>  arch/arm64/include/asm/sysreg.h                  |    1 +
>  drivers/hwtracing/coresight/Kconfig              |   11 +
>  drivers/hwtracing/coresight/Makefile             |    1 +
>  drivers/hwtracing/coresight/coresight-trbe.c     | 1023 ++++++++++++++++++++++
>  drivers/hwtracing/coresight/coresight-trbe.h     |  160 ++++
>  6 files changed, 1235 insertions(+)
>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
> 
> diff --git a/Documentation/trace/coresight/coresight-trbe.rst b/Documentation/trace/coresight/coresight-trbe.rst
> new file mode 100644
> index 0000000..1cbb819
> --- /dev/null
> +++ b/Documentation/trace/coresight/coresight-trbe.rst
> @@ -0,0 +1,39 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +==============================
> +Trace Buffer Extension (TRBE).
> +==============================
> +
> +    :Author:   Anshuman Khandual <anshuman.khandual@arm.com>
> +    :Date:     November 2020
> +
> +Hardware Description
> +--------------------
> +
> +Trace Buffer Extension (TRBE) is a percpu hardware which captures in system
> +memory, CPU traces generated from a corresponding percpu tracing unit. This
> +gets plugged in as a coresight sink device because the corresponding trace
> +genarators (ETE), are plugged in as source device.
> +
> +The TRBE is not compliant to CoreSight architecture specifications, but is
> +driven via the CoreSight driver framework to support the ETE (which is
> +CoreSight compliant) integration.
> +
> +Sysfs files and directories
> +---------------------------
> +
> +The TRBE devices appear on the existing coresight bus alongside the other
> +coresight devices::
> +
> +	>$ ls /sys/bus/coresight/devices
> +	trbe0  trbe1  trbe2 trbe3
> +
> +The ``trbe<N>`` named TRBEs are associated with a CPU.::
> +
> +	>$ ls /sys/bus/coresight/devices/trbe0/
> +        align dbm
> +
> +*Key file items are:-*
> +   * ``align``: TRBE write pointer alignment
> +   * ``dbm``: TRBE updates memory with access and dirty flags
> +

Please add documentation for these, the same way it was done for all the other CS
components [1].

[1]. https://elixir.bootlin.com/linux/latest/source/Documentation/ABI/testing
(sysfs-bus-coresight-device-xyz)

> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 85ae4db..9e2e9b7 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -97,6 +97,7 @@
>  #define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
>  #define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
>  #define SET_PSTATE_TCO(x)		__emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
> +#define TSB_CSYNC			__emit_inst(0xd503225f)
>  
>  #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
>  #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> index f154ae7..aa657ab 100644
> --- a/drivers/hwtracing/coresight/Kconfig
> +++ b/drivers/hwtracing/coresight/Kconfig
> @@ -164,6 +164,17 @@ config CORESIGHT_CTI
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called coresight-cti.
>  
> +config CORESIGHT_TRBE
> +	bool "Trace Buffer Extension (TRBE) driver"

Shouldn't that be "tristate"?

> +	depends on ARM64

I would make it dependent on ETMv4 as well since it can only be used by that
component.

> +	help
> +	  This driver provides support for percpu Trace Buffer Extension (TRBE).
> +	  TRBE always needs to be used along with it's corresponding percpu ETE
> +	  component. ETE generates trace data which is then captured with TRBE.
> +	  Unlike traditional sink devices, TRBE is a CPU feature accessible via
> +	  system registers. But it's explicit dependency with trace unit (ETE)
> +	  requires it to be plugged in as a coresight sink device.

Please add:

          "To compile this driver as a module, choose M here: the
          module will be called coresight-trbe."

I'm out of time for today, I will continue on Monday.

Mathieu

> +
>  config CORESIGHT_CTI_INTEGRATION_REGS
>  	bool "Access CTI CoreSight Integration Registers"
>  	depends on CORESIGHT_CTI
> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
> index f20e357..d608165 100644
> --- a/drivers/hwtracing/coresight/Makefile
> +++ b/drivers/hwtracing/coresight/Makefile
> @@ -21,5 +21,6 @@ obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
>  obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
>  obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
>  obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
> +obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
>  coresight-cti-y := coresight-cti-core.o	coresight-cti-platform.o \
>  		   coresight-cti-sysfs.o
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> new file mode 100644
> index 0000000..1464d8b
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -0,0 +1,1023 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * This driver enables Trace Buffer Extension (TRBE) as a per-cpu coresight
> + * sink device could then pair with an appropriate per-cpu coresight source
> + * device (ETE) thus generating required trace data. Trace can be enabled
> + * via the perf framework.
> + *
> + * Copyright (C) 2020 ARM Ltd.
> + *
> + * Author: Anshuman Khandual <anshuman.khandual@arm.com>
> + */
> +#define DRVNAME "arm_trbe"
> +
> +#define pr_fmt(fmt) DRVNAME ": " fmt
> +
> +#include "coresight-trbe.h"
> +
> +#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
> +
> +/*
> + * A padding packet that will help the user space tools
> + * in skipping relevant sections in the captured trace
> + * data which could not be decoded. TRBE doesn't support
> + * formatting the trace data, unlike the legacy CoreSight
> + * sinks and thus we use ETE trace packets to pad the
> + * sections of the buffer.
> + */
> +#define ETE_IGNORE_PACKET 		0x70
> +
> +/*
> + * Minimum amount of meaningful trace will contain:
> + * A-Sync, Trace Info, Trace On, Address, Atom.
> + * This is about 44bytes of ETE trace. To be on
> + * the safer side, we assume 64bytes is the minimum
> + * space required for a meaningful session, before
> + * we hit a "WRAP" event.
> + */
> +#define TRBE_TRACE_MIN_BUF_SIZE		64
> +
> +enum trbe_fault_action {
> +	TRBE_FAULT_ACT_WRAP,
> +	TRBE_FAULT_ACT_SPURIOUS,
> +	TRBE_FAULT_ACT_FATAL,
> +};
> +
> +struct trbe_buf {
> +	unsigned long trbe_base;
> +	unsigned long trbe_limit;
> +	unsigned long trbe_write;
> +	int nr_pages;
> +	void **pages;
> +	bool snapshot;
> +	struct trbe_cpudata *cpudata;
> +};
> +
> +struct trbe_cpudata {
> +	bool trbe_dbm;
> +	u64 trbe_align;
> +	int cpu;
> +	enum cs_mode mode;
> +	struct trbe_buf *buf;
> +	struct trbe_drvdata *drvdata;
> +};
> +
> +struct trbe_drvdata {
> +	struct trbe_cpudata __percpu *cpudata;
> +	struct perf_output_handle __percpu **handle;
> +	struct hlist_node hotplug_node;
> +	int irq;
> +	cpumask_t supported_cpus;
> +	enum cpuhp_state trbe_online;
> +	struct platform_device *pdev;
> +};
> +
> +static int trbe_alloc_node(struct perf_event *event)
> +{
> +	if (event->cpu == -1)
> +		return NUMA_NO_NODE;
> +	return cpu_to_node(event->cpu);
> +}
> +
> +static void trbe_drain_buffer(void)
> +{
> +	asm(TSB_CSYNC);
> +	dsb(nsh);
> +}
> +
> +static void trbe_drain_and_disable_local(void)
> +{
> +	trbe_drain_buffer();
> +	write_sysreg_s(0, SYS_TRBLIMITR_EL1);
> +	isb();
> +}
> +
> +static void trbe_reset_local(void)
> +{
> +	trbe_drain_and_disable_local();
> +	write_sysreg_s(0, SYS_TRBPTR_EL1);
> +	write_sysreg_s(0, SYS_TRBBASER_EL1);
> +	write_sysreg_s(0, SYS_TRBSR_EL1);
> +}
> +
> +static void trbe_stop_and_truncate_event(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +
> +	/*
> +	 * We cannot proceed with the buffer collection and we
> +	 * do not have any data for the current session. The
> +	 * etm_perf driver expects to close out the aux_buffer
> +	 * at event_stop(). So disable the TRBE here and leave
> +	 * the update_buffer() to return a 0 size.
> +	 */
> +	trbe_drain_and_disable_local();
> +	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> +	*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
> +}
> +
> +/*
> + * TRBE Buffer Management
> + *
> + * The TRBE buffer spans from the base pointer till the limit pointer. When enabled,
> + * it starts writing trace data from the write pointer onward till the limit pointer.
> + * When the write pointer reaches the address just before the limit pointer, it gets
> + * wrapped around again to the base pointer. This is called a TRBE wrap event, which
> + * generates a maintenance interrupt when operated in WRAP or FILL mode. This driver
> + * uses FILL mode, where the TRBE stops the trace collection at wrap event. The IRQ
> + * handler updates the AUX buffer and re-enables the TRBE with updated WRITE and
> + * LIMIT pointers.
> + *
> + *	Wrap around with an IRQ
> + *	------ < ------ < ------- < ----- < -----
> + *	|					|
> + *	------ > ------ > ------- > ----- > -----
> + *
> + *	+---------------+-----------------------+
> + *	|		|			|
> + *	+---------------+-----------------------+
> + *	Base Pointer	Write Pointer		Limit Pointer
> + *
> + * The base and limit pointers always needs to be PAGE_SIZE aligned. But the write
> + * pointer can be aligned to the implementation defined TRBE trace buffer alignment
> + * as captured in trbe_cpudata->trbe_align.
> + *
> + *
> + *		head		tail		wakeup
> + *	+---------------------------------------+----- ~ ~ ------
> + *	|$$$$$$$|################|$$$$$$$$$$$$$$|		|
> + *	+---------------------------------------+----- ~ ~ ------
> + *	Base Pointer	Write Pointer		Limit Pointer
> + *
> + * The perf_output_handle indices (head, tail, wakeup) are monotonically increasing
> + * values which tracks all the driver writes and user reads from the perf auxiliary
> + * buffer. Generally [head..tail] is the area where the driver can write into unless
> + * the wakeup is behind the tail. Enabled TRBE buffer span needs to be adjusted and
> + * configured depending on the perf_output_handle indices, so that the driver does
> + * not override into areas in the perf auxiliary buffer which is being or yet to be
> + * consumed from the user space. The enabled TRBE buffer area is a moving subset of
> + * the allocated perf auxiliary buffer.
> + */
> +static void trbe_pad_buf(struct perf_output_handle *handle, int len)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	u64 head = PERF_IDX2OFF(handle->head, buf);
> +
> +	memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
> +	if (!buf->snapshot)
> +		perf_aux_output_skip(handle, len);
> +}
> +
> +static unsigned long trbe_snapshot_offset(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +
> +	/*
> +	 * The ETE trace has alignment synchronization packets allowing
> +	 * the decoder to reset in case of an overflow or corruption.
> +	 * So we can use the entire buffer for the snapshot mode.
> +	 */
> +	return buf->nr_pages * PAGE_SIZE;
> +}
> +
> +/*
> + * TRBE Limit Calculation
> + *
> + * The following markers are used to illustrate various TRBE buffer situations.
> + *
> + * $$$$ - Data area, unconsumed captured trace data, not to be overridden
> + * #### - Free area, enabled, trace will be written
> + * %%%% - Free area, disabled, trace will not be written
> + * ==== - Free area, padded with ETE_IGNORE_PACKET, trace will be skipped
> + */
> +static unsigned long __trbe_normal_offset(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	struct trbe_cpudata *cpudata = buf->cpudata;
> +	const u64 bufsize = buf->nr_pages * PAGE_SIZE;
> +	u64 limit = bufsize;
> +	u64 head, tail, wakeup;
> +
> +	head = PERF_IDX2OFF(handle->head, buf);
> +
> +	/*
> +	 *		head
> +	 *	------->|
> +	 *	|
> +	 *	head	TRBE align	tail
> +	 * +----|-------|---------------|-------+
> +	 * |$$$$|=======|###############|$$$$$$$|
> +	 * +----|-------|---------------|-------+
> +	 * trbe_base				trbe_base + nr_pages
> +	 *
> +	 * Perf aux buffer output head position can be misaligned depending on
> +	 * various factors including user space reads. In case misaligned, head
> +	 * needs to be aligned before TRBE can be configured. Pad the alignment
> +	 * gap with ETE_IGNORE_PACKET bytes that will be ignored by user tools
> +	 * and skip this section thus advancing the head.
> +	 */
> +	if (!IS_ALIGNED(head, cpudata->trbe_align)) {
> +		unsigned long delta = roundup(head, cpudata->trbe_align) - head;
> +
> +		delta = min(delta, handle->size);
> +		trbe_pad_buf(handle, delta);
> +		head = PERF_IDX2OFF(handle->head, buf);
> +	}
> +
> +	/*
> +	 *	head = tail (size = 0)
> +	 * +----|-------------------------------+
> +	 * |$$$$|$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$	|
> +	 * +----|-------------------------------+
> +	 * trbe_base				trbe_base + nr_pages
> +	 *
> +	 * Perf aux buffer does not have any space for the driver to write into.
> +	 * Just communicate trace truncation event to the user space by marking
> +	 * it with PERF_AUX_FLAG_TRUNCATED.
> +	 */
> +	if (!handle->size) {
> +		perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> +		return 0;
> +	}
> +
> +	/* Compute the tail and wakeup indices now that we've aligned head */
> +	tail = PERF_IDX2OFF(handle->head + handle->size, buf);
> +	wakeup = PERF_IDX2OFF(handle->wakeup, buf);
> +
> +	/*
> +	 * Lets calculate the buffer area which TRBE could write into. There
> +	 * are three possible scenarios here. Limit needs to be aligned with
> +	 * PAGE_SIZE per the TRBE requirement. Always avoid clobbering the
> +	 * unconsumed data.
> +	 *
> +	 * 1) head < tail
> +	 *
> +	 *	head			tail
> +	 * +----|-----------------------|-------+
> +	 * |$$$$|#######################|$$$$$$$|
> +	 * +----|-----------------------|-------+
> +	 * trbe_base			limit	trbe_base + nr_pages
> +	 *
> +	 * TRBE could write into [head..tail] area. Unless the tail is right at
> +	 * the end of the buffer, neither an wrap around nor an IRQ is expected
> +	 * while being enabled.
> +	 *
> +	 * 2) head == tail
> +	 *
> +	 *	head = tail (size > 0)
> +	 * +----|-------------------------------+
> +	 * |%%%%|###############################|
> +	 * +----|-------------------------------+
> +	 * trbe_base				limit = trbe_base + nr_pages
> +	 *
> +	 * TRBE should just write into [head..base + nr_pages] area even though
> +	 * the entire buffer is empty. Reason being, when the trace reaches the
> +	 * end of the buffer, it will just wrap around with an IRQ giving an
> +	 * opportunity to reconfigure the buffer.
> +	 *
> +	 * 3) tail < head
> +	 *
> +	 *	tail			head
> +	 * +----|-----------------------|-------+
> +	 * |%%%%|$$$$$$$$$$$$$$$$$$$$$$$|#######|
> +	 * +----|-----------------------|-------+
> +	 * trbe_base				limit = trbe_base + nr_pages
> +	 *
> +	 * TRBE should just write into [head..base + nr_pages] area even though
> +	 * the [trbe_base..tail] is also empty. Reason being, when the trace
> +	 * reaches the end of the buffer, it will just wrap around with an IRQ
> +	 * giving an opportunity to reconfigure the buffer.
> +	 */
> +	if (head < tail)
> +		limit = round_down(tail, PAGE_SIZE);
> +
> +	/*
> +	 * Wakeup may be arbitrarily far into the future. If it's not in the
> +	 * current generation, either we'll wrap before hitting it, or it's
> +	 * in the past and has been handled already.
> +	 *
> +	 * If there's a wakeup before we wrap, arrange to be woken up by the
> +	 * page boundary following it. Keep the tail boundary if that's lower.
> +	 *
> +	 *	head		wakeup	tail
> +	 * +----|---------------|-------|-------+
> +	 * |$$$$|###############|%%%%%%%|$$$$$$$|
> +	 * +----|---------------|-------|-------+
> +	 * trbe_base		limit		trbe_base + nr_pages
> +	 */
> +	if (handle->wakeup < (handle->head + handle->size) && head <= wakeup)
> +		limit = min(limit, round_up(wakeup, PAGE_SIZE));
> +
> +	/*
> +	 * There are two situation when this can happen i.e limit is before
> +	 * the head and hence TRBE cannot be configured.
> +	 *
> +	 * 1) head < tail (aligned down with PAGE_SIZE) and also they are both
> +	 * within the same PAGE size range.
> +	 *
> +	 *			PAGE_SIZE
> +	 *		|----------------------|
> +	 *
> +	 *		limit	head	tail
> +	 * +------------|------|--------|-------+
> +	 * |$$$$$$$$$$$$$$$$$$$|========|$$$$$$$|
> +	 * +------------|------|--------|-------+
> +	 * trbe_base				trbe_base + nr_pages
> +	 *
> +	 * 2) head < wakeup (aligned up with PAGE_SIZE) < tail and also both
> +	 * head and wakeup are within same PAGE size range.
> +	 *
> +	 *		PAGE_SIZE
> +	 *	|----------------------|
> +	 *
> +	 *	limit	head	wakeup  tail
> +	 * +----|------|-------|--------|-------+
> +	 * |$$$$$$$$$$$|=======|========|$$$$$$$|
> +	 * +----|------|-------|--------|-------+
> +	 * trbe_base				trbe_base + nr_pages
> +	 */
> +	if (limit > head)
> +		return limit;
> +
> +	trbe_pad_buf(handle, handle->size);
> +	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> +	return 0;
> +}
> +
> +static unsigned long trbe_normal_offset(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = perf_get_aux(handle);
> +	u64 limit = __trbe_normal_offset(handle);
> +	u64 head = PERF_IDX2OFF(handle->head, buf);
> +
> +	/*
> +	 * If the head is too close to the limit and we don't
> +	 * have space for a meaningful run, we rather pad it
> +	 * and start fresh.
> +	 */
> +	if (limit && (limit - head < TRBE_TRACE_MIN_BUF_SIZE)) {
> +		trbe_pad_buf(handle, limit - head);
> +		limit = __trbe_normal_offset(handle);
> +	}
> +	return limit;
> +}
> +
> +static unsigned long compute_trbe_buffer_limit(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	unsigned long offset;
> +
> +	if (buf->snapshot)
> +		offset = trbe_snapshot_offset(handle);
> +	else
> +		offset = trbe_normal_offset(handle);
> +	return buf->trbe_base + offset;
> +}
> +
> +static void clr_trbe_status(void)
> +{
> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
> +
> +	WARN_ON(is_trbe_enabled());
> +	trbsr &= ~TRBSR_IRQ;
> +	trbsr &= ~TRBSR_TRG;
> +	trbsr &= ~TRBSR_WRAP;
> +	trbsr &= ~(TRBSR_EC_MASK << TRBSR_EC_SHIFT);
> +	trbsr &= ~(TRBSR_BSC_MASK << TRBSR_BSC_SHIFT);
> +	trbsr &= ~TRBSR_STOP;
> +	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
> +}
> +
> +static void set_trbe_limit_pointer_enabled(unsigned long addr)
> +{
> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> +
> +	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> +
> +	trblimitr &= ~TRBLIMITR_NVM;
> +	trblimitr &= ~(TRBLIMITR_FILL_MODE_MASK << TRBLIMITR_FILL_MODE_SHIFT);
> +	trblimitr &= ~(TRBLIMITR_TRIG_MODE_MASK << TRBLIMITR_TRIG_MODE_SHIFT);
> +	trblimitr &= ~(TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT);
> +
> +	/*
> +	 * Fill trace buffer mode is used here while configuring the
> +	 * TRBE for trace capture. In this particular mode, the trace
> +	 * collection is stopped and a maintenance interrupt is raised
> +	 * when the current write pointer wraps. This pause in trace
> +	 * collection gives the software an opportunity to capture the
> +	 * trace data in the interrupt handler, before reconfiguring
> +	 * the TRBE.
> +	 */
> +	trblimitr |= (TRBE_FILL_MODE_FILL & TRBLIMITR_FILL_MODE_MASK) << TRBLIMITR_FILL_MODE_SHIFT;
> +
> +	/*
> +	 * Trigger mode is not used here while configuring the TRBE for
> +	 * the trace capture. Hence just keep this in the ignore mode.
> +	 */
> +	trblimitr |= (TRBE_TRIG_MODE_IGNORE & TRBLIMITR_TRIG_MODE_MASK) << TRBLIMITR_TRIG_MODE_SHIFT;
> +	trblimitr |= (addr & PAGE_MASK);
> +
> +	trblimitr |= TRBLIMITR_ENABLE;
> +	write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
> +}
> +
> +static void trbe_enable_hw(struct trbe_buf *buf)
> +{
> +	WARN_ON(buf->trbe_write < buf->trbe_base);
> +	WARN_ON(buf->trbe_write >= buf->trbe_limit);
> +	set_trbe_disabled();
> +	isb();
> +	clr_trbe_status();
> +	set_trbe_base_pointer(buf->trbe_base);
> +	set_trbe_write_pointer(buf->trbe_write);
> +
> +	/*
> +	 * Synchronize all the register updates
> +	 * till now before enabling the TRBE.
> +	 */
> +	isb();
> +	set_trbe_limit_pointer_enabled(buf->trbe_limit);
> +
> +	/* Synchronize the TRBE enable event */
> +	isb();
> +}
> +
> +static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
> +				   struct perf_event *event, void **pages,
> +				   int nr_pages, bool snapshot)
> +{
> +	struct trbe_buf *buf;
> +	struct page **pglist;
> +	int i;
> +
> +	/*
> +	 * TRBE LIMIT and TRBE WRITE pointers must be page aligned. But with
> +	 * just a single page, there is not much room left while writing into
> +	 * a partially filled TRBE buffer. Hence restrict the minimum buffer
> +	 * size as two pages.
> +	 */
> +	if (nr_pages < 2)
> +		return NULL;
> +
> +	buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
> +	if (IS_ERR(buf))
> +		return ERR_PTR(-ENOMEM);
> +
> +	pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
> +	if (IS_ERR(pglist)) {
> +		kfree(buf);
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	for (i = 0; i < nr_pages; i++)
> +		pglist[i] = virt_to_page(pages[i]);
> +
> +	buf->trbe_base = (unsigned long) vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
> +	if (IS_ERR((void *)buf->trbe_base)) {
> +		kfree(pglist);
> +		kfree(buf);
> +		return ERR_PTR(buf->trbe_base);
> +	}
> +	buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
> +	buf->trbe_write = buf->trbe_base;
> +	buf->snapshot = snapshot;
> +	buf->nr_pages = nr_pages;
> +	buf->pages = pages;
> +	kfree(pglist);
> +	return buf;
> +}
> +
> +void arm_trbe_free_buffer(void *config)
> +{
> +	struct trbe_buf *buf = config;
> +
> +	vunmap((void *)buf->trbe_base);
> +	kfree(buf);
> +}
> +
> +static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
> +					    struct perf_output_handle *handle,
> +					    void *config)
> +{
> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> +	struct trbe_buf *buf = config;
> +	unsigned long size, offset;
> +
> +	WARN_ON(buf->cpudata != cpudata);
> +	WARN_ON(cpudata->cpu != smp_processor_id());
> +	WARN_ON(cpudata->drvdata != drvdata);
> +	if (cpudata->mode != CS_MODE_PERF)
> +		return -EINVAL;
> +
> +	/*
> +	 * If the TRBE was disabled due to lack of space in the AUX buffer or a
> +	 * spurious fault, the driver leaves it disabled, truncating the buffer.
> +	 * Since the etm_perf driver expects to close out the AUX buffer, the
> +	 * driver skips it. Thus, just pass in 0 size here to indicate that the
> +	 * buffer was truncated.
> +	 */
> +	if (!is_trbe_enabled())
> +		return 0;
> +	/*
> +	 * perf handle structure needs to be shared with the TRBE IRQ handler for
> +	 * capturing trace data and restarting the handle. There is a probability
> +	 * of an undefined reference based crash when etm event is being stopped
> +	 * while a TRBE IRQ also getting processed. This happens due the release
> +	 * of perf handle via perf_aux_output_end() in etm_event_stop(). Stopping
> +	 * the TRBE here will ensure that no IRQ could be generated when the perf
> +	 * handle gets freed in etm_event_stop().
> +	 */
> +	trbe_drain_and_disable_local();
> +	offset = get_trbe_write_pointer() - get_trbe_base_pointer();
> +	size = offset - PERF_IDX2OFF(handle->head, buf);
> +	if (buf->snapshot)
> +		handle->head += size;
> +	return size;
> +}
> +
> +static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)
> +{
> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> +	struct perf_output_handle *handle = data;
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +
> +	WARN_ON(cpudata->cpu != smp_processor_id());
> +	WARN_ON(cpudata->drvdata != drvdata);
> +	if (mode != CS_MODE_PERF)
> +		return -EINVAL;
> +
> +	*this_cpu_ptr(drvdata->handle) = handle;
> +	cpudata->buf = buf;
> +	cpudata->mode = mode;
> +	buf->cpudata = cpudata;
> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> +	if (buf->trbe_limit == buf->trbe_base) {
> +		trbe_stop_and_truncate_event(handle);
> +		return 0;
> +	}
> +	trbe_enable_hw(buf);
> +	return 0;
> +}
> +
> +static int arm_trbe_disable(struct coresight_device *csdev)
> +{
> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> +	struct trbe_buf *buf = cpudata->buf;
> +
> +	WARN_ON(buf->cpudata != cpudata);
> +	WARN_ON(cpudata->cpu != smp_processor_id());
> +	WARN_ON(cpudata->drvdata != drvdata);
> +	if (cpudata->mode != CS_MODE_PERF)
> +		return -EINVAL;
> +
> +	trbe_drain_and_disable_local();
> +	buf->cpudata = NULL;
> +	cpudata->buf = NULL;
> +	cpudata->mode = CS_MODE_DISABLED;
> +	return 0;
> +}
> +
> +static void trbe_handle_spurious(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +
> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> +	if (buf->trbe_limit == buf->trbe_base) {
> +		trbe_drain_and_disable_local();
> +		return;
> +	}
> +	trbe_enable_hw(buf);
> +}
> +
> +static void trbe_handle_overflow(struct perf_output_handle *handle)
> +{
> +	struct perf_event *event = handle->event;
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	unsigned long offset, size;
> +	struct etm_event_data *event_data;
> +
> +	offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
> +	size = offset - PERF_IDX2OFF(handle->head, buf);
> +	if (buf->snapshot)
> +		handle->head = offset;
> +	perf_aux_output_end(handle, size);
> +
> +	event_data = perf_aux_output_begin(handle, event);
> +	if (!event_data) {
> +		trbe_drain_and_disable_local();
> +		*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
> +		return;
> +	}
> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> +	if (buf->trbe_limit == buf->trbe_base) {
> +		trbe_stop_and_truncate_event(handle);
> +		return;
> +	}
> +	*this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;
> +	trbe_enable_hw(buf);
> +}
> +
> +static bool is_perf_trbe(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	struct trbe_cpudata *cpudata = buf->cpudata;
> +	struct trbe_drvdata *drvdata = cpudata->drvdata;
> +	int cpu = smp_processor_id();
> +
> +	WARN_ON(buf->trbe_base != get_trbe_base_pointer());
> +	WARN_ON(buf->trbe_limit != get_trbe_limit_pointer());
> +
> +	if (cpudata->mode != CS_MODE_PERF)
> +		return false;
> +
> +	if (cpudata->cpu != cpu)
> +		return false;
> +
> +	if (!cpumask_test_cpu(cpu, &drvdata->supported_cpus))
> +		return false;
> +
> +	return true;
> +}
> +
> +static enum trbe_fault_action trbe_get_fault_act(struct perf_output_handle *handle)
> +{
> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
> +	int ec = get_trbe_ec(trbsr);
> +	int bsc = get_trbe_bsc(trbsr);
> +
> +	WARN_ON(is_trbe_running(trbsr));
> +	if (is_trbe_trg(trbsr) || is_trbe_abort(trbsr))
> +		return TRBE_FAULT_ACT_FATAL;
> +
> +	if ((ec == TRBE_EC_STAGE1_ABORT) || (ec == TRBE_EC_STAGE2_ABORT))
> +		return TRBE_FAULT_ACT_FATAL;
> +
> +	if (is_trbe_wrap(trbsr) && (ec == TRBE_EC_OTHERS) && (bsc == TRBE_BSC_FILLED)) {
> +		if (get_trbe_write_pointer() == get_trbe_base_pointer())
> +			return TRBE_FAULT_ACT_WRAP;
> +	}
> +	return TRBE_FAULT_ACT_SPURIOUS;
> +}
> +
> +static irqreturn_t arm_trbe_irq_handler(int irq, void *dev)
> +{
> +	struct perf_output_handle **handle_ptr = dev;
> +	struct perf_output_handle *handle = *handle_ptr;
> +	enum trbe_fault_action act;
> +
> +	WARN_ON(!is_trbe_irq(read_sysreg_s(SYS_TRBSR_EL1)));
> +	clr_trbe_irq();
> +
> +	/*
> +	 * Ensure the trace is visible to the CPUs and
> +	 * any external aborts have been resolved.
> +	 */
> +	trbe_drain_buffer();
> +	isb();
> +
> +	if (!perf_get_aux(handle))
> +		return IRQ_NONE;
> +
> +	if (!is_perf_trbe(handle))
> +		return IRQ_NONE;
> +
> +	irq_work_run();
> +
> +	act = trbe_get_fault_act(handle);
> +	switch (act) {
> +	case TRBE_FAULT_ACT_WRAP:
> +		trbe_handle_overflow(handle);
> +		break;
> +	case TRBE_FAULT_ACT_SPURIOUS:
> +		trbe_handle_spurious(handle);
> +		break;
> +	case TRBE_FAULT_ACT_FATAL:
> +		trbe_stop_and_truncate_event(handle);
> +		break;
> +	}
> +	return IRQ_HANDLED;
> +}
> +
> +static const struct coresight_ops_sink arm_trbe_sink_ops = {
> +	.enable		= arm_trbe_enable,
> +	.disable	= arm_trbe_disable,
> +	.alloc_buffer	= arm_trbe_alloc_buffer,
> +	.free_buffer	= arm_trbe_free_buffer,
> +	.update_buffer	= arm_trbe_update_buffer,
> +};
> +
> +static const struct coresight_ops arm_trbe_cs_ops = {
> +	.sink_ops	= &arm_trbe_sink_ops,
> +};
> +
> +static ssize_t align_show(struct device *dev, struct device_attribute *attr, char *buf)
> +{
> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
> +
> +	return sprintf(buf, "%llx\n", cpudata->trbe_align);
> +}
> +static DEVICE_ATTR_RO(align);
> +
> +static ssize_t dbm_show(struct device *dev, struct device_attribute *attr, char *buf)
> +{
> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
> +
> +	return sprintf(buf, "%d\n", cpudata->trbe_dbm);
> +}
> +static DEVICE_ATTR_RO(dbm);
> +
> +static struct attribute *arm_trbe_attrs[] = {
> +	&dev_attr_align.attr,
> +	&dev_attr_dbm.attr,
> +	NULL,
> +};
> +
> +static const struct attribute_group arm_trbe_group = {
> +	.attrs = arm_trbe_attrs,
> +};
> +
> +static const struct attribute_group *arm_trbe_groups[] = {
> +	&arm_trbe_group,
> +	NULL,
> +};
> +
> +static void arm_trbe_probe_coresight_cpu(void *info)
> +{
> +	struct trbe_drvdata *drvdata = info;
> +	struct coresight_desc desc = { 0 };
> +	int cpu = smp_processor_id();
> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
> +	u64 trbidr = read_sysreg_s(SYS_TRBIDR_EL1);
> +	struct device *dev;
> +
> +	if (WARN_ON(!cpudata))
> +		goto cpu_clear;
> +
> +	if (trbe_csdev)
> +		return;
> +
> +	cpudata->cpu = smp_processor_id();
> +	cpudata->drvdata = drvdata;
> +	dev = &cpudata->drvdata->pdev->dev;
> +
> +	if (!is_trbe_available()) {
> +		pr_err("TRBE is not implemented on cpu %d\n", cpudata->cpu);
> +		goto cpu_clear;
> +	}
> +
> +	if (!is_trbe_programmable(trbidr)) {
> +		pr_err("TRBE is owned in higher exception level on cpu %d\n", cpudata->cpu);
> +		goto cpu_clear;
> +	}
> +	desc.name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", DRVNAME, smp_processor_id());
> +	if (IS_ERR(desc.name))
> +		goto cpu_clear;
> +
> +	desc.type = CORESIGHT_DEV_TYPE_SINK;
> +	desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
> +	desc.ops = &arm_trbe_cs_ops;
> +	desc.pdata = dev_get_platdata(dev);
> +	desc.groups = arm_trbe_groups;
> +	desc.dev = dev;
> +	trbe_csdev = coresight_register(&desc);
> +	if (IS_ERR(trbe_csdev))
> +		goto cpu_clear;
> +
> +	dev_set_drvdata(&trbe_csdev->dev, cpudata);
> +	cpudata->trbe_dbm = get_trbe_flag_update(trbidr);
> +	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
> +	if (cpudata->trbe_align > SZ_2K) {
> +		pr_err("Unsupported alignment on cpu %d\n", cpudata->cpu);
> +		goto cpu_clear;
> +	}
> +	per_cpu(csdev_sink, cpu) = trbe_csdev;
> +	trbe_reset_local();
> +	enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
> +	return;
> +cpu_clear:
> +	cpumask_clear_cpu(cpudata->cpu, &cpudata->drvdata->supported_cpus);
> +}
> +
> +static void arm_trbe_remove_coresight_cpu(void *info)
> +{
> +	int cpu = smp_processor_id();
> +	struct trbe_drvdata *drvdata = info;
> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
> +
> +	if (trbe_csdev) {
> +		coresight_unregister(trbe_csdev);
> +		cpudata->drvdata = NULL;
> +		per_cpu(csdev_sink, cpu) = NULL;
> +	}
> +	disable_percpu_irq(drvdata->irq);
> +	trbe_reset_local();
> +}
> +
> +static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata)
> +{
> +	drvdata->cpudata = alloc_percpu(typeof(*drvdata->cpudata));
> +	if (IS_ERR(drvdata->cpudata))
> +		return PTR_ERR(drvdata->cpudata);
> +
> +	arm_trbe_probe_coresight_cpu(drvdata);
> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_probe_coresight_cpu, drvdata, 1);
> +	return 0;
> +}
> +
> +static int arm_trbe_remove_coresight(struct trbe_drvdata *drvdata)
> +{
> +	arm_trbe_remove_coresight_cpu(drvdata);
> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_remove_coresight_cpu, drvdata, 1);
> +	free_percpu(drvdata->cpudata);
> +	return 0;
> +}
> +
> +static int arm_trbe_cpu_startup(unsigned int cpu, struct hlist_node *node)
> +{
> +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
> +
> +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
> +		if (!per_cpu(csdev_sink, cpu)) {
> +			arm_trbe_probe_coresight_cpu(drvdata);
> +		} else {
> +			trbe_reset_local();
> +			enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
> +		}
> +	}
> +	return 0;
> +}
> +
> +static int arm_trbe_cpu_teardown(unsigned int cpu, struct hlist_node *node)
> +{
> +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
> +
> +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
> +		disable_percpu_irq(drvdata->irq);
> +		trbe_reset_local();
> +	}
> +	return 0;
> +}
> +
> +static int arm_trbe_probe_cpuhp(struct trbe_drvdata *drvdata)
> +{
> +	enum cpuhp_state trbe_online;
> +
> +	trbe_online = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
> +					arm_trbe_cpu_startup, arm_trbe_cpu_teardown);
> +	if (trbe_online < 0)
> +		return -EINVAL;
> +
> +	if (cpuhp_state_add_instance(trbe_online, &drvdata->hotplug_node))
> +		return -EINVAL;
> +
> +	drvdata->trbe_online = trbe_online;
> +	return 0;
> +}
> +
> +static void arm_trbe_remove_cpuhp(struct trbe_drvdata *drvdata)
> +{
> +	cpuhp_remove_multi_state(drvdata->trbe_online);
> +}
> +
> +static int arm_trbe_probe_irq(struct platform_device *pdev,
> +			      struct trbe_drvdata *drvdata)
> +{
> +	drvdata->irq = platform_get_irq(pdev, 0);
> +	if (!drvdata->irq) {
> +		pr_err("IRQ not found for the platform device\n");
> +		return -ENXIO;
> +	}
> +
> +	if (!irq_is_percpu(drvdata->irq)) {
> +		pr_err("IRQ is not a PPI\n");
> +		return -EINVAL;
> +	}
> +
> +	if (irq_get_percpu_devid_partition(drvdata->irq, &drvdata->supported_cpus))
> +		return -EINVAL;
> +
> +	drvdata->handle = alloc_percpu(typeof(*drvdata->handle));
> +	if (!drvdata->handle)
> +		return -ENOMEM;
> +
> +	if (request_percpu_irq(drvdata->irq, arm_trbe_irq_handler, DRVNAME, drvdata->handle)) {
> +		free_percpu(drvdata->handle);
> +		return -EINVAL;
> +	}
> +	return 0;
> +}
> +
> +static void arm_trbe_remove_irq(struct trbe_drvdata *drvdata)
> +{
> +	free_percpu_irq(drvdata->irq, drvdata->handle);
> +	free_percpu(drvdata->handle);
> +}
> +
> +static int arm_trbe_device_probe(struct platform_device *pdev)
> +{
> +	struct coresight_platform_data *pdata;
> +	struct trbe_drvdata *drvdata;
> +	struct device *dev = &pdev->dev;
> +	int ret;
> +
> +	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> +	if (IS_ERR(drvdata))
> +		return -ENOMEM;
> +
> +	pdata = coresight_get_platform_data(dev);
> +	if (IS_ERR(pdata)) {
> +		kfree(drvdata);
> +		return -ENOMEM;
> +	}
> +
> +	dev_set_drvdata(dev, drvdata);
> +	dev->platform_data = pdata;
> +	drvdata->pdev = pdev;
> +	ret = arm_trbe_probe_irq(pdev, drvdata);
> +	if (ret)
> +		goto irq_failed;
> +
> +	ret = arm_trbe_probe_coresight(drvdata);
> +	if (ret)
> +		goto probe_failed;
> +
> +	ret = arm_trbe_probe_cpuhp(drvdata);
> +	if (ret)
> +		goto cpuhp_failed;
> +
> +	return 0;
> +cpuhp_failed:
> +	arm_trbe_remove_coresight(drvdata);
> +probe_failed:
> +	arm_trbe_remove_irq(drvdata);
> +irq_failed:
> +	kfree(pdata);
> +	kfree(drvdata);
> +	return ret;
> +}
> +
> +static int arm_trbe_device_remove(struct platform_device *pdev)
> +{
> +	struct coresight_platform_data *pdata = dev_get_platdata(&pdev->dev);
> +	struct trbe_drvdata *drvdata = platform_get_drvdata(pdev);
> +
> +	arm_trbe_remove_coresight(drvdata);
> +	arm_trbe_remove_cpuhp(drvdata);
> +	arm_trbe_remove_irq(drvdata);
> +	kfree(pdata);
> +	kfree(drvdata);
> +	return 0;
> +}
> +
> +static const struct of_device_id arm_trbe_of_match[] = {
> +	{ .compatible = "arm,trace-buffer-extension"},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, arm_trbe_of_match);
> +
> +static struct platform_driver arm_trbe_driver = {
> +	.driver	= {
> +		.name = DRVNAME,
> +		.of_match_table = of_match_ptr(arm_trbe_of_match),
> +		.suppress_bind_attrs = true,
> +	},
> +	.probe	= arm_trbe_device_probe,
> +	.remove	= arm_trbe_device_remove,
> +};
> +
> +static int __init arm_trbe_init(void)
> +{
> +	int ret;
> +
> +	if (arm64_kernel_unmapped_at_el0()) {
> +		pr_err("TRBE wouldn't work if kernel gets unmapped at EL0\n");
> +		return -EOPNOTSUPP;
> +	}
> +
> +	ret = platform_driver_register(&arm_trbe_driver);
> +	if (!ret)
> +		return 0;
> +
> +	pr_err("Error registering %s platform driver\n", DRVNAME);
> +	return ret;
> +}
> +
> +static void __exit arm_trbe_exit(void)
> +{
> +	platform_driver_unregister(&arm_trbe_driver);
> +}
> +module_init(arm_trbe_init);
> +module_exit(arm_trbe_exit);
> +
> +MODULE_AUTHOR("Anshuman Khandual <anshuman.khandual@arm.com>");
> +MODULE_DESCRIPTION("Arm Trace Buffer Extension (TRBE) driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h
> new file mode 100644
> index 0000000..43308bc
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-trbe.h
> @@ -0,0 +1,160 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This contains all required hardware related helper functions for
> + * Trace Buffer Extension (TRBE) driver in the coresight framework.
> + *
> + * Copyright (C) 2020 ARM Ltd.
> + *
> + * Author: Anshuman Khandual <anshuman.khandual@arm.com>
> + */
> +#include <linux/coresight.h>
> +#include <linux/device.h>
> +#include <linux/irq.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/smp.h>
> +
> +#include "coresight-etm-perf.h"
> +
> +DECLARE_PER_CPU(struct coresight_device *, csdev_sink);
> +
> +static inline bool is_trbe_available(void)
> +{
> +	u64 aa64dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
> +	unsigned int trbe = cpuid_feature_extract_unsigned_field(aa64dfr0, ID_AA64DFR0_TRBE_SHIFT);
> +
> +	return trbe >= 0b0001;
> +}
> +
> +static inline bool is_trbe_enabled(void)
> +{
> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> +
> +	return trblimitr & TRBLIMITR_ENABLE;
> +}
> +
> +#define TRBE_EC_OTHERS		0
> +#define TRBE_EC_STAGE1_ABORT	36
> +#define TRBE_EC_STAGE2_ABORT	37
> +
> +static inline int get_trbe_ec(u64 trbsr)
> +{
> +	return (trbsr >> TRBSR_EC_SHIFT) & TRBSR_EC_MASK;
> +}
> +
> +#define TRBE_BSC_NOT_STOPPED	0
> +#define	TRBE_BSC_FILLED		1
> +#define TRBE_BSC_TRIGGERED	2
> +
> +static inline int get_trbe_bsc(u64 trbsr)
> +{
> +	return (trbsr >> TRBSR_BSC_SHIFT) & TRBSR_BSC_MASK;
> +}
> +
> +static inline void clr_trbe_irq(void)
> +{
> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
> +
> +	trbsr &= ~TRBSR_IRQ;
> +	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
> +}
> +
> +static inline bool is_trbe_irq(u64 trbsr)
> +{
> +	return trbsr & TRBSR_IRQ;
> +}
> +
> +static inline bool is_trbe_trg(u64 trbsr)
> +{
> +	return trbsr & TRBSR_TRG;
> +}
> +
> +static inline bool is_trbe_wrap(u64 trbsr)
> +{
> +	return trbsr & TRBSR_WRAP;
> +}
> +
> +static inline bool is_trbe_abort(u64 trbsr)
> +{
> +	return trbsr & TRBSR_ABORT;
> +}
> +
> +static inline bool is_trbe_running(u64 trbsr)
> +{
> +	return !(trbsr & TRBSR_STOP);
> +}
> +
> +#define TRBE_TRIG_MODE_STOP		0
> +#define TRBE_TRIG_MODE_IRQ		1
> +#define TRBE_TRIG_MODE_IGNORE		3
> +
> +#define TRBE_FILL_MODE_FILL		0
> +#define TRBE_FILL_MODE_WRAP		1
> +#define TRBE_FILL_MODE_CIRCULAR_BUFFER	3
> +
> +static inline void set_trbe_disabled(void)
> +{
> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> +
> +	trblimitr &= ~TRBLIMITR_ENABLE;
> +	write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
> +}
> +
> +static inline bool get_trbe_flag_update(u64 trbidr)
> +{
> +	return trbidr & TRBIDR_FLAG;
> +}
> +
> +static inline bool is_trbe_programmable(u64 trbidr)
> +{
> +	return !(trbidr & TRBIDR_PROG);
> +}
> +
> +static inline int get_trbe_address_align(u64 trbidr)
> +{
> +	return (trbidr >> TRBIDR_ALIGN_SHIFT) & TRBIDR_ALIGN_MASK;
> +}
> +
> +static inline unsigned long get_trbe_write_pointer(void)
> +{
> +	u64 trbptr = read_sysreg_s(SYS_TRBPTR_EL1);
> +	unsigned long addr = (trbptr >> TRBPTR_PTR_SHIFT) & TRBPTR_PTR_MASK;
> +
> +	return addr;
> +}
> +
> +static inline void set_trbe_write_pointer(unsigned long addr)
> +{
> +	WARN_ON(is_trbe_enabled());
> +	addr = (addr >> TRBPTR_PTR_SHIFT) & TRBPTR_PTR_MASK;
> +	write_sysreg_s(addr, SYS_TRBPTR_EL1);
> +}
> +
> +static inline unsigned long get_trbe_limit_pointer(void)
> +{
> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> +	unsigned long limit = (trblimitr >> TRBLIMITR_LIMIT_SHIFT) & TRBLIMITR_LIMIT_MASK;
> +	unsigned long addr = limit << TRBLIMITR_LIMIT_SHIFT;
> +
> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> +	return addr;
> +}
> +
> +static inline unsigned long get_trbe_base_pointer(void)
> +{
> +	u64 trbbaser = read_sysreg_s(SYS_TRBBASER_EL1);
> +	unsigned long addr = (trbbaser >> TRBBASER_BASE_SHIFT) & TRBBASER_BASE_MASK;
> +
> +	addr = addr << TRBBASER_BASE_SHIFT;
> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> +	return addr;
> +}
> +
> +static inline void set_trbe_base_pointer(unsigned long addr)
> +{
> +	WARN_ON(is_trbe_enabled());
> +	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> +	write_sysreg_s(addr, SYS_TRBBASER_EL1);
> +}
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-02-05 17:53   ` Mathieu Poirier
@ 2021-02-08  4:20     ` Anshuman Khandual
  2021-02-09 17:39     ` Mathieu Poirier
  1 sibling, 0 replies; 90+ messages in thread
From: Anshuman Khandual @ 2021-02-08  4:20 UTC (permalink / raw)
  To: Mathieu Poirier
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel



On 2/5/21 11:23 PM, Mathieu Poirier wrote:
> On Wed, Jan 27, 2021 at 02:25:35PM +0530, Anshuman Khandual wrote:
>> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
>> accessible via the system registers. The TRBE supports different addressing
>> modes including CPU virtual address and buffer modes including the circular
>> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
>> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
>> access to the trace buffer could be prohibited by a higher exception level
>> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
>> private interrupt (PPI) on address translation errors and when the buffer
>> is full. Overall implementation here is inspired from the Arm SPE driver.
>>
> 
> I got this message when applying the patch: 
> 
> Applying: coresight: sink: Add TRBE driver
> .git/rebase-apply/patch:76: new blank line at EOF.
> +
> warning: 1 line adds whitespace errors.

It could be the additional blank line at the end of documentation file
i.e Documentation/trace/coresight/coresight-trbe.rst, will drop it.
 
>  
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> Changes in V3:
>>
>> - Added new DT bindings document TRBE.yaml
>> - Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3
>> - Dropped isb() from trbe_reset_local()
>> - Dropped gap between (void *) and buf->trbe_base
>> - Changed 'int' to 'unsigned int' in is_trbe_available()
>> - Dropped unused function set_trbe_running(), set_trbe_virtual_mode(),
>>   set_trbe_enabled() and set_trbe_limit_pointer()
>> - Changed get_trbe_flag_update(), is_trbe_programmable() and
>>   get_trbe_address_align() to accept TRBIDR value
>> - Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), is_trbe_trg(),
>>   is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value
>> - Dropped snapshot mode condition in arm_trbe_alloc_buffer()
>> - Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled
>> - Compute trbe_limit before trbe_write to get the updated handle
>> - Added trbe_stop_and_truncate_event()
>> - Dropped trbe_handle_fatal()
>>
>>  Documentation/trace/coresight/coresight-trbe.rst |   39 +
>>  arch/arm64/include/asm/sysreg.h                  |    1 +
>>  drivers/hwtracing/coresight/Kconfig              |   11 +
>>  drivers/hwtracing/coresight/Makefile             |    1 +
>>  drivers/hwtracing/coresight/coresight-trbe.c     | 1023 ++++++++++++++++++++++
>>  drivers/hwtracing/coresight/coresight-trbe.h     |  160 ++++
>>  6 files changed, 1235 insertions(+)
>>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
>>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
>>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
>>
>> diff --git a/Documentation/trace/coresight/coresight-trbe.rst b/Documentation/trace/coresight/coresight-trbe.rst
>> new file mode 100644
>> index 0000000..1cbb819
>> --- /dev/null
>> +++ b/Documentation/trace/coresight/coresight-trbe.rst
>> @@ -0,0 +1,39 @@
>> +.. SPDX-License-Identifier: GPL-2.0
>> +
>> +==============================
>> +Trace Buffer Extension (TRBE).
>> +==============================
>> +
>> +    :Author:   Anshuman Khandual <anshuman.khandual@arm.com>
>> +    :Date:     November 2020
>> +
>> +Hardware Description
>> +--------------------
>> +
>> +Trace Buffer Extension (TRBE) is a percpu hardware which captures in system
>> +memory, CPU traces generated from a corresponding percpu tracing unit. This
>> +gets plugged in as a coresight sink device because the corresponding trace
>> +genarators (ETE), are plugged in as source device.
>> +
>> +The TRBE is not compliant to CoreSight architecture specifications, but is
>> +driven via the CoreSight driver framework to support the ETE (which is
>> +CoreSight compliant) integration.
>> +
>> +Sysfs files and directories
>> +---------------------------
>> +
>> +The TRBE devices appear on the existing coresight bus alongside the other
>> +coresight devices::
>> +
>> +	>$ ls /sys/bus/coresight/devices
>> +	trbe0  trbe1  trbe2 trbe3
>> +
>> +The ``trbe<N>`` named TRBEs are associated with a CPU.::
>> +
>> +	>$ ls /sys/bus/coresight/devices/trbe0/
>> +        align dbm
>> +
>> +*Key file items are:-*
>> +   * ``align``: TRBE write pointer alignment
>> +   * ``dbm``: TRBE updates memory with access and dirty flags
>> +
> 
> Please add documentation for these, the same way it was done for all the other CS
> components [1].
> 
> [1]. https://elixir.bootlin.com/linux/latest/source/Documentation/ABI/testing
> (sysfs-bus-coresight-device-xyz)

Sure, will add the following new sysfs doc file in this regard.
Marked the KernelVersion as 5.12, will change if required.

new file mode 100644
index 0000000..5cb090f
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe
@@ -0,0 +1,14 @@
+What:          /sys/bus/coresight/devices/trbe<cpu>/align
+Date:          Feb 2021
+KernelVersion: 5.12
+Contact:       Anshuman Khandual <anshuman.khandual@arm.com>
+Description:   (Read) Shows the TRBE write pointer alignment. This value
+               is fetched from the TRBIDR register.
+
+What:          /sys/bus/coresight/devices/trbe<cpu>/dbm
+Date:          Feb 2021
+KernelVersion:  5.12
+Contact:       Anshuman Khandual <anshuman.khandual@arm.com>
+Description:   (Read) Shows if TRBE updates in the memory are with access
+               and dirty flag updates as well. This value is fetched from
+               the TRBIDR register.

> 
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 85ae4db..9e2e9b7 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -97,6 +97,7 @@
>>  #define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
>>  #define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
>>  #define SET_PSTATE_TCO(x)		__emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
>> +#define TSB_CSYNC			__emit_inst(0xd503225f)
>>  
>>  #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
>>  #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
>> index f154ae7..aa657ab 100644
>> --- a/drivers/hwtracing/coresight/Kconfig
>> +++ b/drivers/hwtracing/coresight/Kconfig
>> @@ -164,6 +164,17 @@ config CORESIGHT_CTI
>>  	  To compile this driver as a module, choose M here: the
>>  	  module will be called coresight-cti.
>>  
>> +config CORESIGHT_TRBE
>> +	bool "Trace Buffer Extension (TRBE) driver"
> 
> Shouldn't that be "tristate"?

Yes, will change.

> 
>> +	depends on ARM64
> 
> I would make it dependent on ETMv4 as well since it can only be used by that
> component.

Sure, will also add CORESIGHT_SOURCE_ETM4X as dependency.

> 
>> +	help
>> +	  This driver provides support for percpu Trace Buffer Extension (TRBE).
>> +	  TRBE always needs to be used along with it's corresponding percpu ETE
>> +	  component. ETE generates trace data which is then captured with TRBE.
>> +	  Unlike traditional sink devices, TRBE is a CPU feature accessible via
>> +	  system registers. But it's explicit dependency with trace unit (ETE)
>> +	  requires it to be plugged in as a coresight sink device.
> 
> Please add:
> 
>           "To compile this driver as a module, choose M here: the
>           module will be called coresight-trbe."

Added.

> 
> I'm out of time for today, I will continue on Monday.

Sure.

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-02-05 17:53   ` Mathieu Poirier
  2021-02-08  4:20     ` Anshuman Khandual
@ 2021-02-09 17:39     ` Mathieu Poirier
  2021-02-10  4:12       ` Anshuman Khandual
  1 sibling, 1 reply; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-09 17:39 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel

On Fri, Feb 05, 2021 at 10:53:30AM -0700, Mathieu Poirier wrote:
> On Wed, Jan 27, 2021 at 02:25:35PM +0530, Anshuman Khandual wrote:
> > Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
> > accessible via the system registers. The TRBE supports different addressing
> > modes including CPU virtual address and buffer modes including the circular
> > buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
> > an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
> > access to the trace buffer could be prohibited by a higher exception level
> > (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
> > private interrupt (PPI) on address translation errors and when the buffer
> > is full. Overall implementation here is inspired from the Arm SPE driver.
> >
> 
> I got this message when applying the patch: 
> 
> Applying: coresight: sink: Add TRBE driver
> .git/rebase-apply/patch:76: new blank line at EOF.
> +
> warning: 1 line adds whitespace errors.
>  
> > Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Cc: Mike Leach <mike.leach@linaro.org>
> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> > ---
> > Changes in V3:
> > 
> > - Added new DT bindings document TRBE.yaml
> > - Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3
> > - Dropped isb() from trbe_reset_local()
> > - Dropped gap between (void *) and buf->trbe_base
> > - Changed 'int' to 'unsigned int' in is_trbe_available()
> > - Dropped unused function set_trbe_running(), set_trbe_virtual_mode(),
> >   set_trbe_enabled() and set_trbe_limit_pointer()
> > - Changed get_trbe_flag_update(), is_trbe_programmable() and
> >   get_trbe_address_align() to accept TRBIDR value
> > - Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), is_trbe_trg(),
> >   is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value
> > - Dropped snapshot mode condition in arm_trbe_alloc_buffer()
> > - Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled
> > - Compute trbe_limit before trbe_write to get the updated handle
> > - Added trbe_stop_and_truncate_event()
> > - Dropped trbe_handle_fatal()
> > 
> >  Documentation/trace/coresight/coresight-trbe.rst |   39 +
> >  arch/arm64/include/asm/sysreg.h                  |    1 +
> >  drivers/hwtracing/coresight/Kconfig              |   11 +
> >  drivers/hwtracing/coresight/Makefile             |    1 +
> >  drivers/hwtracing/coresight/coresight-trbe.c     | 1023 ++++++++++++++++++++++
> >  drivers/hwtracing/coresight/coresight-trbe.h     |  160 ++++
> >  6 files changed, 1235 insertions(+)
> >  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
> >  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
> >  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
> > 
> > diff --git a/Documentation/trace/coresight/coresight-trbe.rst b/Documentation/trace/coresight/coresight-trbe.rst
> > new file mode 100644
> > index 0000000..1cbb819
> > --- /dev/null
> > +++ b/Documentation/trace/coresight/coresight-trbe.rst
> > @@ -0,0 +1,39 @@
> > +.. SPDX-License-Identifier: GPL-2.0
> > +
> > +==============================
> > +Trace Buffer Extension (TRBE).
> > +==============================
> > +
> > +    :Author:   Anshuman Khandual <anshuman.khandual@arm.com>
> > +    :Date:     November 2020
> > +
> > +Hardware Description
> > +--------------------
> > +
> > +Trace Buffer Extension (TRBE) is a percpu hardware which captures in system
> > +memory, CPU traces generated from a corresponding percpu tracing unit. This
> > +gets plugged in as a coresight sink device because the corresponding trace
> > +genarators (ETE), are plugged in as source device.
> > +
> > +The TRBE is not compliant to CoreSight architecture specifications, but is
> > +driven via the CoreSight driver framework to support the ETE (which is
> > +CoreSight compliant) integration.
> > +
> > +Sysfs files and directories
> > +---------------------------
> > +
> > +The TRBE devices appear on the existing coresight bus alongside the other
> > +coresight devices::
> > +
> > +	>$ ls /sys/bus/coresight/devices
> > +	trbe0  trbe1  trbe2 trbe3
> > +
> > +The ``trbe<N>`` named TRBEs are associated with a CPU.::
> > +
> > +	>$ ls /sys/bus/coresight/devices/trbe0/
> > +        align dbm
> > +
> > +*Key file items are:-*
> > +   * ``align``: TRBE write pointer alignment
> > +   * ``dbm``: TRBE updates memory with access and dirty flags
> > +
> 
> Please add documentation for these, the same way it was done for all the other CS
> components [1].
> 
> [1]. https://elixir.bootlin.com/linux/latest/source/Documentation/ABI/testing
> (sysfs-bus-coresight-device-xyz)
> 
> > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> > index 85ae4db..9e2e9b7 100644
> > --- a/arch/arm64/include/asm/sysreg.h
> > +++ b/arch/arm64/include/asm/sysreg.h
> > @@ -97,6 +97,7 @@
> >  #define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
> >  #define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
> >  #define SET_PSTATE_TCO(x)		__emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
> > +#define TSB_CSYNC			__emit_inst(0xd503225f)
> >  
> >  #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
> >  #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
> > diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> > index f154ae7..aa657ab 100644
> > --- a/drivers/hwtracing/coresight/Kconfig
> > +++ b/drivers/hwtracing/coresight/Kconfig
> > @@ -164,6 +164,17 @@ config CORESIGHT_CTI
> >  	  To compile this driver as a module, choose M here: the
> >  	  module will be called coresight-cti.
> >  
> > +config CORESIGHT_TRBE
> > +	bool "Trace Buffer Extension (TRBE) driver"
> 
> Shouldn't that be "tristate"?
> 
> > +	depends on ARM64
> 
> I would make it dependent on ETMv4 as well since it can only be used by that
> component.
> 
> > +	help
> > +	  This driver provides support for percpu Trace Buffer Extension (TRBE).
> > +	  TRBE always needs to be used along with it's corresponding percpu ETE
> > +	  component. ETE generates trace data which is then captured with TRBE.
> > +	  Unlike traditional sink devices, TRBE is a CPU feature accessible via
> > +	  system registers. But it's explicit dependency with trace unit (ETE)
> > +	  requires it to be plugged in as a coresight sink device.
> 
> Please add:
> 
>           "To compile this driver as a module, choose M here: the
>           module will be called coresight-trbe."
> 
> I'm out of time for today, I will continue on Monday.
> 
> Mathieu
> 
> > +
> >  config CORESIGHT_CTI_INTEGRATION_REGS
> >  	bool "Access CTI CoreSight Integration Registers"
> >  	depends on CORESIGHT_CTI
> > diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
> > index f20e357..d608165 100644
> > --- a/drivers/hwtracing/coresight/Makefile
> > +++ b/drivers/hwtracing/coresight/Makefile
> > @@ -21,5 +21,6 @@ obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
> >  obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
> >  obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
> >  obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
> > +obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
> >  coresight-cti-y := coresight-cti-core.o	coresight-cti-platform.o \
> >  		   coresight-cti-sysfs.o
> > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> > new file mode 100644
> > index 0000000..1464d8b
> > --- /dev/null
> > +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> > @@ -0,0 +1,1023 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * This driver enables Trace Buffer Extension (TRBE) as a per-cpu coresight
> > + * sink device could then pair with an appropriate per-cpu coresight source
> > + * device (ETE) thus generating required trace data. Trace can be enabled
> > + * via the perf framework.
> > + *
> > + * Copyright (C) 2020 ARM Ltd.
> > + *
> > + * Author: Anshuman Khandual <anshuman.khandual@arm.com>
> > + */
> > +#define DRVNAME "arm_trbe"
> > +
> > +#define pr_fmt(fmt) DRVNAME ": " fmt
> > +
> > +#include "coresight-trbe.h"
> > +
> > +#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
> > +
> > +/*
> > + * A padding packet that will help the user space tools
> > + * in skipping relevant sections in the captured trace
> > + * data which could not be decoded. TRBE doesn't support
> > + * formatting the trace data, unlike the legacy CoreSight
> > + * sinks and thus we use ETE trace packets to pad the
> > + * sections of the buffer.
> > + */
> > +#define ETE_IGNORE_PACKET 		0x70
> > +
> > +/*
> > + * Minimum amount of meaningful trace will contain:
> > + * A-Sync, Trace Info, Trace On, Address, Atom.
> > + * This is about 44bytes of ETE trace. To be on
> > + * the safer side, we assume 64bytes is the minimum
> > + * space required for a meaningful session, before
> > + * we hit a "WRAP" event.
> > + */
> > +#define TRBE_TRACE_MIN_BUF_SIZE		64
> > +
> > +enum trbe_fault_action {
> > +	TRBE_FAULT_ACT_WRAP,
> > +	TRBE_FAULT_ACT_SPURIOUS,
> > +	TRBE_FAULT_ACT_FATAL,
> > +};
> > +
> > +struct trbe_buf {
> > +	unsigned long trbe_base;
> > +	unsigned long trbe_limit;
> > +	unsigned long trbe_write;
> > +	int nr_pages;
> > +	void **pages;
> > +	bool snapshot;
> > +	struct trbe_cpudata *cpudata;
> > +};
> > +
> > +struct trbe_cpudata {
> > +	bool trbe_dbm;
> > +	u64 trbe_align;
> > +	int cpu;
> > +	enum cs_mode mode;
> > +	struct trbe_buf *buf;
> > +	struct trbe_drvdata *drvdata;
> > +};
> > +
> > +struct trbe_drvdata {
> > +	struct trbe_cpudata __percpu *cpudata;
> > +	struct perf_output_handle __percpu **handle;
> > +	struct hlist_node hotplug_node;
> > +	int irq;
> > +	cpumask_t supported_cpus;
> > +	enum cpuhp_state trbe_online;
> > +	struct platform_device *pdev;
> > +};
> > +
> > +static int trbe_alloc_node(struct perf_event *event)
> > +{
> > +	if (event->cpu == -1)
> > +		return NUMA_NO_NODE;
> > +	return cpu_to_node(event->cpu);
> > +}
> > +
> > +static void trbe_drain_buffer(void)
> > +{
> > +	asm(TSB_CSYNC);
> > +	dsb(nsh);
> > +}
> > +
> > +static void trbe_drain_and_disable_local(void)
> > +{
> > +	trbe_drain_buffer();
> > +	write_sysreg_s(0, SYS_TRBLIMITR_EL1);
> > +	isb();
> > +}
> > +
> > +static void trbe_reset_local(void)
> > +{
> > +	trbe_drain_and_disable_local();
> > +	write_sysreg_s(0, SYS_TRBPTR_EL1);
> > +	write_sysreg_s(0, SYS_TRBBASER_EL1);
> > +	write_sysreg_s(0, SYS_TRBSR_EL1);
> > +}
> > +
> > +static void trbe_stop_and_truncate_event(struct perf_output_handle *handle)
> > +{
> > +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> > +
> > +	/*
> > +	 * We cannot proceed with the buffer collection and we
> > +	 * do not have any data for the current session. The
> > +	 * etm_perf driver expects to close out the aux_buffer
> > +	 * at event_stop(). So disable the TRBE here and leave
> > +	 * the update_buffer() to return a 0 size.
> > +	 */
> > +	trbe_drain_and_disable_local();
> > +	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> > +	*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
> > +}
> > +
> > +/*
> > + * TRBE Buffer Management
> > + *
> > + * The TRBE buffer spans from the base pointer till the limit pointer. When enabled,
> > + * it starts writing trace data from the write pointer onward till the limit pointer.
> > + * When the write pointer reaches the address just before the limit pointer, it gets
> > + * wrapped around again to the base pointer. This is called a TRBE wrap event, which
> > + * generates a maintenance interrupt when operated in WRAP or FILL mode. This driver
> > + * uses FILL mode, where the TRBE stops the trace collection at wrap event. The IRQ
> > + * handler updates the AUX buffer and re-enables the TRBE with updated WRITE and
> > + * LIMIT pointers.
> > + *
> > + *	Wrap around with an IRQ
> > + *	------ < ------ < ------- < ----- < -----
> > + *	|					|
> > + *	------ > ------ > ------- > ----- > -----
> > + *
> > + *	+---------------+-----------------------+
> > + *	|		|			|
> > + *	+---------------+-----------------------+
> > + *	Base Pointer	Write Pointer		Limit Pointer
> > + *
> > + * The base and limit pointers always needs to be PAGE_SIZE aligned. But the write
> > + * pointer can be aligned to the implementation defined TRBE trace buffer alignment
> > + * as captured in trbe_cpudata->trbe_align.
> > + *
> > + *
> > + *		head		tail		wakeup
> > + *	+---------------------------------------+----- ~ ~ ------
> > + *	|$$$$$$$|################|$$$$$$$$$$$$$$|		|
> > + *	+---------------------------------------+----- ~ ~ ------
> > + *	Base Pointer	Write Pointer		Limit Pointer
> > + *
> > + * The perf_output_handle indices (head, tail, wakeup) are monotonically increasing
> > + * values which tracks all the driver writes and user reads from the perf auxiliary
> > + * buffer. Generally [head..tail] is the area where the driver can write into unless
> > + * the wakeup is behind the tail. Enabled TRBE buffer span needs to be adjusted and
> > + * configured depending on the perf_output_handle indices, so that the driver does
> > + * not override into areas in the perf auxiliary buffer which is being or yet to be
> > + * consumed from the user space. The enabled TRBE buffer area is a moving subset of
> > + * the allocated perf auxiliary buffer.
> > + */
> > +static void trbe_pad_buf(struct perf_output_handle *handle, int len)
> > +{
> > +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> > +	u64 head = PERF_IDX2OFF(handle->head, buf);
> > +
> > +	memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
> > +	if (!buf->snapshot)
> > +		perf_aux_output_skip(handle, len);
> > +}
> > +
> > +static unsigned long trbe_snapshot_offset(struct perf_output_handle *handle)
> > +{
> > +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> > +
> > +	/*
> > +	 * The ETE trace has alignment synchronization packets allowing
> > +	 * the decoder to reset in case of an overflow or corruption.
> > +	 * So we can use the entire buffer for the snapshot mode.
> > +	 */
> > +	return buf->nr_pages * PAGE_SIZE;
> > +}
> > +
> > +/*
> > + * TRBE Limit Calculation
> > + *
> > + * The following markers are used to illustrate various TRBE buffer situations.
> > + *
> > + * $$$$ - Data area, unconsumed captured trace data, not to be overridden
> > + * #### - Free area, enabled, trace will be written
> > + * %%%% - Free area, disabled, trace will not be written
> > + * ==== - Free area, padded with ETE_IGNORE_PACKET, trace will be skipped
> > + */
> > +static unsigned long __trbe_normal_offset(struct perf_output_handle *handle)
> > +{
> > +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> > +	struct trbe_cpudata *cpudata = buf->cpudata;
> > +	const u64 bufsize = buf->nr_pages * PAGE_SIZE;
> > +	u64 limit = bufsize;
> > +	u64 head, tail, wakeup;
> > +
> > +	head = PERF_IDX2OFF(handle->head, buf);
> > +
> > +	/*
> > +	 *		head
> > +	 *	------->|
> > +	 *	|
> > +	 *	head	TRBE align	tail
> > +	 * +----|-------|---------------|-------+
> > +	 * |$$$$|=======|###############|$$$$$$$|
> > +	 * +----|-------|---------------|-------+
> > +	 * trbe_base				trbe_base + nr_pages
> > +	 *
> > +	 * Perf aux buffer output head position can be misaligned depending on
> > +	 * various factors including user space reads. In case misaligned, head
> > +	 * needs to be aligned before TRBE can be configured. Pad the alignment
> > +	 * gap with ETE_IGNORE_PACKET bytes that will be ignored by user tools
> > +	 * and skip this section thus advancing the head.
> > +	 */
> > +	if (!IS_ALIGNED(head, cpudata->trbe_align)) {
> > +		unsigned long delta = roundup(head, cpudata->trbe_align) - head;
> > +
> > +		delta = min(delta, handle->size);
> > +		trbe_pad_buf(handle, delta);
> > +		head = PERF_IDX2OFF(handle->head, buf);
> > +	}
> > +
> > +	/*
> > +	 *	head = tail (size = 0)
> > +	 * +----|-------------------------------+
> > +	 * |$$$$|$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$	|
> > +	 * +----|-------------------------------+
> > +	 * trbe_base				trbe_base + nr_pages
> > +	 *
> > +	 * Perf aux buffer does not have any space for the driver to write into.
> > +	 * Just communicate trace truncation event to the user space by marking
> > +	 * it with PERF_AUX_FLAG_TRUNCATED.
> > +	 */
> > +	if (!handle->size) {
> > +		perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> > +		return 0;
> > +	}
> > +
> > +	/* Compute the tail and wakeup indices now that we've aligned head */
> > +	tail = PERF_IDX2OFF(handle->head + handle->size, buf);
> > +	wakeup = PERF_IDX2OFF(handle->wakeup, buf);
> > +
> > +	/*
> > +	 * Lets calculate the buffer area which TRBE could write into. There
> > +	 * are three possible scenarios here. Limit needs to be aligned with
> > +	 * PAGE_SIZE per the TRBE requirement. Always avoid clobbering the
> > +	 * unconsumed data.
> > +	 *
> > +	 * 1) head < tail
> > +	 *
> > +	 *	head			tail
> > +	 * +----|-----------------------|-------+
> > +	 * |$$$$|#######################|$$$$$$$|
> > +	 * +----|-----------------------|-------+
> > +	 * trbe_base			limit	trbe_base + nr_pages
> > +	 *
> > +	 * TRBE could write into [head..tail] area. Unless the tail is right at
> > +	 * the end of the buffer, neither an wrap around nor an IRQ is expected
> > +	 * while being enabled.
> > +	 *
> > +	 * 2) head == tail
> > +	 *
> > +	 *	head = tail (size > 0)
> > +	 * +----|-------------------------------+
> > +	 * |%%%%|###############################|
> > +	 * +----|-------------------------------+
> > +	 * trbe_base				limit = trbe_base + nr_pages
> > +	 *
> > +	 * TRBE should just write into [head..base + nr_pages] area even though
> > +	 * the entire buffer is empty. Reason being, when the trace reaches the
> > +	 * end of the buffer, it will just wrap around with an IRQ giving an
> > +	 * opportunity to reconfigure the buffer.
> > +	 *
> > +	 * 3) tail < head
> > +	 *
> > +	 *	tail			head
> > +	 * +----|-----------------------|-------+
> > +	 * |%%%%|$$$$$$$$$$$$$$$$$$$$$$$|#######|
> > +	 * +----|-----------------------|-------+
> > +	 * trbe_base				limit = trbe_base + nr_pages
> > +	 *
> > +	 * TRBE should just write into [head..base + nr_pages] area even though
> > +	 * the [trbe_base..tail] is also empty. Reason being, when the trace
> > +	 * reaches the end of the buffer, it will just wrap around with an IRQ
> > +	 * giving an opportunity to reconfigure the buffer.
> > +	 */
> > +	if (head < tail)
> > +		limit = round_down(tail, PAGE_SIZE);
> > +
> > +	/*
> > +	 * Wakeup may be arbitrarily far into the future. If it's not in the
> > +	 * current generation, either we'll wrap before hitting it, or it's
> > +	 * in the past and has been handled already.
> > +	 *
> > +	 * If there's a wakeup before we wrap, arrange to be woken up by the
> > +	 * page boundary following it. Keep the tail boundary if that's lower.
> > +	 *
> > +	 *	head		wakeup	tail
> > +	 * +----|---------------|-------|-------+
> > +	 * |$$$$|###############|%%%%%%%|$$$$$$$|
> > +	 * +----|---------------|-------|-------+
> > +	 * trbe_base		limit		trbe_base + nr_pages
> > +	 */
> > +	if (handle->wakeup < (handle->head + handle->size) && head <= wakeup)
> > +		limit = min(limit, round_up(wakeup, PAGE_SIZE));
> > +
> > +	/*
> > +	 * There are two situation when this can happen i.e limit is before
> > +	 * the head and hence TRBE cannot be configured.
> > +	 *
> > +	 * 1) head < tail (aligned down with PAGE_SIZE) and also they are both
> > +	 * within the same PAGE size range.
> > +	 *
> > +	 *			PAGE_SIZE
> > +	 *		|----------------------|
> > +	 *
> > +	 *		limit	head	tail
> > +	 * +------------|------|--------|-------+
> > +	 * |$$$$$$$$$$$$$$$$$$$|========|$$$$$$$|
> > +	 * +------------|------|--------|-------+
> > +	 * trbe_base				trbe_base + nr_pages
> > +	 *
> > +	 * 2) head < wakeup (aligned up with PAGE_SIZE) < tail and also both
> > +	 * head and wakeup are within same PAGE size range.
> > +	 *
> > +	 *		PAGE_SIZE
> > +	 *	|----------------------|
> > +	 *
> > +	 *	limit	head	wakeup  tail
> > +	 * +----|------|-------|--------|-------+
> > +	 * |$$$$$$$$$$$|=======|========|$$$$$$$|
> > +	 * +----|------|-------|--------|-------+
> > +	 * trbe_base				trbe_base + nr_pages
> > +	 */
> > +	if (limit > head)
> > +		return limit;
> > +
> > +	trbe_pad_buf(handle, handle->size);
> > +	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> > +	return 0;
> > +}
> > +
> > +static unsigned long trbe_normal_offset(struct perf_output_handle *handle)
> > +{
> > +	struct trbe_buf *buf = perf_get_aux(handle);
> > +	u64 limit = __trbe_normal_offset(handle);
> > +	u64 head = PERF_IDX2OFF(handle->head, buf);
> > +
> > +	/*
> > +	 * If the head is too close to the limit and we don't
> > +	 * have space for a meaningful run, we rather pad it
> > +	 * and start fresh.
> > +	 */
> > +	if (limit && (limit - head < TRBE_TRACE_MIN_BUF_SIZE)) {
> > +		trbe_pad_buf(handle, limit - head);
> > +		limit = __trbe_normal_offset(handle);
> > +	}
> > +	return limit;
> > +}
> > +
> > +static unsigned long compute_trbe_buffer_limit(struct perf_output_handle *handle)
> > +{
> > +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> > +	unsigned long offset;
> > +
> > +	if (buf->snapshot)
> > +		offset = trbe_snapshot_offset(handle);
> > +	else
> > +		offset = trbe_normal_offset(handle);
> > +	return buf->trbe_base + offset;
> > +}
> > +
> > +static void clr_trbe_status(void)
> > +{
> > +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
> > +
> > +	WARN_ON(is_trbe_enabled());
> > +	trbsr &= ~TRBSR_IRQ;
> > +	trbsr &= ~TRBSR_TRG;
> > +	trbsr &= ~TRBSR_WRAP;
> > +	trbsr &= ~(TRBSR_EC_MASK << TRBSR_EC_SHIFT);
> > +	trbsr &= ~(TRBSR_BSC_MASK << TRBSR_BSC_SHIFT);
> > +	trbsr &= ~TRBSR_STOP;
> > +	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
> > +}
> > +
> > +static void set_trbe_limit_pointer_enabled(unsigned long addr)
> > +{
> > +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> > +
> > +	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
> > +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> > +
> > +	trblimitr &= ~TRBLIMITR_NVM;
> > +	trblimitr &= ~(TRBLIMITR_FILL_MODE_MASK << TRBLIMITR_FILL_MODE_SHIFT);
> > +	trblimitr &= ~(TRBLIMITR_TRIG_MODE_MASK << TRBLIMITR_TRIG_MODE_SHIFT);
> > +	trblimitr &= ~(TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT);
> > +
> > +	/*
> > +	 * Fill trace buffer mode is used here while configuring the
> > +	 * TRBE for trace capture. In this particular mode, the trace
> > +	 * collection is stopped and a maintenance interrupt is raised
> > +	 * when the current write pointer wraps. This pause in trace
> > +	 * collection gives the software an opportunity to capture the
> > +	 * trace data in the interrupt handler, before reconfiguring
> > +	 * the TRBE.
> > +	 */
> > +	trblimitr |= (TRBE_FILL_MODE_FILL & TRBLIMITR_FILL_MODE_MASK) << TRBLIMITR_FILL_MODE_SHIFT;
> > +
> > +	/*
> > +	 * Trigger mode is not used here while configuring the TRBE for
> > +	 * the trace capture. Hence just keep this in the ignore mode.
> > +	 */
> > +	trblimitr |= (TRBE_TRIG_MODE_IGNORE & TRBLIMITR_TRIG_MODE_MASK) << TRBLIMITR_TRIG_MODE_SHIFT;
> > +	trblimitr |= (addr & PAGE_MASK);
> > +
> > +	trblimitr |= TRBLIMITR_ENABLE;
> > +	write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
> > +}
> > +
> > +static void trbe_enable_hw(struct trbe_buf *buf)
> > +{
> > +	WARN_ON(buf->trbe_write < buf->trbe_base);
> > +	WARN_ON(buf->trbe_write >= buf->trbe_limit);
> > +	set_trbe_disabled();
> > +	isb();
> > +	clr_trbe_status();
> > +	set_trbe_base_pointer(buf->trbe_base);
> > +	set_trbe_write_pointer(buf->trbe_write);
> > +
> > +	/*
> > +	 * Synchronize all the register updates
> > +	 * till now before enabling the TRBE.
> > +	 */
> > +	isb();
> > +	set_trbe_limit_pointer_enabled(buf->trbe_limit);
> > +
> > +	/* Synchronize the TRBE enable event */
> > +	isb();
> > +}
> > +
> > +static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
> > +				   struct perf_event *event, void **pages,
> > +				   int nr_pages, bool snapshot)
> > +{
> > +	struct trbe_buf *buf;
> > +	struct page **pglist;
> > +	int i;
> > +
> > +	/*
> > +	 * TRBE LIMIT and TRBE WRITE pointers must be page aligned. But with
> > +	 * just a single page, there is not much room left while writing into
> > +	 * a partially filled TRBE buffer. Hence restrict the minimum buffer
> > +	 * size as two pages.
> > +	 */
> > +	if (nr_pages < 2)
> > +		return NULL;
> > +
> > +	buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
> > +	if (IS_ERR(buf))
> > +		return ERR_PTR(-ENOMEM);
> > +
> > +	pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
> > +	if (IS_ERR(pglist)) {
> > +		kfree(buf);
> > +		return ERR_PTR(-ENOMEM);
> > +	}
> > +
> > +	for (i = 0; i < nr_pages; i++)
> > +		pglist[i] = virt_to_page(pages[i]);
> > +
> > +	buf->trbe_base = (unsigned long) vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
> > +	if (IS_ERR((void *)buf->trbe_base)) {
> > +		kfree(pglist);
> > +		kfree(buf);
> > +		return ERR_PTR(buf->trbe_base);
> > +	}
> > +	buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
> > +	buf->trbe_write = buf->trbe_base;
> > +	buf->snapshot = snapshot;
> > +	buf->nr_pages = nr_pages;
> > +	buf->pages = pages;
> > +	kfree(pglist);
> > +	return buf;
> > +}
> > +
> > +void arm_trbe_free_buffer(void *config)
> > +{
> > +	struct trbe_buf *buf = config;
> > +
> > +	vunmap((void *)buf->trbe_base);
> > +	kfree(buf);
> > +}
> > +
> > +static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
> > +					    struct perf_output_handle *handle,
> > +					    void *config)
> > +{
> > +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> > +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> > +	struct trbe_buf *buf = config;
> > +	unsigned long size, offset;
> > +
> > +	WARN_ON(buf->cpudata != cpudata);
> > +	WARN_ON(cpudata->cpu != smp_processor_id());
> > +	WARN_ON(cpudata->drvdata != drvdata);
> > +	if (cpudata->mode != CS_MODE_PERF)
> > +		return -EINVAL;
> > +
> > +	/*
> > +	 * If the TRBE was disabled due to lack of space in the AUX buffer or a
> > +	 * spurious fault, the driver leaves it disabled, truncating the buffer.
> > +	 * Since the etm_perf driver expects to close out the AUX buffer, the
> > +	 * driver skips it. Thus, just pass in 0 size here to indicate that the
> > +	 * buffer was truncated.
> > +	 */
> > +	if (!is_trbe_enabled())
> > +		return 0;
> > +	/*
> > +	 * perf handle structure needs to be shared with the TRBE IRQ handler for
> > +	 * capturing trace data and restarting the handle. There is a probability
> > +	 * of an undefined reference based crash when etm event is being stopped
> > +	 * while a TRBE IRQ also getting processed. This happens due the release
> > +	 * of perf handle via perf_aux_output_end() in etm_event_stop(). Stopping
> > +	 * the TRBE here will ensure that no IRQ could be generated when the perf
> > +	 * handle gets freed in etm_event_stop().
> > +	 */
> > +	trbe_drain_and_disable_local();
> > +	offset = get_trbe_write_pointer() - get_trbe_base_pointer();
> > +	size = offset - PERF_IDX2OFF(handle->head, buf);
> > +	if (buf->snapshot)
> > +		handle->head += size;
> > +	return size;
> > +}
> > +
> > +static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)
> > +{
> > +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> > +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> > +	struct perf_output_handle *handle = data;
> > +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> > +
> > +	WARN_ON(cpudata->cpu != smp_processor_id());
> > +	WARN_ON(cpudata->drvdata != drvdata);
> > +	if (mode != CS_MODE_PERF)
> > +		return -EINVAL;
> > +
> > +	*this_cpu_ptr(drvdata->handle) = handle;
> > +	cpudata->buf = buf;
> > +	cpudata->mode = mode;
> > +	buf->cpudata = cpudata;
> > +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
> > +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> > +	if (buf->trbe_limit == buf->trbe_base) {
> > +		trbe_stop_and_truncate_event(handle);
> > +		return 0;
> > +	}
> > +	trbe_enable_hw(buf);
> > +	return 0;
> > +}
> > +
> > +static int arm_trbe_disable(struct coresight_device *csdev)
> > +{
> > +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> > +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> > +	struct trbe_buf *buf = cpudata->buf;
> > +
> > +	WARN_ON(buf->cpudata != cpudata);
> > +	WARN_ON(cpudata->cpu != smp_processor_id());
> > +	WARN_ON(cpudata->drvdata != drvdata);
> > +	if (cpudata->mode != CS_MODE_PERF)
> > +		return -EINVAL;
> > +
> > +	trbe_drain_and_disable_local();
> > +	buf->cpudata = NULL;
> > +	cpudata->buf = NULL;
> > +	cpudata->mode = CS_MODE_DISABLED;
> > +	return 0;
> > +}
> > +
> > +static void trbe_handle_spurious(struct perf_output_handle *handle)
> > +{
> > +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> > +
> > +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
> > +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> > +	if (buf->trbe_limit == buf->trbe_base) {
> > +		trbe_drain_and_disable_local();
> > +		return;
> > +	}
> > +	trbe_enable_hw(buf);
> > +}
> > +
> > +static void trbe_handle_overflow(struct perf_output_handle *handle)
> > +{
> > +	struct perf_event *event = handle->event;
> > +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> > +	unsigned long offset, size;
> > +	struct etm_event_data *event_data;
> > +
> > +	offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
> > +	size = offset - PERF_IDX2OFF(handle->head, buf);
> > +	if (buf->snapshot)
> > +		handle->head = offset;
> > +	perf_aux_output_end(handle, size);
> > +
> > +	event_data = perf_aux_output_begin(handle, event);
> > +	if (!event_data) {
> > +		trbe_drain_and_disable_local();
> > +		*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
> > +		return;
> > +	}
> > +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
> > +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> > +	if (buf->trbe_limit == buf->trbe_base) {
> > +		trbe_stop_and_truncate_event(handle);
> > +		return;
> > +	}
> > +	*this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;
> > +	trbe_enable_hw(buf);
> > +}
> > +
> > +static bool is_perf_trbe(struct perf_output_handle *handle)
> > +{
> > +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> > +	struct trbe_cpudata *cpudata = buf->cpudata;
> > +	struct trbe_drvdata *drvdata = cpudata->drvdata;
> > +	int cpu = smp_processor_id();
> > +
> > +	WARN_ON(buf->trbe_base != get_trbe_base_pointer());
> > +	WARN_ON(buf->trbe_limit != get_trbe_limit_pointer());
> > +
> > +	if (cpudata->mode != CS_MODE_PERF)
> > +		return false;
> > +
> > +	if (cpudata->cpu != cpu)
> > +		return false;
> > +
> > +	if (!cpumask_test_cpu(cpu, &drvdata->supported_cpus))
> > +		return false;
> > +
> > +	return true;
> > +}
> > +
> > +static enum trbe_fault_action trbe_get_fault_act(struct perf_output_handle *handle)
> > +{
> > +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
> > +	int ec = get_trbe_ec(trbsr);
> > +	int bsc = get_trbe_bsc(trbsr);
> > +
> > +	WARN_ON(is_trbe_running(trbsr));
> > +	if (is_trbe_trg(trbsr) || is_trbe_abort(trbsr))
> > +		return TRBE_FAULT_ACT_FATAL;
> > +
> > +	if ((ec == TRBE_EC_STAGE1_ABORT) || (ec == TRBE_EC_STAGE2_ABORT))
> > +		return TRBE_FAULT_ACT_FATAL;
> > +
> > +	if (is_trbe_wrap(trbsr) && (ec == TRBE_EC_OTHERS) && (bsc == TRBE_BSC_FILLED)) {
> > +		if (get_trbe_write_pointer() == get_trbe_base_pointer())
> > +			return TRBE_FAULT_ACT_WRAP;
> > +	}
> > +	return TRBE_FAULT_ACT_SPURIOUS;
> > +}
> > +
> > +static irqreturn_t arm_trbe_irq_handler(int irq, void *dev)
> > +{
> > +	struct perf_output_handle **handle_ptr = dev;
> > +	struct perf_output_handle *handle = *handle_ptr;
> > +	enum trbe_fault_action act;
> > +
> > +	WARN_ON(!is_trbe_irq(read_sysreg_s(SYS_TRBSR_EL1)));
> > +	clr_trbe_irq();
> > +
> > +	/*
> > +	 * Ensure the trace is visible to the CPUs and
> > +	 * any external aborts have been resolved.
> > +	 */
> > +	trbe_drain_buffer();
> > +	isb();
> > +
> > +	if (!perf_get_aux(handle))
> > +		return IRQ_NONE;
> > +
> > +	if (!is_perf_trbe(handle))
> > +		return IRQ_NONE;
> > +
> > +	irq_work_run();

There is a comment in the SPE driver about this.  Since this driver closely
follows that implementation it would be nice to have the comments as well.
Otherwise the reader has to constantly go back to the original driver.

I will come back to this function later.

> > +
> > +	act = trbe_get_fault_act(handle);
> > +	switch (act) {
> > +	case TRBE_FAULT_ACT_WRAP:
> > +		trbe_handle_overflow(handle);
> > +		break;
> > +	case TRBE_FAULT_ACT_SPURIOUS:
> > +		trbe_handle_spurious(handle);
> > +		break;
> > +	case TRBE_FAULT_ACT_FATAL:
> > +		trbe_stop_and_truncate_event(handle);
> > +		break;
> > +	}
> > +	return IRQ_HANDLED;
> > +}
> > +
> > +static const struct coresight_ops_sink arm_trbe_sink_ops = {
> > +	.enable		= arm_trbe_enable,
> > +	.disable	= arm_trbe_disable,
> > +	.alloc_buffer	= arm_trbe_alloc_buffer,
> > +	.free_buffer	= arm_trbe_free_buffer,
> > +	.update_buffer	= arm_trbe_update_buffer,
> > +};
> > +
> > +static const struct coresight_ops arm_trbe_cs_ops = {
> > +	.sink_ops	= &arm_trbe_sink_ops,
> > +};
> > +
> > +static ssize_t align_show(struct device *dev, struct device_attribute *attr, char *buf)
> > +{
> > +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
> > +
> > +	return sprintf(buf, "%llx\n", cpudata->trbe_align);
> > +}
> > +static DEVICE_ATTR_RO(align);
> > +
> > +static ssize_t dbm_show(struct device *dev, struct device_attribute *attr, char *buf)
> > +{
> > +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
> > +
> > +	return sprintf(buf, "%d\n", cpudata->trbe_dbm);
> > +}
> > +static DEVICE_ATTR_RO(dbm);
> > +
> > +static struct attribute *arm_trbe_attrs[] = {
> > +	&dev_attr_align.attr,
> > +	&dev_attr_dbm.attr,
> > +	NULL,
> > +};
> > +
> > +static const struct attribute_group arm_trbe_group = {
> > +	.attrs = arm_trbe_attrs,
> > +};
> > +
> > +static const struct attribute_group *arm_trbe_groups[] = {
> > +	&arm_trbe_group,
> > +	NULL,
> > +};
> > +
> > +static void arm_trbe_probe_coresight_cpu(void *info)
> > +{
> > +	struct trbe_drvdata *drvdata = info;
> > +	struct coresight_desc desc = { 0 };
> > +	int cpu = smp_processor_id();
> > +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
> > +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
> > +	u64 trbidr = read_sysreg_s(SYS_TRBIDR_EL1);
> > +	struct device *dev;
> > +
> > +	if (WARN_ON(!cpudata))
> > +		goto cpu_clear;

Where was the memory for cpudata allocated?  As far as I can tell, at this time
it is just a pointer that was not allocated and as such it should be NULL.

> > +
> > +	if (trbe_csdev)
> > +		return;
> > +
> > +	cpudata->cpu = smp_processor_id();

Why call this again when you already did above?  And how is
arm_trbe_probe_coresight_cpu() is called for every CPU in the system?

> > +	cpudata->drvdata = drvdata;
> > +	dev = &cpudata->drvdata->pdev->dev;
> > +
> > +	if (!is_trbe_available()) {
> > +		pr_err("TRBE is not implemented on cpu %d\n", cpudata->cpu);
> > +		goto cpu_clear;
> > +	}
> > +
> > +	if (!is_trbe_programmable(trbidr)) {
> > +		pr_err("TRBE is owned in higher exception level on cpu %d\n", cpudata->cpu);
> > +		goto cpu_clear;
> > +	}
> > +	desc.name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", DRVNAME, smp_processor_id());
> > +	if (IS_ERR(desc.name))
> > +		goto cpu_clear;
> > +
> > +	desc.type = CORESIGHT_DEV_TYPE_SINK;
> > +	desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
> > +	desc.ops = &arm_trbe_cs_ops;
> > +	desc.pdata = dev_get_platdata(dev);
> > +	desc.groups = arm_trbe_groups;
> > +	desc.dev = dev;
> > +	trbe_csdev = coresight_register(&desc);
> > +	if (IS_ERR(trbe_csdev))
> > +		goto cpu_clear;
> > +
> > +	dev_set_drvdata(&trbe_csdev->dev, cpudata);
> > +	cpudata->trbe_dbm = get_trbe_flag_update(trbidr);
> > +	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
> > +	if (cpudata->trbe_align > SZ_2K) {
> > +		pr_err("Unsupported alignment on cpu %d\n", cpudata->cpu);
> > +		goto cpu_clear;
> > +	}
> > +	per_cpu(csdev_sink, cpu) = trbe_csdev;
> > +	trbe_reset_local();
> > +	enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
> > +	return;
> > +cpu_clear:
> > +	cpumask_clear_cpu(cpudata->cpu, &cpudata->drvdata->supported_cpus);
> > +}
> > +
> > +static void arm_trbe_remove_coresight_cpu(void *info)
> > +{
> > +	int cpu = smp_processor_id();
> > +	struct trbe_drvdata *drvdata = info;
> > +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
> > +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
> > +
> > +	if (trbe_csdev) {
> > +		coresight_unregister(trbe_csdev);
> > +		cpudata->drvdata = NULL;
> > +		per_cpu(csdev_sink, cpu) = NULL;
> > +	}
> > +	disable_percpu_irq(drvdata->irq);
> > +	trbe_reset_local();
> > +}
> > +
> > +static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata)
> > +{
> > +	drvdata->cpudata = alloc_percpu(typeof(*drvdata->cpudata));
> > +	if (IS_ERR(drvdata->cpudata))
> > +		return PTR_ERR(drvdata->cpudata);
> > +
> > +	arm_trbe_probe_coresight_cpu(drvdata);
> > +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_probe_coresight_cpu, drvdata, 1);
> > +	return 0;
> > +}
> > +
> > +static int arm_trbe_remove_coresight(struct trbe_drvdata *drvdata)
> > +{
> > +	arm_trbe_remove_coresight_cpu(drvdata);
> > +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_remove_coresight_cpu, drvdata, 1);
> > +	free_percpu(drvdata->cpudata);
> > +	return 0;
> > +}
> > +
> > +static int arm_trbe_cpu_startup(unsigned int cpu, struct hlist_node *node)
> > +{
> > +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
> > +
> > +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
> > +		if (!per_cpu(csdev_sink, cpu)) {
> > +			arm_trbe_probe_coresight_cpu(drvdata);
> > +		} else {
> > +			trbe_reset_local();
> > +			enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
> > +		}
> > +	}
> > +	return 0;
> > +}
> > +
> > +static int arm_trbe_cpu_teardown(unsigned int cpu, struct hlist_node *node)
> > +{
> > +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
> > +
> > +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
> > +		disable_percpu_irq(drvdata->irq);
> > +		trbe_reset_local();
> > +	}
> > +	return 0;
> > +}
> > +
> > +static int arm_trbe_probe_cpuhp(struct trbe_drvdata *drvdata)
> > +{
> > +	enum cpuhp_state trbe_online;
> > +
> > +	trbe_online = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
> > +					arm_trbe_cpu_startup, arm_trbe_cpu_teardown);
> > +	if (trbe_online < 0)
> > +		return -EINVAL;
> > +
> > +	if (cpuhp_state_add_instance(trbe_online, &drvdata->hotplug_node))
> > +		return -EINVAL;
> > +
> > +	drvdata->trbe_online = trbe_online;
> > +	return 0;
> > +}
> > +
> > +static void arm_trbe_remove_cpuhp(struct trbe_drvdata *drvdata)
> > +{
> > +	cpuhp_remove_multi_state(drvdata->trbe_online);
> > +}
> > +
> > +static int arm_trbe_probe_irq(struct platform_device *pdev,
> > +			      struct trbe_drvdata *drvdata)
> > +{
> > +	drvdata->irq = platform_get_irq(pdev, 0);
> > +	if (!drvdata->irq) {

Please use function platform_get_irq() properly - there is even an example on
how to do so in the documentation section of the function.

> > +		pr_err("IRQ not found for the platform device\n");
> > +		return -ENXIO;

Why use a different error code?

> > +	}
> > +
> > +	if (!irq_is_percpu(drvdata->irq)) {
> > +		pr_err("IRQ is not a PPI\n");
> > +		return -EINVAL;
> > +	}
> > +
> > +	if (irq_get_percpu_devid_partition(drvdata->irq, &drvdata->supported_cpus))
> > +		return -EINVAL;
> > +
> > +	drvdata->handle = alloc_percpu(typeof(*drvdata->handle));
> > +	if (!drvdata->handle)
> > +		return -ENOMEM;
> > +
> > +	if (request_percpu_irq(drvdata->irq, arm_trbe_irq_handler, DRVNAME, drvdata->handle)) {
> > +		free_percpu(drvdata->handle);
> > +		return -EINVAL;

Here too you need to use the error code from the calling function rather than
making your own.  Please revise for the entire patch.

> > +	}
> > +	return 0;
> > +}
> > +
> > +static void arm_trbe_remove_irq(struct trbe_drvdata *drvdata)
> > +{
> > +	free_percpu_irq(drvdata->irq, drvdata->handle);
> > +	free_percpu(drvdata->handle);
> > +}
> > +
> > +static int arm_trbe_device_probe(struct platform_device *pdev)
> > +{
> > +	struct coresight_platform_data *pdata;
> > +	struct trbe_drvdata *drvdata;
> > +	struct device *dev = &pdev->dev;
> > +	int ret;
> > +
> > +	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> > +	if (IS_ERR(drvdata))
> > +		return -ENOMEM;

        if (!drvdata)

> > +
> > +	pdata = coresight_get_platform_data(dev);
> > +	if (IS_ERR(pdata)) {
> > +		kfree(drvdata);

No need to do this since devm_kzalloc() was used above.

> > +		return -ENOMEM;

Why not using the error from coresight_get_platform_data() instead of
masking it?

> > +	}
> > +
> > +	dev_set_drvdata(dev, drvdata);
> > +	dev->platform_data = pdata;
> > +	drvdata->pdev = pdev;
> > +	ret = arm_trbe_probe_irq(pdev, drvdata);
> > +	if (ret)
> > +		goto irq_failed;
> > +
> > +	ret = arm_trbe_probe_coresight(drvdata);
> > +	if (ret)
> > +		goto probe_failed;
> > +
> > +	ret = arm_trbe_probe_cpuhp(drvdata);
> > +	if (ret)
> > +		goto cpuhp_failed;
> > +
> > +	return 0;
> > +cpuhp_failed:
> > +	arm_trbe_remove_coresight(drvdata);
> > +probe_failed:
> > +	arm_trbe_remove_irq(drvdata);
> > +irq_failed:
> > +	kfree(pdata);
> > +	kfree(drvdata);

Same here - both @pdata and @drvdata have been allocated by devm_kzalloc().
devm_kzalloc().

> > +	return ret;
> > +}
> > +
> > +static int arm_trbe_device_remove(struct platform_device *pdev)
> > +{
> > +	struct coresight_platform_data *pdata = dev_get_platdata(&pdev->dev);
> > +	struct trbe_drvdata *drvdata = platform_get_drvdata(pdev);
> > +
> > +	arm_trbe_remove_coresight(drvdata);
> > +	arm_trbe_remove_cpuhp(drvdata);
> > +	arm_trbe_remove_irq(drvdata);
> > +	kfree(pdata);
> > +	kfree(drvdata);
> > +	return 0;
> > +}
> > +
> > +static const struct of_device_id arm_trbe_of_match[] = {
> > +	{ .compatible = "arm,trace-buffer-extension"},
> > +	{},
> > +};
> > +MODULE_DEVICE_TABLE(of, arm_trbe_of_match);
> > +
> > +static struct platform_driver arm_trbe_driver = {
> > +	.driver	= {
> > +		.name = DRVNAME,
> > +		.of_match_table = of_match_ptr(arm_trbe_of_match),
> > +		.suppress_bind_attrs = true,
> > +	},
> > +	.probe	= arm_trbe_device_probe,
> > +	.remove	= arm_trbe_device_remove,
> > +};
> > +
> > +static int __init arm_trbe_init(void)
> > +{
> > +	int ret;
> > +
> > +	if (arm64_kernel_unmapped_at_el0()) {
> > +		pr_err("TRBE wouldn't work if kernel gets unmapped at EL0\n");
> > +		return -EOPNOTSUPP;
> > +	}
> > +
> > +	ret = platform_driver_register(&arm_trbe_driver);
> > +	if (!ret)
> > +		return 0;
> > +
> > +	pr_err("Error registering %s platform driver\n", DRVNAME);
> > +	return ret;
> > +}
> > +
> > +static void __exit arm_trbe_exit(void)
> > +{
> > +	platform_driver_unregister(&arm_trbe_driver);
> > +}
> > +module_init(arm_trbe_init);
> > +module_exit(arm_trbe_exit);
> > +
> > +MODULE_AUTHOR("Anshuman Khandual <anshuman.khandual@arm.com>");
> > +MODULE_DESCRIPTION("Arm Trace Buffer Extension (TRBE) driver");
> > +MODULE_LICENSE("GPL v2");
> > diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h
> > new file mode 100644
> > index 0000000..43308bc
> > --- /dev/null
> > +++ b/drivers/hwtracing/coresight/coresight-trbe.h
> > @@ -0,0 +1,160 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * This contains all required hardware related helper functions for
> > + * Trace Buffer Extension (TRBE) driver in the coresight framework.
> > + *
> > + * Copyright (C) 2020 ARM Ltd.
> > + *
> > + * Author: Anshuman Khandual <anshuman.khandual@arm.com>
> > + */
> > +#include <linux/coresight.h>
> > +#include <linux/device.h>
> > +#include <linux/irq.h>
> > +#include <linux/kernel.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/smp.h>
> > +
> > +#include "coresight-etm-perf.h"
> > +
> > +DECLARE_PER_CPU(struct coresight_device *, csdev_sink);
> > +
> > +static inline bool is_trbe_available(void)
> > +{
> > +	u64 aa64dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
> > +	unsigned int trbe = cpuid_feature_extract_unsigned_field(aa64dfr0, ID_AA64DFR0_TRBE_SHIFT);
> > +
> > +	return trbe >= 0b0001;
> > +}
> > +
> > +static inline bool is_trbe_enabled(void)
> > +{
> > +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> > +
> > +	return trblimitr & TRBLIMITR_ENABLE;
> > +}
> > +
> > +#define TRBE_EC_OTHERS		0
> > +#define TRBE_EC_STAGE1_ABORT	36
> > +#define TRBE_EC_STAGE2_ABORT	37
> > +
> > +static inline int get_trbe_ec(u64 trbsr)
> > +{
> > +	return (trbsr >> TRBSR_EC_SHIFT) & TRBSR_EC_MASK;
> > +}
> > +
> > +#define TRBE_BSC_NOT_STOPPED	0
> > +#define	TRBE_BSC_FILLED		1
> > +#define TRBE_BSC_TRIGGERED	2
> > +
> > +static inline int get_trbe_bsc(u64 trbsr)
> > +{
> > +	return (trbsr >> TRBSR_BSC_SHIFT) & TRBSR_BSC_MASK;
> > +}
> > +
> > +static inline void clr_trbe_irq(void)
> > +{
> > +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
> > +
> > +	trbsr &= ~TRBSR_IRQ;
> > +	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
> > +}
> > +
> > +static inline bool is_trbe_irq(u64 trbsr)
> > +{
> > +	return trbsr & TRBSR_IRQ;
> > +}
> > +
> > +static inline bool is_trbe_trg(u64 trbsr)
> > +{
> > +	return trbsr & TRBSR_TRG;
> > +}
> > +
> > +static inline bool is_trbe_wrap(u64 trbsr)
> > +{
> > +	return trbsr & TRBSR_WRAP;
> > +}
> > +
> > +static inline bool is_trbe_abort(u64 trbsr)
> > +{
> > +	return trbsr & TRBSR_ABORT;
> > +}
> > +
> > +static inline bool is_trbe_running(u64 trbsr)
> > +{
> > +	return !(trbsr & TRBSR_STOP);
> > +}
> > +
> > +#define TRBE_TRIG_MODE_STOP		0
> > +#define TRBE_TRIG_MODE_IRQ		1
> > +#define TRBE_TRIG_MODE_IGNORE		3
> > +
> > +#define TRBE_FILL_MODE_FILL		0
> > +#define TRBE_FILL_MODE_WRAP		1
> > +#define TRBE_FILL_MODE_CIRCULAR_BUFFER	3
> > +
> > +static inline void set_trbe_disabled(void)
> > +{
> > +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> > +
> > +	trblimitr &= ~TRBLIMITR_ENABLE;
> > +	write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
> > +}
> > +
> > +static inline bool get_trbe_flag_update(u64 trbidr)
> > +{
> > +	return trbidr & TRBIDR_FLAG;
> > +}
> > +
> > +static inline bool is_trbe_programmable(u64 trbidr)
> > +{
> > +	return !(trbidr & TRBIDR_PROG);
> > +}
> > +
> > +static inline int get_trbe_address_align(u64 trbidr)
> > +{
> > +	return (trbidr >> TRBIDR_ALIGN_SHIFT) & TRBIDR_ALIGN_MASK;
> > +}
> > +
> > +static inline unsigned long get_trbe_write_pointer(void)
> > +{
> > +	u64 trbptr = read_sysreg_s(SYS_TRBPTR_EL1);
> > +	unsigned long addr = (trbptr >> TRBPTR_PTR_SHIFT) & TRBPTR_PTR_MASK;
> > +
> > +	return addr;
> > +}
> > +
> > +static inline void set_trbe_write_pointer(unsigned long addr)
> > +{
> > +	WARN_ON(is_trbe_enabled());
> > +	addr = (addr >> TRBPTR_PTR_SHIFT) & TRBPTR_PTR_MASK;
> > +	write_sysreg_s(addr, SYS_TRBPTR_EL1);
> > +}
> > +
> > +static inline unsigned long get_trbe_limit_pointer(void)
> > +{
> > +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> > +	unsigned long limit = (trblimitr >> TRBLIMITR_LIMIT_SHIFT) & TRBLIMITR_LIMIT_MASK;
> > +	unsigned long addr = limit << TRBLIMITR_LIMIT_SHIFT;
> > +
> > +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> > +	return addr;
> > +}
> > +
> > +static inline unsigned long get_trbe_base_pointer(void)
> > +{
> > +	u64 trbbaser = read_sysreg_s(SYS_TRBBASER_EL1);
> > +	unsigned long addr = (trbbaser >> TRBBASER_BASE_SHIFT) & TRBBASER_BASE_MASK;
> > +
> > +	addr = addr << TRBBASER_BASE_SHIFT;
> > +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> > +	return addr;
> > +}
> > +
> > +static inline void set_trbe_base_pointer(unsigned long addr)
> > +{
> > +	WARN_ON(is_trbe_enabled());
> > +	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
> > +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> > +	write_sysreg_s(addr, SYS_TRBBASER_EL1);
> > +}
> > -- 
> > 2.7.4
> > 

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 06/14] dts: bindings: Document device tree bindings for ETE
  2021-01-27  8:55 ` [PATCH V3 06/14] dts: bindings: Document device tree bindings for ETE Anshuman Khandual
@ 2021-02-09 19:00   ` Rob Herring
  2021-02-10 12:33     ` Suzuki K Poulose
  0 siblings, 1 reply; 90+ messages in thread
From: Rob Herring @ 2021-02-09 19:00 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, mathieu.poirier, suzuki.poulose,
	mike.leach, lcherian, linux-kernel, devicetree

On Wed, Jan 27, 2021 at 02:25:30PM +0530, Anshuman Khandual wrote:
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> Document the device tree bindings for Embedded Trace Extensions.
> ETE can be connected to legacy coresight components and thus
> could optionally contain a connection graph as described by
> the CoreSight bindings.
> 
> Cc: devicetree@vger.kernel.org
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> Changes in V3:
> 
> - Fixed all DT yaml semantics problems
> 
>  Documentation/devicetree/bindings/arm/ete.yaml | 74 ++++++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/ete.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/ete.yaml b/Documentation/devicetree/bindings/arm/ete.yaml
> new file mode 100644
> index 0000000..edc1fe2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/ete.yaml
> @@ -0,0 +1,74 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +# Copyright 2021, Arm Ltd
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/ete.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: ARM Embedded Trace Extensions
> +
> +maintainers:
> +  - Suzuki K Poulose <suzuki.poulose@arm.com>
> +  - Mathieu Poirier <mathieu.poirier@linaro.org>
> +
> +description: |
> +  Arm Embedded Trace Extension(ETE) is a per CPU trace component that
> +  allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
> +  architecture and has extended support for future architecture changes.
> +  The trace generated by the ETE could be stored via legacy CoreSight
> +  components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
> +  Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
> +  legacy CoreSight components, a node must be listed per instance, along
> +  with any optional connection graph as per the coresight bindings.
> +  See bindings/arm/coresight.txt.
> +
> +properties:
> +  $nodename:
> +    pattern: "^ete([0-9a-f]+)$"
> +  compatible:
> +    items:
> +      - const: arm,embedded-trace-extension
> +
> +  cpu:

We've already established 'cpus' for this purpose.

> +    description: |
> +      Handle to the cpu this ETE is bound to.
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +
> +  out-ports:
> +    type: object

Replace with: $ref: /schemas/graph.yaml#/properties/ports

> +    description: |
> +      Output connections from the ETE to legacy CoreSight trace bus.
> +    properties:
> +      port:
> +        $ref: /schemas/graph.yaml#/properties/port

Actually, if only 1 port ever, you can drop 'out-ports' and just have 
'port'. Not sure though if the coresight stuff depends on 'out-ports'.

> +
> +required:
> +  - compatible
> +  - cpu
> +
> +additionalProperties: false
> +
> +examples:
> +
> +# An ETE node without legacy CoreSight connections
> +  - |
> +    ete0 {
> +      compatible = "arm,embedded-trace-extension";
> +      cpu = <&cpu_0>;
> +    };
> +# An ETE node with legacy CoreSight connections
> +  - |
> +   ete1 {
> +      compatible = "arm,embedded-trace-extension";
> +      cpu = <&cpu_1>;
> +
> +      out-ports {        /* legacy coresight connection */
> +         port {
> +             ete1_out_port: endpoint {
> +                remote-endpoint = <&funnel_in_port0>;
> +             };
> +         };
> +      };
> +   };
> +
> +...
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 12/14] dts: bindings: Document device tree bindings for Arm TRBE
  2021-01-27  8:55 ` [PATCH V3 12/14] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual
@ 2021-02-09 19:04   ` Rob Herring
  0 siblings, 0 replies; 90+ messages in thread
From: Rob Herring @ 2021-02-09 19:04 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-kernel, linux-arm-kernel, devicetree, coresight,
	mike.leach, mathieu.poirier, lcherian, suzuki.poulose

On Wed, 27 Jan 2021 14:25:36 +0530, Anshuman Khandual wrote:
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> Document the device tree bindings for Trace Buffer Extension (TRBE).
> 
> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> Changes in V3:
> 
> - Added missing description for the TRBE hardware
> - Fixed all DT yaml semantics problems
> 
>  Documentation/devicetree/bindings/arm/trbe.yaml | 49 +++++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/trbe.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-02-09 17:39     ` Mathieu Poirier
@ 2021-02-10  4:12       ` Anshuman Khandual
  2021-02-10 16:54         ` Mathieu Poirier
  0 siblings, 1 reply; 90+ messages in thread
From: Anshuman Khandual @ 2021-02-10  4:12 UTC (permalink / raw)
  To: Mathieu Poirier
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel



On 2/9/21 11:09 PM, Mathieu Poirier wrote:
> On Fri, Feb 05, 2021 at 10:53:30AM -0700, Mathieu Poirier wrote:
>> On Wed, Jan 27, 2021 at 02:25:35PM +0530, Anshuman Khandual wrote:
>>> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
>>> accessible via the system registers. The TRBE supports different addressing
>>> modes including CPU virtual address and buffer modes including the circular
>>> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
>>> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
>>> access to the trace buffer could be prohibited by a higher exception level
>>> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
>>> private interrupt (PPI) on address translation errors and when the buffer
>>> is full. Overall implementation here is inspired from the Arm SPE driver.
>>>
>>
>> I got this message when applying the patch: 
>>
>> Applying: coresight: sink: Add TRBE driver
>> .git/rebase-apply/patch:76: new blank line at EOF.
>> +
>> warning: 1 line adds whitespace errors.
>>  
>>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>>> Cc: Mike Leach <mike.leach@linaro.org>
>>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>>> ---
>>> Changes in V3:
>>>
>>> - Added new DT bindings document TRBE.yaml
>>> - Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3
>>> - Dropped isb() from trbe_reset_local()
>>> - Dropped gap between (void *) and buf->trbe_base
>>> - Changed 'int' to 'unsigned int' in is_trbe_available()
>>> - Dropped unused function set_trbe_running(), set_trbe_virtual_mode(),
>>>   set_trbe_enabled() and set_trbe_limit_pointer()
>>> - Changed get_trbe_flag_update(), is_trbe_programmable() and
>>>   get_trbe_address_align() to accept TRBIDR value
>>> - Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), is_trbe_trg(),
>>>   is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value
>>> - Dropped snapshot mode condition in arm_trbe_alloc_buffer()
>>> - Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled
>>> - Compute trbe_limit before trbe_write to get the updated handle
>>> - Added trbe_stop_and_truncate_event()
>>> - Dropped trbe_handle_fatal()
>>>
>>>  Documentation/trace/coresight/coresight-trbe.rst |   39 +
>>>  arch/arm64/include/asm/sysreg.h                  |    1 +
>>>  drivers/hwtracing/coresight/Kconfig              |   11 +
>>>  drivers/hwtracing/coresight/Makefile             |    1 +
>>>  drivers/hwtracing/coresight/coresight-trbe.c     | 1023 ++++++++++++++++++++++
>>>  drivers/hwtracing/coresight/coresight-trbe.h     |  160 ++++
>>>  6 files changed, 1235 insertions(+)
>>>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
>>>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
>>>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
>>>
>>> diff --git a/Documentation/trace/coresight/coresight-trbe.rst b/Documentation/trace/coresight/coresight-trbe.rst
>>> new file mode 100644
>>> index 0000000..1cbb819
>>> --- /dev/null
>>> +++ b/Documentation/trace/coresight/coresight-trbe.rst
>>> @@ -0,0 +1,39 @@
>>> +.. SPDX-License-Identifier: GPL-2.0
>>> +
>>> +==============================
>>> +Trace Buffer Extension (TRBE).
>>> +==============================
>>> +
>>> +    :Author:   Anshuman Khandual <anshuman.khandual@arm.com>
>>> +    :Date:     November 2020
>>> +
>>> +Hardware Description
>>> +--------------------
>>> +
>>> +Trace Buffer Extension (TRBE) is a percpu hardware which captures in system
>>> +memory, CPU traces generated from a corresponding percpu tracing unit. This
>>> +gets plugged in as a coresight sink device because the corresponding trace
>>> +genarators (ETE), are plugged in as source device.
>>> +
>>> +The TRBE is not compliant to CoreSight architecture specifications, but is
>>> +driven via the CoreSight driver framework to support the ETE (which is
>>> +CoreSight compliant) integration.
>>> +
>>> +Sysfs files and directories
>>> +---------------------------
>>> +
>>> +The TRBE devices appear on the existing coresight bus alongside the other
>>> +coresight devices::
>>> +
>>> +	>$ ls /sys/bus/coresight/devices
>>> +	trbe0  trbe1  trbe2 trbe3
>>> +
>>> +The ``trbe<N>`` named TRBEs are associated with a CPU.::
>>> +
>>> +	>$ ls /sys/bus/coresight/devices/trbe0/
>>> +        align dbm
>>> +
>>> +*Key file items are:-*
>>> +   * ``align``: TRBE write pointer alignment
>>> +   * ``dbm``: TRBE updates memory with access and dirty flags
>>> +
>>
>> Please add documentation for these, the same way it was done for all the other CS
>> components [1].
>>
>> [1]. https://elixir.bootlin.com/linux/latest/source/Documentation/ABI/testing
>> (sysfs-bus-coresight-device-xyz)
>>
>>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>>> index 85ae4db..9e2e9b7 100644
>>> --- a/arch/arm64/include/asm/sysreg.h
>>> +++ b/arch/arm64/include/asm/sysreg.h
>>> @@ -97,6 +97,7 @@
>>>  #define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
>>>  #define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
>>>  #define SET_PSTATE_TCO(x)		__emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
>>> +#define TSB_CSYNC			__emit_inst(0xd503225f)
>>>  
>>>  #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
>>>  #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
>>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
>>> index f154ae7..aa657ab 100644
>>> --- a/drivers/hwtracing/coresight/Kconfig
>>> +++ b/drivers/hwtracing/coresight/Kconfig
>>> @@ -164,6 +164,17 @@ config CORESIGHT_CTI
>>>  	  To compile this driver as a module, choose M here: the
>>>  	  module will be called coresight-cti.
>>>  
>>> +config CORESIGHT_TRBE
>>> +	bool "Trace Buffer Extension (TRBE) driver"
>>
>> Shouldn't that be "tristate"?
>>
>>> +	depends on ARM64
>>
>> I would make it dependent on ETMv4 as well since it can only be used by that
>> component.
>>
>>> +	help
>>> +	  This driver provides support for percpu Trace Buffer Extension (TRBE).
>>> +	  TRBE always needs to be used along with it's corresponding percpu ETE
>>> +	  component. ETE generates trace data which is then captured with TRBE.
>>> +	  Unlike traditional sink devices, TRBE is a CPU feature accessible via
>>> +	  system registers. But it's explicit dependency with trace unit (ETE)
>>> +	  requires it to be plugged in as a coresight sink device.
>>
>> Please add:
>>
>>           "To compile this driver as a module, choose M here: the
>>           module will be called coresight-trbe."
>>
>> I'm out of time for today, I will continue on Monday.
>>
>> Mathieu
>>
>>> +
>>>  config CORESIGHT_CTI_INTEGRATION_REGS
>>>  	bool "Access CTI CoreSight Integration Registers"
>>>  	depends on CORESIGHT_CTI
>>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
>>> index f20e357..d608165 100644
>>> --- a/drivers/hwtracing/coresight/Makefile
>>> +++ b/drivers/hwtracing/coresight/Makefile
>>> @@ -21,5 +21,6 @@ obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
>>>  obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
>>>  obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
>>>  obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
>>> +obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
>>>  coresight-cti-y := coresight-cti-core.o	coresight-cti-platform.o \
>>>  		   coresight-cti-sysfs.o
>>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
>>> new file mode 100644
>>> index 0000000..1464d8b
>>> --- /dev/null
>>> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
>>> @@ -0,0 +1,1023 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * This driver enables Trace Buffer Extension (TRBE) as a per-cpu coresight
>>> + * sink device could then pair with an appropriate per-cpu coresight source
>>> + * device (ETE) thus generating required trace data. Trace can be enabled
>>> + * via the perf framework.
>>> + *
>>> + * Copyright (C) 2020 ARM Ltd.
>>> + *
>>> + * Author: Anshuman Khandual <anshuman.khandual@arm.com>
>>> + */
>>> +#define DRVNAME "arm_trbe"
>>> +
>>> +#define pr_fmt(fmt) DRVNAME ": " fmt
>>> +
>>> +#include "coresight-trbe.h"
>>> +
>>> +#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
>>> +
>>> +/*
>>> + * A padding packet that will help the user space tools
>>> + * in skipping relevant sections in the captured trace
>>> + * data which could not be decoded. TRBE doesn't support
>>> + * formatting the trace data, unlike the legacy CoreSight
>>> + * sinks and thus we use ETE trace packets to pad the
>>> + * sections of the buffer.
>>> + */
>>> +#define ETE_IGNORE_PACKET 		0x70
>>> +
>>> +/*
>>> + * Minimum amount of meaningful trace will contain:
>>> + * A-Sync, Trace Info, Trace On, Address, Atom.
>>> + * This is about 44bytes of ETE trace. To be on
>>> + * the safer side, we assume 64bytes is the minimum
>>> + * space required for a meaningful session, before
>>> + * we hit a "WRAP" event.
>>> + */
>>> +#define TRBE_TRACE_MIN_BUF_SIZE		64
>>> +
>>> +enum trbe_fault_action {
>>> +	TRBE_FAULT_ACT_WRAP,
>>> +	TRBE_FAULT_ACT_SPURIOUS,
>>> +	TRBE_FAULT_ACT_FATAL,
>>> +};
>>> +
>>> +struct trbe_buf {
>>> +	unsigned long trbe_base;
>>> +	unsigned long trbe_limit;
>>> +	unsigned long trbe_write;
>>> +	int nr_pages;
>>> +	void **pages;
>>> +	bool snapshot;
>>> +	struct trbe_cpudata *cpudata;
>>> +};
>>> +
>>> +struct trbe_cpudata {
>>> +	bool trbe_dbm;
>>> +	u64 trbe_align;
>>> +	int cpu;
>>> +	enum cs_mode mode;
>>> +	struct trbe_buf *buf;
>>> +	struct trbe_drvdata *drvdata;
>>> +};
>>> +
>>> +struct trbe_drvdata {
>>> +	struct trbe_cpudata __percpu *cpudata;
>>> +	struct perf_output_handle __percpu **handle;
>>> +	struct hlist_node hotplug_node;
>>> +	int irq;
>>> +	cpumask_t supported_cpus;
>>> +	enum cpuhp_state trbe_online;
>>> +	struct platform_device *pdev;
>>> +};
>>> +
>>> +static int trbe_alloc_node(struct perf_event *event)
>>> +{
>>> +	if (event->cpu == -1)
>>> +		return NUMA_NO_NODE;
>>> +	return cpu_to_node(event->cpu);
>>> +}
>>> +
>>> +static void trbe_drain_buffer(void)
>>> +{
>>> +	asm(TSB_CSYNC);
>>> +	dsb(nsh);
>>> +}
>>> +
>>> +static void trbe_drain_and_disable_local(void)
>>> +{
>>> +	trbe_drain_buffer();
>>> +	write_sysreg_s(0, SYS_TRBLIMITR_EL1);
>>> +	isb();
>>> +}
>>> +
>>> +static void trbe_reset_local(void)
>>> +{
>>> +	trbe_drain_and_disable_local();
>>> +	write_sysreg_s(0, SYS_TRBPTR_EL1);
>>> +	write_sysreg_s(0, SYS_TRBBASER_EL1);
>>> +	write_sysreg_s(0, SYS_TRBSR_EL1);
>>> +}
>>> +
>>> +static void trbe_stop_and_truncate_event(struct perf_output_handle *handle)
>>> +{
>>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>>> +
>>> +	/*
>>> +	 * We cannot proceed with the buffer collection and we
>>> +	 * do not have any data for the current session. The
>>> +	 * etm_perf driver expects to close out the aux_buffer
>>> +	 * at event_stop(). So disable the TRBE here and leave
>>> +	 * the update_buffer() to return a 0 size.
>>> +	 */
>>> +	trbe_drain_and_disable_local();
>>> +	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
>>> +	*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
>>> +}
>>> +
>>> +/*
>>> + * TRBE Buffer Management
>>> + *
>>> + * The TRBE buffer spans from the base pointer till the limit pointer. When enabled,
>>> + * it starts writing trace data from the write pointer onward till the limit pointer.
>>> + * When the write pointer reaches the address just before the limit pointer, it gets
>>> + * wrapped around again to the base pointer. This is called a TRBE wrap event, which
>>> + * generates a maintenance interrupt when operated in WRAP or FILL mode. This driver
>>> + * uses FILL mode, where the TRBE stops the trace collection at wrap event. The IRQ
>>> + * handler updates the AUX buffer and re-enables the TRBE with updated WRITE and
>>> + * LIMIT pointers.
>>> + *
>>> + *	Wrap around with an IRQ
>>> + *	------ < ------ < ------- < ----- < -----
>>> + *	|					|
>>> + *	------ > ------ > ------- > ----- > -----
>>> + *
>>> + *	+---------------+-----------------------+
>>> + *	|		|			|
>>> + *	+---------------+-----------------------+
>>> + *	Base Pointer	Write Pointer		Limit Pointer
>>> + *
>>> + * The base and limit pointers always needs to be PAGE_SIZE aligned. But the write
>>> + * pointer can be aligned to the implementation defined TRBE trace buffer alignment
>>> + * as captured in trbe_cpudata->trbe_align.
>>> + *
>>> + *
>>> + *		head		tail		wakeup
>>> + *	+---------------------------------------+----- ~ ~ ------
>>> + *	|$$$$$$$|################|$$$$$$$$$$$$$$|		|
>>> + *	+---------------------------------------+----- ~ ~ ------
>>> + *	Base Pointer	Write Pointer		Limit Pointer
>>> + *
>>> + * The perf_output_handle indices (head, tail, wakeup) are monotonically increasing
>>> + * values which tracks all the driver writes and user reads from the perf auxiliary
>>> + * buffer. Generally [head..tail] is the area where the driver can write into unless
>>> + * the wakeup is behind the tail. Enabled TRBE buffer span needs to be adjusted and
>>> + * configured depending on the perf_output_handle indices, so that the driver does
>>> + * not override into areas in the perf auxiliary buffer which is being or yet to be
>>> + * consumed from the user space. The enabled TRBE buffer area is a moving subset of
>>> + * the allocated perf auxiliary buffer.
>>> + */
>>> +static void trbe_pad_buf(struct perf_output_handle *handle, int len)
>>> +{
>>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>>> +	u64 head = PERF_IDX2OFF(handle->head, buf);
>>> +
>>> +	memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
>>> +	if (!buf->snapshot)
>>> +		perf_aux_output_skip(handle, len);
>>> +}
>>> +
>>> +static unsigned long trbe_snapshot_offset(struct perf_output_handle *handle)
>>> +{
>>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>>> +
>>> +	/*
>>> +	 * The ETE trace has alignment synchronization packets allowing
>>> +	 * the decoder to reset in case of an overflow or corruption.
>>> +	 * So we can use the entire buffer for the snapshot mode.
>>> +	 */
>>> +	return buf->nr_pages * PAGE_SIZE;
>>> +}
>>> +
>>> +/*
>>> + * TRBE Limit Calculation
>>> + *
>>> + * The following markers are used to illustrate various TRBE buffer situations.
>>> + *
>>> + * $$$$ - Data area, unconsumed captured trace data, not to be overridden
>>> + * #### - Free area, enabled, trace will be written
>>> + * %%%% - Free area, disabled, trace will not be written
>>> + * ==== - Free area, padded with ETE_IGNORE_PACKET, trace will be skipped
>>> + */
>>> +static unsigned long __trbe_normal_offset(struct perf_output_handle *handle)
>>> +{
>>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>>> +	struct trbe_cpudata *cpudata = buf->cpudata;
>>> +	const u64 bufsize = buf->nr_pages * PAGE_SIZE;
>>> +	u64 limit = bufsize;
>>> +	u64 head, tail, wakeup;
>>> +
>>> +	head = PERF_IDX2OFF(handle->head, buf);
>>> +
>>> +	/*
>>> +	 *		head
>>> +	 *	------->|
>>> +	 *	|
>>> +	 *	head	TRBE align	tail
>>> +	 * +----|-------|---------------|-------+
>>> +	 * |$$$$|=======|###############|$$$$$$$|
>>> +	 * +----|-------|---------------|-------+
>>> +	 * trbe_base				trbe_base + nr_pages
>>> +	 *
>>> +	 * Perf aux buffer output head position can be misaligned depending on
>>> +	 * various factors including user space reads. In case misaligned, head
>>> +	 * needs to be aligned before TRBE can be configured. Pad the alignment
>>> +	 * gap with ETE_IGNORE_PACKET bytes that will be ignored by user tools
>>> +	 * and skip this section thus advancing the head.
>>> +	 */
>>> +	if (!IS_ALIGNED(head, cpudata->trbe_align)) {
>>> +		unsigned long delta = roundup(head, cpudata->trbe_align) - head;
>>> +
>>> +		delta = min(delta, handle->size);
>>> +		trbe_pad_buf(handle, delta);
>>> +		head = PERF_IDX2OFF(handle->head, buf);
>>> +	}
>>> +
>>> +	/*
>>> +	 *	head = tail (size = 0)
>>> +	 * +----|-------------------------------+
>>> +	 * |$$$$|$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$	|
>>> +	 * +----|-------------------------------+
>>> +	 * trbe_base				trbe_base + nr_pages
>>> +	 *
>>> +	 * Perf aux buffer does not have any space for the driver to write into.
>>> +	 * Just communicate trace truncation event to the user space by marking
>>> +	 * it with PERF_AUX_FLAG_TRUNCATED.
>>> +	 */
>>> +	if (!handle->size) {
>>> +		perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
>>> +		return 0;
>>> +	}
>>> +
>>> +	/* Compute the tail and wakeup indices now that we've aligned head */
>>> +	tail = PERF_IDX2OFF(handle->head + handle->size, buf);
>>> +	wakeup = PERF_IDX2OFF(handle->wakeup, buf);
>>> +
>>> +	/*
>>> +	 * Lets calculate the buffer area which TRBE could write into. There
>>> +	 * are three possible scenarios here. Limit needs to be aligned with
>>> +	 * PAGE_SIZE per the TRBE requirement. Always avoid clobbering the
>>> +	 * unconsumed data.
>>> +	 *
>>> +	 * 1) head < tail
>>> +	 *
>>> +	 *	head			tail
>>> +	 * +----|-----------------------|-------+
>>> +	 * |$$$$|#######################|$$$$$$$|
>>> +	 * +----|-----------------------|-------+
>>> +	 * trbe_base			limit	trbe_base + nr_pages
>>> +	 *
>>> +	 * TRBE could write into [head..tail] area. Unless the tail is right at
>>> +	 * the end of the buffer, neither an wrap around nor an IRQ is expected
>>> +	 * while being enabled.
>>> +	 *
>>> +	 * 2) head == tail
>>> +	 *
>>> +	 *	head = tail (size > 0)
>>> +	 * +----|-------------------------------+
>>> +	 * |%%%%|###############################|
>>> +	 * +----|-------------------------------+
>>> +	 * trbe_base				limit = trbe_base + nr_pages
>>> +	 *
>>> +	 * TRBE should just write into [head..base + nr_pages] area even though
>>> +	 * the entire buffer is empty. Reason being, when the trace reaches the
>>> +	 * end of the buffer, it will just wrap around with an IRQ giving an
>>> +	 * opportunity to reconfigure the buffer.
>>> +	 *
>>> +	 * 3) tail < head
>>> +	 *
>>> +	 *	tail			head
>>> +	 * +----|-----------------------|-------+
>>> +	 * |%%%%|$$$$$$$$$$$$$$$$$$$$$$$|#######|
>>> +	 * +----|-----------------------|-------+
>>> +	 * trbe_base				limit = trbe_base + nr_pages
>>> +	 *
>>> +	 * TRBE should just write into [head..base + nr_pages] area even though
>>> +	 * the [trbe_base..tail] is also empty. Reason being, when the trace
>>> +	 * reaches the end of the buffer, it will just wrap around with an IRQ
>>> +	 * giving an opportunity to reconfigure the buffer.
>>> +	 */
>>> +	if (head < tail)
>>> +		limit = round_down(tail, PAGE_SIZE);
>>> +
>>> +	/*
>>> +	 * Wakeup may be arbitrarily far into the future. If it's not in the
>>> +	 * current generation, either we'll wrap before hitting it, or it's
>>> +	 * in the past and has been handled already.
>>> +	 *
>>> +	 * If there's a wakeup before we wrap, arrange to be woken up by the
>>> +	 * page boundary following it. Keep the tail boundary if that's lower.
>>> +	 *
>>> +	 *	head		wakeup	tail
>>> +	 * +----|---------------|-------|-------+
>>> +	 * |$$$$|###############|%%%%%%%|$$$$$$$|
>>> +	 * +----|---------------|-------|-------+
>>> +	 * trbe_base		limit		trbe_base + nr_pages
>>> +	 */
>>> +	if (handle->wakeup < (handle->head + handle->size) && head <= wakeup)
>>> +		limit = min(limit, round_up(wakeup, PAGE_SIZE));
>>> +
>>> +	/*
>>> +	 * There are two situation when this can happen i.e limit is before
>>> +	 * the head and hence TRBE cannot be configured.
>>> +	 *
>>> +	 * 1) head < tail (aligned down with PAGE_SIZE) and also they are both
>>> +	 * within the same PAGE size range.
>>> +	 *
>>> +	 *			PAGE_SIZE
>>> +	 *		|----------------------|
>>> +	 *
>>> +	 *		limit	head	tail
>>> +	 * +------------|------|--------|-------+
>>> +	 * |$$$$$$$$$$$$$$$$$$$|========|$$$$$$$|
>>> +	 * +------------|------|--------|-------+
>>> +	 * trbe_base				trbe_base + nr_pages
>>> +	 *
>>> +	 * 2) head < wakeup (aligned up with PAGE_SIZE) < tail and also both
>>> +	 * head and wakeup are within same PAGE size range.
>>> +	 *
>>> +	 *		PAGE_SIZE
>>> +	 *	|----------------------|
>>> +	 *
>>> +	 *	limit	head	wakeup  tail
>>> +	 * +----|------|-------|--------|-------+
>>> +	 * |$$$$$$$$$$$|=======|========|$$$$$$$|
>>> +	 * +----|------|-------|--------|-------+
>>> +	 * trbe_base				trbe_base + nr_pages
>>> +	 */
>>> +	if (limit > head)
>>> +		return limit;
>>> +
>>> +	trbe_pad_buf(handle, handle->size);
>>> +	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
>>> +	return 0;
>>> +}
>>> +
>>> +static unsigned long trbe_normal_offset(struct perf_output_handle *handle)
>>> +{
>>> +	struct trbe_buf *buf = perf_get_aux(handle);
>>> +	u64 limit = __trbe_normal_offset(handle);
>>> +	u64 head = PERF_IDX2OFF(handle->head, buf);
>>> +
>>> +	/*
>>> +	 * If the head is too close to the limit and we don't
>>> +	 * have space for a meaningful run, we rather pad it
>>> +	 * and start fresh.
>>> +	 */
>>> +	if (limit && (limit - head < TRBE_TRACE_MIN_BUF_SIZE)) {
>>> +		trbe_pad_buf(handle, limit - head);
>>> +		limit = __trbe_normal_offset(handle);
>>> +	}
>>> +	return limit;
>>> +}
>>> +
>>> +static unsigned long compute_trbe_buffer_limit(struct perf_output_handle *handle)
>>> +{
>>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>>> +	unsigned long offset;
>>> +
>>> +	if (buf->snapshot)
>>> +		offset = trbe_snapshot_offset(handle);
>>> +	else
>>> +		offset = trbe_normal_offset(handle);
>>> +	return buf->trbe_base + offset;
>>> +}
>>> +
>>> +static void clr_trbe_status(void)
>>> +{
>>> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
>>> +
>>> +	WARN_ON(is_trbe_enabled());
>>> +	trbsr &= ~TRBSR_IRQ;
>>> +	trbsr &= ~TRBSR_TRG;
>>> +	trbsr &= ~TRBSR_WRAP;
>>> +	trbsr &= ~(TRBSR_EC_MASK << TRBSR_EC_SHIFT);
>>> +	trbsr &= ~(TRBSR_BSC_MASK << TRBSR_BSC_SHIFT);
>>> +	trbsr &= ~TRBSR_STOP;
>>> +	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
>>> +}
>>> +
>>> +static void set_trbe_limit_pointer_enabled(unsigned long addr)
>>> +{
>>> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
>>> +
>>> +	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
>>> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
>>> +
>>> +	trblimitr &= ~TRBLIMITR_NVM;
>>> +	trblimitr &= ~(TRBLIMITR_FILL_MODE_MASK << TRBLIMITR_FILL_MODE_SHIFT);
>>> +	trblimitr &= ~(TRBLIMITR_TRIG_MODE_MASK << TRBLIMITR_TRIG_MODE_SHIFT);
>>> +	trblimitr &= ~(TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT);
>>> +
>>> +	/*
>>> +	 * Fill trace buffer mode is used here while configuring the
>>> +	 * TRBE for trace capture. In this particular mode, the trace
>>> +	 * collection is stopped and a maintenance interrupt is raised
>>> +	 * when the current write pointer wraps. This pause in trace
>>> +	 * collection gives the software an opportunity to capture the
>>> +	 * trace data in the interrupt handler, before reconfiguring
>>> +	 * the TRBE.
>>> +	 */
>>> +	trblimitr |= (TRBE_FILL_MODE_FILL & TRBLIMITR_FILL_MODE_MASK) << TRBLIMITR_FILL_MODE_SHIFT;
>>> +
>>> +	/*
>>> +	 * Trigger mode is not used here while configuring the TRBE for
>>> +	 * the trace capture. Hence just keep this in the ignore mode.
>>> +	 */
>>> +	trblimitr |= (TRBE_TRIG_MODE_IGNORE & TRBLIMITR_TRIG_MODE_MASK) << TRBLIMITR_TRIG_MODE_SHIFT;
>>> +	trblimitr |= (addr & PAGE_MASK);
>>> +
>>> +	trblimitr |= TRBLIMITR_ENABLE;
>>> +	write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
>>> +}
>>> +
>>> +static void trbe_enable_hw(struct trbe_buf *buf)
>>> +{
>>> +	WARN_ON(buf->trbe_write < buf->trbe_base);
>>> +	WARN_ON(buf->trbe_write >= buf->trbe_limit);
>>> +	set_trbe_disabled();
>>> +	isb();
>>> +	clr_trbe_status();
>>> +	set_trbe_base_pointer(buf->trbe_base);
>>> +	set_trbe_write_pointer(buf->trbe_write);
>>> +
>>> +	/*
>>> +	 * Synchronize all the register updates
>>> +	 * till now before enabling the TRBE.
>>> +	 */
>>> +	isb();
>>> +	set_trbe_limit_pointer_enabled(buf->trbe_limit);
>>> +
>>> +	/* Synchronize the TRBE enable event */
>>> +	isb();
>>> +}
>>> +
>>> +static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
>>> +				   struct perf_event *event, void **pages,
>>> +				   int nr_pages, bool snapshot)
>>> +{
>>> +	struct trbe_buf *buf;
>>> +	struct page **pglist;
>>> +	int i;
>>> +
>>> +	/*
>>> +	 * TRBE LIMIT and TRBE WRITE pointers must be page aligned. But with
>>> +	 * just a single page, there is not much room left while writing into
>>> +	 * a partially filled TRBE buffer. Hence restrict the minimum buffer
>>> +	 * size as two pages.
>>> +	 */
>>> +	if (nr_pages < 2)
>>> +		return NULL;
>>> +
>>> +	buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
>>> +	if (IS_ERR(buf))
>>> +		return ERR_PTR(-ENOMEM);
>>> +
>>> +	pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
>>> +	if (IS_ERR(pglist)) {
>>> +		kfree(buf);
>>> +		return ERR_PTR(-ENOMEM);
>>> +	}
>>> +
>>> +	for (i = 0; i < nr_pages; i++)
>>> +		pglist[i] = virt_to_page(pages[i]);
>>> +
>>> +	buf->trbe_base = (unsigned long) vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
>>> +	if (IS_ERR((void *)buf->trbe_base)) {
>>> +		kfree(pglist);
>>> +		kfree(buf);
>>> +		return ERR_PTR(buf->trbe_base);
>>> +	}
>>> +	buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
>>> +	buf->trbe_write = buf->trbe_base;
>>> +	buf->snapshot = snapshot;
>>> +	buf->nr_pages = nr_pages;
>>> +	buf->pages = pages;
>>> +	kfree(pglist);
>>> +	return buf;
>>> +}
>>> +
>>> +void arm_trbe_free_buffer(void *config)
>>> +{
>>> +	struct trbe_buf *buf = config;
>>> +
>>> +	vunmap((void *)buf->trbe_base);
>>> +	kfree(buf);
>>> +}
>>> +
>>> +static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
>>> +					    struct perf_output_handle *handle,
>>> +					    void *config)
>>> +{
>>> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
>>> +	struct trbe_buf *buf = config;
>>> +	unsigned long size, offset;
>>> +
>>> +	WARN_ON(buf->cpudata != cpudata);
>>> +	WARN_ON(cpudata->cpu != smp_processor_id());
>>> +	WARN_ON(cpudata->drvdata != drvdata);
>>> +	if (cpudata->mode != CS_MODE_PERF)
>>> +		return -EINVAL;
>>> +
>>> +	/*
>>> +	 * If the TRBE was disabled due to lack of space in the AUX buffer or a
>>> +	 * spurious fault, the driver leaves it disabled, truncating the buffer.
>>> +	 * Since the etm_perf driver expects to close out the AUX buffer, the
>>> +	 * driver skips it. Thus, just pass in 0 size here to indicate that the
>>> +	 * buffer was truncated.
>>> +	 */
>>> +	if (!is_trbe_enabled())
>>> +		return 0;
>>> +	/*
>>> +	 * perf handle structure needs to be shared with the TRBE IRQ handler for
>>> +	 * capturing trace data and restarting the handle. There is a probability
>>> +	 * of an undefined reference based crash when etm event is being stopped
>>> +	 * while a TRBE IRQ also getting processed. This happens due the release
>>> +	 * of perf handle via perf_aux_output_end() in etm_event_stop(). Stopping
>>> +	 * the TRBE here will ensure that no IRQ could be generated when the perf
>>> +	 * handle gets freed in etm_event_stop().
>>> +	 */
>>> +	trbe_drain_and_disable_local();
>>> +	offset = get_trbe_write_pointer() - get_trbe_base_pointer();
>>> +	size = offset - PERF_IDX2OFF(handle->head, buf);
>>> +	if (buf->snapshot)
>>> +		handle->head += size;
>>> +	return size;
>>> +}
>>> +
>>> +static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)
>>> +{
>>> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
>>> +	struct perf_output_handle *handle = data;
>>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>>> +
>>> +	WARN_ON(cpudata->cpu != smp_processor_id());
>>> +	WARN_ON(cpudata->drvdata != drvdata);
>>> +	if (mode != CS_MODE_PERF)
>>> +		return -EINVAL;
>>> +
>>> +	*this_cpu_ptr(drvdata->handle) = handle;
>>> +	cpudata->buf = buf;
>>> +	cpudata->mode = mode;
>>> +	buf->cpudata = cpudata;
>>> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
>>> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
>>> +	if (buf->trbe_limit == buf->trbe_base) {
>>> +		trbe_stop_and_truncate_event(handle);
>>> +		return 0;
>>> +	}
>>> +	trbe_enable_hw(buf);
>>> +	return 0;
>>> +}
>>> +
>>> +static int arm_trbe_disable(struct coresight_device *csdev)
>>> +{
>>> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
>>> +	struct trbe_buf *buf = cpudata->buf;
>>> +
>>> +	WARN_ON(buf->cpudata != cpudata);
>>> +	WARN_ON(cpudata->cpu != smp_processor_id());
>>> +	WARN_ON(cpudata->drvdata != drvdata);
>>> +	if (cpudata->mode != CS_MODE_PERF)
>>> +		return -EINVAL;
>>> +
>>> +	trbe_drain_and_disable_local();
>>> +	buf->cpudata = NULL;
>>> +	cpudata->buf = NULL;
>>> +	cpudata->mode = CS_MODE_DISABLED;
>>> +	return 0;
>>> +}
>>> +
>>> +static void trbe_handle_spurious(struct perf_output_handle *handle)
>>> +{
>>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>>> +
>>> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
>>> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
>>> +	if (buf->trbe_limit == buf->trbe_base) {
>>> +		trbe_drain_and_disable_local();
>>> +		return;
>>> +	}
>>> +	trbe_enable_hw(buf);
>>> +}
>>> +
>>> +static void trbe_handle_overflow(struct perf_output_handle *handle)
>>> +{
>>> +	struct perf_event *event = handle->event;
>>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>>> +	unsigned long offset, size;
>>> +	struct etm_event_data *event_data;
>>> +
>>> +	offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
>>> +	size = offset - PERF_IDX2OFF(handle->head, buf);
>>> +	if (buf->snapshot)
>>> +		handle->head = offset;
>>> +	perf_aux_output_end(handle, size);
>>> +
>>> +	event_data = perf_aux_output_begin(handle, event);
>>> +	if (!event_data) {
>>> +		trbe_drain_and_disable_local();
>>> +		*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
>>> +		return;
>>> +	}
>>> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
>>> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
>>> +	if (buf->trbe_limit == buf->trbe_base) {
>>> +		trbe_stop_and_truncate_event(handle);
>>> +		return;
>>> +	}
>>> +	*this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;
>>> +	trbe_enable_hw(buf);
>>> +}
>>> +
>>> +static bool is_perf_trbe(struct perf_output_handle *handle)
>>> +{
>>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>>> +	struct trbe_cpudata *cpudata = buf->cpudata;
>>> +	struct trbe_drvdata *drvdata = cpudata->drvdata;
>>> +	int cpu = smp_processor_id();
>>> +
>>> +	WARN_ON(buf->trbe_base != get_trbe_base_pointer());
>>> +	WARN_ON(buf->trbe_limit != get_trbe_limit_pointer());
>>> +
>>> +	if (cpudata->mode != CS_MODE_PERF)
>>> +		return false;
>>> +
>>> +	if (cpudata->cpu != cpu)
>>> +		return false;
>>> +
>>> +	if (!cpumask_test_cpu(cpu, &drvdata->supported_cpus))
>>> +		return false;
>>> +
>>> +	return true;
>>> +}
>>> +
>>> +static enum trbe_fault_action trbe_get_fault_act(struct perf_output_handle *handle)
>>> +{
>>> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
>>> +	int ec = get_trbe_ec(trbsr);
>>> +	int bsc = get_trbe_bsc(trbsr);
>>> +
>>> +	WARN_ON(is_trbe_running(trbsr));
>>> +	if (is_trbe_trg(trbsr) || is_trbe_abort(trbsr))
>>> +		return TRBE_FAULT_ACT_FATAL;
>>> +
>>> +	if ((ec == TRBE_EC_STAGE1_ABORT) || (ec == TRBE_EC_STAGE2_ABORT))
>>> +		return TRBE_FAULT_ACT_FATAL;
>>> +
>>> +	if (is_trbe_wrap(trbsr) && (ec == TRBE_EC_OTHERS) && (bsc == TRBE_BSC_FILLED)) {
>>> +		if (get_trbe_write_pointer() == get_trbe_base_pointer())
>>> +			return TRBE_FAULT_ACT_WRAP;
>>> +	}
>>> +	return TRBE_FAULT_ACT_SPURIOUS;
>>> +}
>>> +
>>> +static irqreturn_t arm_trbe_irq_handler(int irq, void *dev)
>>> +{
>>> +	struct perf_output_handle **handle_ptr = dev;
>>> +	struct perf_output_handle *handle = *handle_ptr;
>>> +	enum trbe_fault_action act;
>>> +
>>> +	WARN_ON(!is_trbe_irq(read_sysreg_s(SYS_TRBSR_EL1)));
>>> +	clr_trbe_irq();
>>> +
>>> +	/*
>>> +	 * Ensure the trace is visible to the CPUs and
>>> +	 * any external aborts have been resolved.
>>> +	 */
>>> +	trbe_drain_buffer();
>>> +	isb();
>>> +
>>> +	if (!perf_get_aux(handle))
>>> +		return IRQ_NONE;
>>> +
>>> +	if (!is_perf_trbe(handle))
>>> +		return IRQ_NONE;
>>> +
>>> +	irq_work_run();
> 
> There is a comment in the SPE driver about this.  Since this driver closely
> follows that implementation it would be nice to have the comments as well.
> Otherwise the reader has to constantly go back to the original driver.

Sure, will add the following comment before irq_work_run().

        /*
         * Ensure perf callbacks have completed, which may disable the
         * profiling buffer in response to a TRUNCATION flag.
         */

> 
> I will come back to this function later.

Okay.

> 
>>> +
>>> +	act = trbe_get_fault_act(handle);
>>> +	switch (act) {
>>> +	case TRBE_FAULT_ACT_WRAP:
>>> +		trbe_handle_overflow(handle);
>>> +		break;
>>> +	case TRBE_FAULT_ACT_SPURIOUS:
>>> +		trbe_handle_spurious(handle);
>>> +		break;
>>> +	case TRBE_FAULT_ACT_FATAL:
>>> +		trbe_stop_and_truncate_event(handle);
>>> +		break;
>>> +	}
>>> +	return IRQ_HANDLED;
>>> +}
>>> +
>>> +static const struct coresight_ops_sink arm_trbe_sink_ops = {
>>> +	.enable		= arm_trbe_enable,
>>> +	.disable	= arm_trbe_disable,
>>> +	.alloc_buffer	= arm_trbe_alloc_buffer,
>>> +	.free_buffer	= arm_trbe_free_buffer,
>>> +	.update_buffer	= arm_trbe_update_buffer,
>>> +};
>>> +
>>> +static const struct coresight_ops arm_trbe_cs_ops = {
>>> +	.sink_ops	= &arm_trbe_sink_ops,
>>> +};
>>> +
>>> +static ssize_t align_show(struct device *dev, struct device_attribute *attr, char *buf)
>>> +{
>>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
>>> +
>>> +	return sprintf(buf, "%llx\n", cpudata->trbe_align);
>>> +}
>>> +static DEVICE_ATTR_RO(align);
>>> +
>>> +static ssize_t dbm_show(struct device *dev, struct device_attribute *attr, char *buf)
>>> +{
>>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
>>> +
>>> +	return sprintf(buf, "%d\n", cpudata->trbe_dbm);
>>> +}
>>> +static DEVICE_ATTR_RO(dbm);
>>> +
>>> +static struct attribute *arm_trbe_attrs[] = {
>>> +	&dev_attr_align.attr,
>>> +	&dev_attr_dbm.attr,
>>> +	NULL,
>>> +};
>>> +
>>> +static const struct attribute_group arm_trbe_group = {
>>> +	.attrs = arm_trbe_attrs,
>>> +};
>>> +
>>> +static const struct attribute_group *arm_trbe_groups[] = {
>>> +	&arm_trbe_group,
>>> +	NULL,
>>> +};
>>> +
>>> +static void arm_trbe_probe_coresight_cpu(void *info)
>>> +{
>>> +	struct trbe_drvdata *drvdata = info;
>>> +	struct coresight_desc desc = { 0 };
>>> +	int cpu = smp_processor_id();
>>> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
>>> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
>>> +	u64 trbidr = read_sysreg_s(SYS_TRBIDR_EL1);
>>> +	struct device *dev;
>>> +
>>> +	if (WARN_ON(!cpudata))
>>> +		goto cpu_clear;
> 
> Where was the memory for cpudata allocated?  As far as I can tell, at this time
> it is just a pointer that was not allocated and as such it should be NULL.

cpudata gets allocated in arm_trbe_probe_coresight() just before calling
individual CPU based probes i.e arm_trbe_probe_coresight_cpu() directly
and via smp_call_function_many().

arm_trbe_device_probe()
	arm_trbe_probe_coresight()
		arm_trbe_probe_coresight_cpu()

> 
>>> +
>>> +	if (trbe_csdev)
>>> +		return;
>>> +
>>> +	cpudata->cpu = smp_processor_id();
> 
> Why call this again when you already did above?  And how is

Right, this is redundant. Will just assign it as cpu which has already
been computed.

> arm_trbe_probe_coresight_cpu() is called for every CPU in the system?

During boot in arm_trbe_probe_coresight(), it is called once directly on
the executing cpu and on all other via smp_call_function_many().

> 
>>> +	cpudata->drvdata = drvdata;
>>> +	dev = &cpudata->drvdata->pdev->dev;
>>> +
>>> +	if (!is_trbe_available()) {
>>> +		pr_err("TRBE is not implemented on cpu %d\n", cpudata->cpu);
>>> +		goto cpu_clear;
>>> +	}
>>> +
>>> +	if (!is_trbe_programmable(trbidr)) {
>>> +		pr_err("TRBE is owned in higher exception level on cpu %d\n", cpudata->cpu);
>>> +		goto cpu_clear;
>>> +	}
>>> +	desc.name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", DRVNAME, smp_processor_id());
>>> +	if (IS_ERR(desc.name))
>>> +		goto cpu_clear;
>>> +
>>> +	desc.type = CORESIGHT_DEV_TYPE_SINK;
>>> +	desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
>>> +	desc.ops = &arm_trbe_cs_ops;
>>> +	desc.pdata = dev_get_platdata(dev);
>>> +	desc.groups = arm_trbe_groups;
>>> +	desc.dev = dev;
>>> +	trbe_csdev = coresight_register(&desc);
>>> +	if (IS_ERR(trbe_csdev))
>>> +		goto cpu_clear;
>>> +
>>> +	dev_set_drvdata(&trbe_csdev->dev, cpudata);
>>> +	cpudata->trbe_dbm = get_trbe_flag_update(trbidr);
>>> +	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
>>> +	if (cpudata->trbe_align > SZ_2K) {
>>> +		pr_err("Unsupported alignment on cpu %d\n", cpudata->cpu);
>>> +		goto cpu_clear;
>>> +	}
>>> +	per_cpu(csdev_sink, cpu) = trbe_csdev;
>>> +	trbe_reset_local();
>>> +	enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
>>> +	return;
>>> +cpu_clear:
>>> +	cpumask_clear_cpu(cpudata->cpu, &cpudata->drvdata->supported_cpus);
>>> +}
>>> +
>>> +static void arm_trbe_remove_coresight_cpu(void *info)
>>> +{
>>> +	int cpu = smp_processor_id();
>>> +	struct trbe_drvdata *drvdata = info;
>>> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
>>> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
>>> +
>>> +	if (trbe_csdev) {
>>> +		coresight_unregister(trbe_csdev);
>>> +		cpudata->drvdata = NULL;
>>> +		per_cpu(csdev_sink, cpu) = NULL;
>>> +	}
>>> +	disable_percpu_irq(drvdata->irq);
>>> +	trbe_reset_local();
>>> +}
>>> +
>>> +static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata)
>>> +{
>>> +	drvdata->cpudata = alloc_percpu(typeof(*drvdata->cpudata));
>>> +	if (IS_ERR(drvdata->cpudata))
>>> +		return PTR_ERR(drvdata->cpudata);
>>> +
>>> +	arm_trbe_probe_coresight_cpu(drvdata);
>>> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_probe_coresight_cpu, drvdata, 1);
>>> +	return 0;
>>> +}
>>> +
>>> +static int arm_trbe_remove_coresight(struct trbe_drvdata *drvdata)
>>> +{
>>> +	arm_trbe_remove_coresight_cpu(drvdata);
>>> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_remove_coresight_cpu, drvdata, 1);
>>> +	free_percpu(drvdata->cpudata);
>>> +	return 0;
>>> +}
>>> +
>>> +static int arm_trbe_cpu_startup(unsigned int cpu, struct hlist_node *node)
>>> +{
>>> +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
>>> +
>>> +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
>>> +		if (!per_cpu(csdev_sink, cpu)) {
>>> +			arm_trbe_probe_coresight_cpu(drvdata);
>>> +		} else {
>>> +			trbe_reset_local();
>>> +			enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
>>> +		}
>>> +	}
>>> +	return 0;
>>> +}
>>> +
>>> +static int arm_trbe_cpu_teardown(unsigned int cpu, struct hlist_node *node)
>>> +{
>>> +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
>>> +
>>> +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
>>> +		disable_percpu_irq(drvdata->irq);
>>> +		trbe_reset_local();
>>> +	}
>>> +	return 0;
>>> +}
>>> +
>>> +static int arm_trbe_probe_cpuhp(struct trbe_drvdata *drvdata)
>>> +{
>>> +	enum cpuhp_state trbe_online;
>>> +
>>> +	trbe_online = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
>>> +					arm_trbe_cpu_startup, arm_trbe_cpu_teardown);
>>> +	if (trbe_online < 0)
>>> +		return -EINVAL;
>>> +
>>> +	if (cpuhp_state_add_instance(trbe_online, &drvdata->hotplug_node))
>>> +		return -EINVAL;
>>> +
>>> +	drvdata->trbe_online = trbe_online;
>>> +	return 0;
>>> +}
>>> +
>>> +static void arm_trbe_remove_cpuhp(struct trbe_drvdata *drvdata)
>>> +{
>>> +	cpuhp_remove_multi_state(drvdata->trbe_online);
>>> +}
>>> +
>>> +static int arm_trbe_probe_irq(struct platform_device *pdev,
>>> +			      struct trbe_drvdata *drvdata)
>>> +{
>>> +	drvdata->irq = platform_get_irq(pdev, 0);
>>> +	if (!drvdata->irq) {
> 
> Please use function platform_get_irq() properly - there is even an example on
> how to do so in the documentation section of the function.

The documentation says, the format should be.

int irq = platform_get_irq(pdev, 0);
if (irq < 0)
	return irq;

Will change the conditional check above.

> 
>>> +		pr_err("IRQ not found for the platform device\n");
>>> +		return -ENXIO;
> 
> Why use a different error code?

We could return the irq (which is < 0) but followed the SPE
driver which returns ENXIO here. Happy to change either way.

> 
>>> +	}
>>> +
>>> +	if (!irq_is_percpu(drvdata->irq)) {
>>> +		pr_err("IRQ is not a PPI\n");
>>> +		return -EINVAL;
>>> +	}
>>> +
>>> +	if (irq_get_percpu_devid_partition(drvdata->irq, &drvdata->supported_cpus))
>>> +		return -EINVAL;
>>> +
>>> +	drvdata->handle = alloc_percpu(typeof(*drvdata->handle));
>>> +	if (!drvdata->handle)
>>> +		return -ENOMEM;
>>> +
>>> +	if (request_percpu_irq(drvdata->irq, arm_trbe_irq_handler, DRVNAME, drvdata->handle)) {
>>> +		free_percpu(drvdata->handle);
>>> +		return -EINVAL;
> 
> Here too you need to use the error code from the calling function rather than
> making your own.  Please revise for the entire patch.

Okay, will capture the return value from request_percpu_irq() and
return the same when it is an error case i.e being positive.

> 
>>> +	}
>>> +	return 0;
>>> +}
>>> +
>>> +static void arm_trbe_remove_irq(struct trbe_drvdata *drvdata)
>>> +{
>>> +	free_percpu_irq(drvdata->irq, drvdata->handle);
>>> +	free_percpu(drvdata->handle);
>>> +}
>>> +
>>> +static int arm_trbe_device_probe(struct platform_device *pdev)
>>> +{
>>> +	struct coresight_platform_data *pdata;
>>> +	struct trbe_drvdata *drvdata;
>>> +	struct device *dev = &pdev->dev;
>>> +	int ret;
>>> +
>>> +	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
>>> +	if (IS_ERR(drvdata))
>>> +		return -ENOMEM;
> 
>         if (!drvdata)

Changed.

> 
>>> +
>>> +	pdata = coresight_get_platform_data(dev);
>>> +	if (IS_ERR(pdata)) {
>>> +		kfree(drvdata);
> 
> No need to do this since devm_kzalloc() was used above.

Suzuki had pointed out these issues, have already incorporated them i.e
dropped kfree() here.

> 
>>> +		return -ENOMEM;
> 
> Why not using the error from coresight_get_platform_data() instead of
> masking it?

Okay, will return PTR_ERR(pdata) instead.

> 
>>> +	}
>>> +
>>> +	dev_set_drvdata(dev, drvdata);
>>> +	dev->platform_data = pdata;
>>> +	drvdata->pdev = pdev;
>>> +	ret = arm_trbe_probe_irq(pdev, drvdata);
>>> +	if (ret)
>>> +		goto irq_failed;
>>> +
>>> +	ret = arm_trbe_probe_coresight(drvdata);
>>> +	if (ret)
>>> +		goto probe_failed;
>>> +
>>> +	ret = arm_trbe_probe_cpuhp(drvdata);
>>> +	if (ret)
>>> +		goto cpuhp_failed;
>>> +
>>> +	return 0;
>>> +cpuhp_failed:
>>> +	arm_trbe_remove_coresight(drvdata);
>>> +probe_failed:
>>> +	arm_trbe_remove_irq(drvdata);
>>> +irq_failed:
>>> +	kfree(pdata);
>>> +	kfree(drvdata);
> 
> Same here - both @pdata and @drvdata have been allocated by devm_kzalloc().
> devm_kzalloc().

Dropped these kfree() statements.

- Anshuman

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 06/14] dts: bindings: Document device tree bindings for ETE
  2021-02-09 19:00   ` Rob Herring
@ 2021-02-10 12:33     ` Suzuki K Poulose
  2021-02-18 18:33       ` Rob Herring
  0 siblings, 1 reply; 90+ messages in thread
From: Suzuki K Poulose @ 2021-02-10 12:33 UTC (permalink / raw)
  To: Rob Herring, Anshuman Khandual
  Cc: linux-arm-kernel, coresight, mathieu.poirier, mike.leach,
	lcherian, linux-kernel, devicetree

Hi Rob

On 2/9/21 7:00 PM, Rob Herring wrote:
> On Wed, Jan 27, 2021 at 02:25:30PM +0530, Anshuman Khandual wrote:
>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>
>> Document the device tree bindings for Embedded Trace Extensions.
>> ETE can be connected to legacy coresight components and thus
>> could optionally contain a connection graph as described by
>> the CoreSight bindings.
>>
>> Cc: devicetree@vger.kernel.org
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Cc: Rob Herring <robh@kernel.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> Changes in V3:
>>
>> - Fixed all DT yaml semantics problems
>>
>>   Documentation/devicetree/bindings/arm/ete.yaml | 74 ++++++++++++++++++++++++++
>>   1 file changed, 74 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/arm/ete.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/ete.yaml b/Documentation/devicetree/bindings/arm/ete.yaml
>> new file mode 100644
>> index 0000000..edc1fe2
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/ete.yaml
>> @@ -0,0 +1,74 @@
>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
>> +# Copyright 2021, Arm Ltd
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/arm/ete.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: ARM Embedded Trace Extensions
>> +
>> +maintainers:
>> +  - Suzuki K Poulose <suzuki.poulose@arm.com>
>> +  - Mathieu Poirier <mathieu.poirier@linaro.org>
>> +
>> +description: |
>> +  Arm Embedded Trace Extension(ETE) is a per CPU trace component that
>> +  allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
>> +  architecture and has extended support for future architecture changes.
>> +  The trace generated by the ETE could be stored via legacy CoreSight
>> +  components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
>> +  Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
>> +  legacy CoreSight components, a node must be listed per instance, along
>> +  with any optional connection graph as per the coresight bindings.
>> +  See bindings/arm/coresight.txt.
>> +
>> +properties:
>> +  $nodename:
>> +    pattern: "^ete([0-9a-f]+)$"
>> +  compatible:
>> +    items:
>> +      - const: arm,embedded-trace-extension
>> +
>> +  cpu:
> 
> We've already established 'cpus' for this purpose.
> 

Please see : https://lkml.kernel.org/r/9417218b-6eda-373b-a2cb-869089ffc7cd@arm.com
for my response in the previous version to this and the one with out-ports.

>> +    description: |
>> +      Handle to the cpu this ETE is bound to.
>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +
>> +  out-ports:
>> +    type: object
> 
> Replace with: $ref: /schemas/graph.yaml#/properties/ports

So, just to confirm again :
The CoreSight graph bindings expect the input ports and output ports
grouped under in-ports{} and out-ports{} respectively to avoid having
to specify the direction of the ports in the individual "port" nodes.
i.e

in-ports {

	property: ports
	  OR
	property: port

	required:
		OneOf:
			ports
			port
}

out-ports {

	# same as above
}

So thats why I added out-ports as a new object, where the ports/port
could be a child node.

Ideally the definition of out-ports /in-ports should go to a common schema
for CoreSight bindings, when we move to Yaml for the existing bindings,
which will follow in a separate series, later.

> 
>> +    description: |
>> +      Output connections from the ETE to legacy CoreSight trace bus.
>> +    properties:
>> +      port:
>> +        $ref: /schemas/graph.yaml#/properties/port
> 
> Actually, if only 1 port ever, you can drop 'out-ports' and just have
> 'port'. Not sure though if the coresight stuff depends on 'out-ports'.
> 

Cheers
Suzuki

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-02-10  4:12       ` Anshuman Khandual
@ 2021-02-10 16:54         ` Mathieu Poirier
  0 siblings, 0 replies; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-10 16:54 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel

On Wed, Feb 10, 2021 at 09:42:29AM +0530, Anshuman Khandual wrote:
> 
> 
> On 2/9/21 11:09 PM, Mathieu Poirier wrote:
> > On Fri, Feb 05, 2021 at 10:53:30AM -0700, Mathieu Poirier wrote:
> >> On Wed, Jan 27, 2021 at 02:25:35PM +0530, Anshuman Khandual wrote:
> >>> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
> >>> accessible via the system registers. The TRBE supports different addressing
> >>> modes including CPU virtual address and buffer modes including the circular
> >>> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
> >>> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
> >>> access to the trace buffer could be prohibited by a higher exception level
> >>> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
> >>> private interrupt (PPI) on address translation errors and when the buffer
> >>> is full. Overall implementation here is inspired from the Arm SPE driver.
> >>>
> >>
> >> I got this message when applying the patch: 
> >>
> >> Applying: coresight: sink: Add TRBE driver
> >> .git/rebase-apply/patch:76: new blank line at EOF.
> >> +
> >> warning: 1 line adds whitespace errors.
> >>  
> >>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> >>> Cc: Mike Leach <mike.leach@linaro.org>
> >>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> >>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> >>> ---
> >>> Changes in V3:
> >>>
> >>> - Added new DT bindings document TRBE.yaml
> >>> - Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3
> >>> - Dropped isb() from trbe_reset_local()
> >>> - Dropped gap between (void *) and buf->trbe_base
> >>> - Changed 'int' to 'unsigned int' in is_trbe_available()
> >>> - Dropped unused function set_trbe_running(), set_trbe_virtual_mode(),
> >>>   set_trbe_enabled() and set_trbe_limit_pointer()
> >>> - Changed get_trbe_flag_update(), is_trbe_programmable() and
> >>>   get_trbe_address_align() to accept TRBIDR value
> >>> - Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), is_trbe_trg(),
> >>>   is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value
> >>> - Dropped snapshot mode condition in arm_trbe_alloc_buffer()
> >>> - Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled
> >>> - Compute trbe_limit before trbe_write to get the updated handle
> >>> - Added trbe_stop_and_truncate_event()
> >>> - Dropped trbe_handle_fatal()
> >>>
> >>>  Documentation/trace/coresight/coresight-trbe.rst |   39 +
> >>>  arch/arm64/include/asm/sysreg.h                  |    1 +
> >>>  drivers/hwtracing/coresight/Kconfig              |   11 +
> >>>  drivers/hwtracing/coresight/Makefile             |    1 +
> >>>  drivers/hwtracing/coresight/coresight-trbe.c     | 1023 ++++++++++++++++++++++
> >>>  drivers/hwtracing/coresight/coresight-trbe.h     |  160 ++++
> >>>  6 files changed, 1235 insertions(+)
> >>>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
> >>>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
> >>>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
> >>>

[...]

> >>> +
> >>> +static irqreturn_t arm_trbe_irq_handler(int irq, void *dev)
> >>> +{
> >>> +	struct perf_output_handle **handle_ptr = dev;
> >>> +	struct perf_output_handle *handle = *handle_ptr;
> >>> +	enum trbe_fault_action act;
> >>> +
> >>> +	WARN_ON(!is_trbe_irq(read_sysreg_s(SYS_TRBSR_EL1)));
> >>> +	clr_trbe_irq();
> >>> +
> >>> +	/*
> >>> +	 * Ensure the trace is visible to the CPUs and
> >>> +	 * any external aborts have been resolved.
> >>> +	 */
> >>> +	trbe_drain_buffer();
> >>> +	isb();
> >>> +
> >>> +	if (!perf_get_aux(handle))
> >>> +		return IRQ_NONE;
> >>> +
> >>> +	if (!is_perf_trbe(handle))
> >>> +		return IRQ_NONE;
> >>> +
> >>> +	irq_work_run();
> > 
> > There is a comment in the SPE driver about this.  Since this driver closely
> > follows that implementation it would be nice to have the comments as well.
> > Otherwise the reader has to constantly go back to the original driver.
> 
> Sure, will add the following comment before irq_work_run().
> 
>         /*
>          * Ensure perf callbacks have completed, which may disable the
>          * profiling buffer in response to a TRUNCATION flag.
>          */
> 
> > 
> > I will come back to this function later.
> 
> Okay.
> 
> > 
> >>> +
> >>> +	act = trbe_get_fault_act(handle);
> >>> +	switch (act) {
> >>> +	case TRBE_FAULT_ACT_WRAP:
> >>> +		trbe_handle_overflow(handle);
> >>> +		break;
> >>> +	case TRBE_FAULT_ACT_SPURIOUS:
> >>> +		trbe_handle_spurious(handle);
> >>> +		break;
> >>> +	case TRBE_FAULT_ACT_FATAL:
> >>> +		trbe_stop_and_truncate_event(handle);
> >>> +		break;
> >>> +	}
> >>> +	return IRQ_HANDLED;
> >>> +}
> >>> +
> >>> +static const struct coresight_ops_sink arm_trbe_sink_ops = {
> >>> +	.enable		= arm_trbe_enable,
> >>> +	.disable	= arm_trbe_disable,
> >>> +	.alloc_buffer	= arm_trbe_alloc_buffer,
> >>> +	.free_buffer	= arm_trbe_free_buffer,
> >>> +	.update_buffer	= arm_trbe_update_buffer,
> >>> +};
> >>> +
> >>> +static const struct coresight_ops arm_trbe_cs_ops = {
> >>> +	.sink_ops	= &arm_trbe_sink_ops,
> >>> +};
> >>> +
> >>> +static ssize_t align_show(struct device *dev, struct device_attribute *attr, char *buf)
> >>> +{
> >>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
> >>> +
> >>> +	return sprintf(buf, "%llx\n", cpudata->trbe_align);
> >>> +}
> >>> +static DEVICE_ATTR_RO(align);
> >>> +
> >>> +static ssize_t dbm_show(struct device *dev, struct device_attribute *attr, char *buf)
> >>> +{
> >>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
> >>> +
> >>> +	return sprintf(buf, "%d\n", cpudata->trbe_dbm);
> >>> +}
> >>> +static DEVICE_ATTR_RO(dbm);
> >>> +
> >>> +static struct attribute *arm_trbe_attrs[] = {
> >>> +	&dev_attr_align.attr,
> >>> +	&dev_attr_dbm.attr,
> >>> +	NULL,
> >>> +};
> >>> +
> >>> +static const struct attribute_group arm_trbe_group = {
> >>> +	.attrs = arm_trbe_attrs,
> >>> +};
> >>> +
> >>> +static const struct attribute_group *arm_trbe_groups[] = {
> >>> +	&arm_trbe_group,
> >>> +	NULL,
> >>> +};
> >>> +
> >>> +static void arm_trbe_probe_coresight_cpu(void *info)
> >>> +{
> >>> +	struct trbe_drvdata *drvdata = info;
> >>> +	struct coresight_desc desc = { 0 };
> >>> +	int cpu = smp_processor_id();
> >>> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
> >>> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
> >>> +	u64 trbidr = read_sysreg_s(SYS_TRBIDR_EL1);
> >>> +	struct device *dev;
> >>> +
> >>> +	if (WARN_ON(!cpudata))
> >>> +		goto cpu_clear;
> > 
> > Where was the memory for cpudata allocated?  As far as I can tell, at this time
> > it is just a pointer that was not allocated and as such it should be NULL.
> 
> cpudata gets allocated in arm_trbe_probe_coresight() just before calling
> individual CPU based probes i.e arm_trbe_probe_coresight_cpu() directly
> and via smp_call_function_many().
> 
> arm_trbe_device_probe()
> 	arm_trbe_probe_coresight()
> 		arm_trbe_probe_coresight_cpu()

Ah yes, my apologies here.  Looking at the code I realised I skipped
arm_trbe_probe_coresight() and went straight to arm_trbe_probe_coresight_cpu().
No wonder things didn't make sense.  I will take another look at this function. 

> 
> > 
> >>> +
> >>> +	if (trbe_csdev)
> >>> +		return;
> >>> +
> >>> +	cpudata->cpu = smp_processor_id();
> > 
> > Why call this again when you already did above?  And how is
> 
> Right, this is redundant. Will just assign it as cpu which has already
> been computed.
> 
> > arm_trbe_probe_coresight_cpu() is called for every CPU in the system?
> 
> During boot in arm_trbe_probe_coresight(), it is called once directly on
> the executing cpu and on all other via smp_call_function_many().
> 
> > 
> >>> +	cpudata->drvdata = drvdata;
> >>> +	dev = &cpudata->drvdata->pdev->dev;
> >>> +
> >>> +	if (!is_trbe_available()) {
> >>> +		pr_err("TRBE is not implemented on cpu %d\n", cpudata->cpu);
> >>> +		goto cpu_clear;
> >>> +	}
> >>> +
> >>> +	if (!is_trbe_programmable(trbidr)) {
> >>> +		pr_err("TRBE is owned in higher exception level on cpu %d\n", cpudata->cpu);
> >>> +		goto cpu_clear;
> >>> +	}
> >>> +	desc.name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", DRVNAME, smp_processor_id());
> >>> +	if (IS_ERR(desc.name))
> >>> +		goto cpu_clear;
> >>> +
> >>> +	desc.type = CORESIGHT_DEV_TYPE_SINK;
> >>> +	desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
> >>> +	desc.ops = &arm_trbe_cs_ops;
> >>> +	desc.pdata = dev_get_platdata(dev);
> >>> +	desc.groups = arm_trbe_groups;
> >>> +	desc.dev = dev;
> >>> +	trbe_csdev = coresight_register(&desc);
> >>> +	if (IS_ERR(trbe_csdev))
> >>> +		goto cpu_clear;
> >>> +
> >>> +	dev_set_drvdata(&trbe_csdev->dev, cpudata);
> >>> +	cpudata->trbe_dbm = get_trbe_flag_update(trbidr);
> >>> +	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
> >>> +	if (cpudata->trbe_align > SZ_2K) {
> >>> +		pr_err("Unsupported alignment on cpu %d\n", cpudata->cpu);
> >>> +		goto cpu_clear;
> >>> +	}
> >>> +	per_cpu(csdev_sink, cpu) = trbe_csdev;
> >>> +	trbe_reset_local();
> >>> +	enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
> >>> +	return;
> >>> +cpu_clear:
> >>> +	cpumask_clear_cpu(cpudata->cpu, &cpudata->drvdata->supported_cpus);
> >>> +}
> >>> +
> >>> +static void arm_trbe_remove_coresight_cpu(void *info)
> >>> +{
> >>> +	int cpu = smp_processor_id();
> >>> +	struct trbe_drvdata *drvdata = info;
> >>> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
> >>> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
> >>> +
> >>> +	if (trbe_csdev) {
> >>> +		coresight_unregister(trbe_csdev);
> >>> +		cpudata->drvdata = NULL;
> >>> +		per_cpu(csdev_sink, cpu) = NULL;
> >>> +	}
> >>> +	disable_percpu_irq(drvdata->irq);
> >>> +	trbe_reset_local();
> >>> +}
> >>> +
> >>> +static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata)
> >>> +{
> >>> +	drvdata->cpudata = alloc_percpu(typeof(*drvdata->cpudata));
> >>> +	if (IS_ERR(drvdata->cpudata))
> >>> +		return PTR_ERR(drvdata->cpudata);
> >>> +
> >>> +	arm_trbe_probe_coresight_cpu(drvdata);
> >>> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_probe_coresight_cpu, drvdata, 1);
> >>> +	return 0;
> >>> +}
> >>> +
> >>> +static int arm_trbe_remove_coresight(struct trbe_drvdata *drvdata)
> >>> +{
> >>> +	arm_trbe_remove_coresight_cpu(drvdata);
> >>> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_remove_coresight_cpu, drvdata, 1);
> >>> +	free_percpu(drvdata->cpudata);
> >>> +	return 0;
> >>> +}
> >>> +
> >>> +static int arm_trbe_cpu_startup(unsigned int cpu, struct hlist_node *node)
> >>> +{
> >>> +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
> >>> +
> >>> +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
> >>> +		if (!per_cpu(csdev_sink, cpu)) {
> >>> +			arm_trbe_probe_coresight_cpu(drvdata);
> >>> +		} else {
> >>> +			trbe_reset_local();
> >>> +			enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
> >>> +		}
> >>> +	}
> >>> +	return 0;
> >>> +}
> >>> +
> >>> +static int arm_trbe_cpu_teardown(unsigned int cpu, struct hlist_node *node)
> >>> +{
> >>> +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
> >>> +
> >>> +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
> >>> +		disable_percpu_irq(drvdata->irq);
> >>> +		trbe_reset_local();
> >>> +	}
> >>> +	return 0;
> >>> +}
> >>> +
> >>> +static int arm_trbe_probe_cpuhp(struct trbe_drvdata *drvdata)
> >>> +{
> >>> +	enum cpuhp_state trbe_online;
> >>> +
> >>> +	trbe_online = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
> >>> +					arm_trbe_cpu_startup, arm_trbe_cpu_teardown);
> >>> +	if (trbe_online < 0)
> >>> +		return -EINVAL;
> >>> +
> >>> +	if (cpuhp_state_add_instance(trbe_online, &drvdata->hotplug_node))
> >>> +		return -EINVAL;
> >>> +
> >>> +	drvdata->trbe_online = trbe_online;
> >>> +	return 0;
> >>> +}
> >>> +
> >>> +static void arm_trbe_remove_cpuhp(struct trbe_drvdata *drvdata)
> >>> +{
> >>> +	cpuhp_remove_multi_state(drvdata->trbe_online);
> >>> +}
> >>> +
> >>> +static int arm_trbe_probe_irq(struct platform_device *pdev,
> >>> +			      struct trbe_drvdata *drvdata)
> >>> +{
> >>> +	drvdata->irq = platform_get_irq(pdev, 0);
> >>> +	if (!drvdata->irq) {
> > 
> > Please use function platform_get_irq() properly - there is even an example on
> > how to do so in the documentation section of the function.
> 
> The documentation says, the format should be.
> 
> int irq = platform_get_irq(pdev, 0);
> if (irq < 0)
> 	return irq;
> 
> Will change the conditional check above.
> 
> > 
> >>> +		pr_err("IRQ not found for the platform device\n");
> >>> +		return -ENXIO;
> > 
> > Why use a different error code?
> 
> We could return the irq (which is < 0) but followed the SPE
> driver which returns ENXIO here. Happy to change either way.

Please use the right error code.

> 
> > 
> >>> +	}
> >>> +
> >>> +	if (!irq_is_percpu(drvdata->irq)) {
> >>> +		pr_err("IRQ is not a PPI\n");
> >>> +		return -EINVAL;
> >>> +	}
> >>> +
> >>> +	if (irq_get_percpu_devid_partition(drvdata->irq, &drvdata->supported_cpus))
> >>> +		return -EINVAL;
> >>> +
> >>> +	drvdata->handle = alloc_percpu(typeof(*drvdata->handle));
> >>> +	if (!drvdata->handle)
> >>> +		return -ENOMEM;
> >>> +
> >>> +	if (request_percpu_irq(drvdata->irq, arm_trbe_irq_handler, DRVNAME, drvdata->handle)) {
> >>> +		free_percpu(drvdata->handle);
> >>> +		return -EINVAL;
> > 
> > Here too you need to use the error code from the calling function rather than
> > making your own.  Please revise for the entire patch.
> 
> Okay, will capture the return value from request_percpu_irq() and
> return the same when it is an error case i.e being positive.
> 
> > 
> >>> +	}
> >>> +	return 0;
> >>> +}
> >>> +
> >>> +static void arm_trbe_remove_irq(struct trbe_drvdata *drvdata)
> >>> +{
> >>> +	free_percpu_irq(drvdata->irq, drvdata->handle);
> >>> +	free_percpu(drvdata->handle);
> >>> +}
> >>> +
> >>> +static int arm_trbe_device_probe(struct platform_device *pdev)
> >>> +{
> >>> +	struct coresight_platform_data *pdata;
> >>> +	struct trbe_drvdata *drvdata;
> >>> +	struct device *dev = &pdev->dev;
> >>> +	int ret;
> >>> +
> >>> +	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> >>> +	if (IS_ERR(drvdata))
> >>> +		return -ENOMEM;
> > 
> >         if (!drvdata)
> 
> Changed.
> 
> > 
> >>> +
> >>> +	pdata = coresight_get_platform_data(dev);
> >>> +	if (IS_ERR(pdata)) {
> >>> +		kfree(drvdata);
> > 
> > No need to do this since devm_kzalloc() was used above.
> 
> Suzuki had pointed out these issues, have already incorporated them i.e
> dropped kfree() here.
> 

To avoid getting tunel vision I don't look at other comments before reviewing a
patchset.  As such it is possible to get redundant comments.

More to come shortly.

> > 
> >>> +		return -ENOMEM;
> > 
> > Why not using the error from coresight_get_platform_data() instead of
> > masking it?
> 
> Okay, will return PTR_ERR(pdata) instead.
> 
> > 
> >>> +	}
> >>> +
> >>> +	dev_set_drvdata(dev, drvdata);
> >>> +	dev->platform_data = pdata;
> >>> +	drvdata->pdev = pdev;
> >>> +	ret = arm_trbe_probe_irq(pdev, drvdata);
> >>> +	if (ret)
> >>> +		goto irq_failed;
> >>> +
> >>> +	ret = arm_trbe_probe_coresight(drvdata);
> >>> +	if (ret)
> >>> +		goto probe_failed;
> >>> +
> >>> +	ret = arm_trbe_probe_cpuhp(drvdata);
> >>> +	if (ret)
> >>> +		goto cpuhp_failed;
> >>> +
> >>> +	return 0;
> >>> +cpuhp_failed:
> >>> +	arm_trbe_remove_coresight(drvdata);
> >>> +probe_failed:
> >>> +	arm_trbe_remove_irq(drvdata);
> >>> +irq_failed:
> >>> +	kfree(pdata);
> >>> +	kfree(drvdata);
> > 
> > Same here - both @pdata and @drvdata have been allocated by devm_kzalloc().
> > devm_kzalloc().
> 
> Dropped these kfree() statements.
> 
> - Anshuman

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-01-27  8:55 ` [PATCH V3 11/14] coresight: sink: Add TRBE driver Anshuman Khandual
       [not found]   ` <12cdc8ca-0a69-bfba-bbcd-fb392d6ca051@arm.com>
  2021-02-05 17:53   ` Mathieu Poirier
@ 2021-02-10 19:00   ` Mathieu Poirier
  2021-02-12  5:43     ` Anshuman Khandual
  2021-02-11 19:00   ` Mathieu Poirier
  2021-02-12 20:26   ` Mathieu Poirier
  4 siblings, 1 reply; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-10 19:00 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel

On Wed, Jan 27, 2021 at 02:25:35PM +0530, Anshuman Khandual wrote:
> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
> accessible via the system registers. The TRBE supports different addressing
> modes including CPU virtual address and buffer modes including the circular
> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
> access to the trace buffer could be prohibited by a higher exception level
> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
> private interrupt (PPI) on address translation errors and when the buffer
> is full. Overall implementation here is inspired from the Arm SPE driver.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> Changes in V3:
> 
> - Added new DT bindings document TRBE.yaml
> - Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3
> - Dropped isb() from trbe_reset_local()
> - Dropped gap between (void *) and buf->trbe_base
> - Changed 'int' to 'unsigned int' in is_trbe_available()
> - Dropped unused function set_trbe_running(), set_trbe_virtual_mode(),
>   set_trbe_enabled() and set_trbe_limit_pointer()
> - Changed get_trbe_flag_update(), is_trbe_programmable() and
>   get_trbe_address_align() to accept TRBIDR value
> - Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), is_trbe_trg(),
>   is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value
> - Dropped snapshot mode condition in arm_trbe_alloc_buffer()
> - Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled
> - Compute trbe_limit before trbe_write to get the updated handle
> - Added trbe_stop_and_truncate_event()
> - Dropped trbe_handle_fatal()
> 
>  Documentation/trace/coresight/coresight-trbe.rst |   39 +
>  arch/arm64/include/asm/sysreg.h                  |    1 +
>  drivers/hwtracing/coresight/Kconfig              |   11 +
>  drivers/hwtracing/coresight/Makefile             |    1 +
>  drivers/hwtracing/coresight/coresight-trbe.c     | 1023 ++++++++++++++++++++++
>  drivers/hwtracing/coresight/coresight-trbe.h     |  160 ++++
>  6 files changed, 1235 insertions(+)
>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
> +

[...]

> +static void arm_trbe_probe_coresight_cpu(void *info)
> +{
> +	struct trbe_drvdata *drvdata = info;
> +	struct coresight_desc desc = { 0 };
> +	int cpu = smp_processor_id();
> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
> +	u64 trbidr = read_sysreg_s(SYS_TRBIDR_EL1);
> +	struct device *dev;
> +
> +	if (WARN_ON(!cpudata))
> +		goto cpu_clear;

There is already a check for this in arm_trbe_probe_coresight(), we couldn't be
here if there was a problem with the allocation.

> +
> +	if (trbe_csdev)
> +		return;

Now that's a reason to have a WARN_ON().  If we are probing and a sink is
already present in this cpu's slot, something went seriously wrong and we should
be clear about it.

> +
> +	cpudata->cpu = smp_processor_id();
> +	cpudata->drvdata = drvdata;
> +	dev = &cpudata->drvdata->pdev->dev;
> +
> +	if (!is_trbe_available()) {
> +		pr_err("TRBE is not implemented on cpu %d\n", cpudata->cpu);
> +		goto cpu_clear;
> +	}
> +
> +	if (!is_trbe_programmable(trbidr)) {
> +		pr_err("TRBE is owned in higher exception level on cpu %d\n", cpudata->cpu);
> +		goto cpu_clear;
> +	}
> +	desc.name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", DRVNAME, smp_processor_id());

We will end up with "arm_trbe0", "arm_trbe1" and so on in sysfs...  Is the
"arm_" part absolutely needed?  I think this should be like what we do for etmv3
and etmv4 where only "etmX" shows up in sysfs.

> +	if (IS_ERR(desc.name))
> +		goto cpu_clear;
> +
> +	desc.type = CORESIGHT_DEV_TYPE_SINK;
> +	desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
> +	desc.ops = &arm_trbe_cs_ops;
> +	desc.pdata = dev_get_platdata(dev);
> +	desc.groups = arm_trbe_groups;
> +	desc.dev = dev;
> +	trbe_csdev = coresight_register(&desc);
> +	if (IS_ERR(trbe_csdev))
> +		goto cpu_clear;
> +
> +	dev_set_drvdata(&trbe_csdev->dev, cpudata);
> +	cpudata->trbe_dbm = get_trbe_flag_update(trbidr);
> +	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
> +	if (cpudata->trbe_align > SZ_2K) {
> +		pr_err("Unsupported alignment on cpu %d\n", cpudata->cpu);
> +		goto cpu_clear;

Here coresight_unregister() should be called.  The other option is to call
coresight_register() when everything else is known to be fine, which is the
favoured approach.

> +	}
> +	per_cpu(csdev_sink, cpu) = trbe_csdev;
> +	trbe_reset_local();
> +	enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
> +	return;
> +cpu_clear:
> +	cpumask_clear_cpu(cpudata->cpu, &cpudata->drvdata->supported_cpus);
> +}
> +
> +static void arm_trbe_remove_coresight_cpu(void *info)
> +{
> +	int cpu = smp_processor_id();
> +	struct trbe_drvdata *drvdata = info;
> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
> +
> +	if (trbe_csdev) {

In what scenario do you see not having a trbe_csdev and still needing to disable
IRQs for the HW?  If there is a such a case then a few lines of comment is
needed.

> +		coresight_unregister(trbe_csdev);
> +		cpudata->drvdata = NULL;
> +		per_cpu(csdev_sink, cpu) = NULL;
> +	}
> +	disable_percpu_irq(drvdata->irq);
> +	trbe_reset_local();

Theoretically this code shouldn't run when the TRBE is enabled, because the CS
core will prevent that from happening.  As sush disabling interrupts after
coresight_unregister() has been called and setting cpudata->drvdata to NULL
should be fine.  But from an outsider's point of view it will look very bizarre.
Either write a comment to explain all that or call the above two before doing
the cleanup.

> +}
> +
> +static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata)
> +{
> +	drvdata->cpudata = alloc_percpu(typeof(*drvdata->cpudata));
> +	if (IS_ERR(drvdata->cpudata))
> +		return PTR_ERR(drvdata->cpudata);

As far as I can tell alloc_percpu() returns NULL on failure and nothing else.

> +
> +	arm_trbe_probe_coresight_cpu(drvdata);
> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_probe_coresight_cpu, drvdata, 1);

The above two calls look racy to me.  The executing process could be moved to
another CPU between the call to arm_trbe_probe_coresight_cpu() and
smp_call_function_many(), which would prevent the initialisation of the TRBE on
the new CPU to be done.  I suggest using a for_each_cpu() loop where
smp_call_function_single() would be used.  That way we are guaranteed all the
TRBEs will be initialised.

> +	return 0;
> +}
> +
> +static int arm_trbe_remove_coresight(struct trbe_drvdata *drvdata)
> +{
> +	arm_trbe_remove_coresight_cpu(drvdata);
> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_remove_coresight_cpu, drvdata, 1);

Same as above.

I'm out of time for today, more to come tomorrow.

Mathieu

> +	free_percpu(drvdata->cpudata);
> +	return 0;
> +}
> +
> +static int arm_trbe_cpu_startup(unsigned int cpu, struct hlist_node *node)
> +{
> +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
> +
> +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
> +		if (!per_cpu(csdev_sink, cpu)) {
> +			arm_trbe_probe_coresight_cpu(drvdata);
> +		} else {
> +			trbe_reset_local();
> +			enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
> +		}
> +	}
> +	return 0;
> +}
> +
> +static int arm_trbe_cpu_teardown(unsigned int cpu, struct hlist_node *node)
> +{
> +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
> +
> +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
> +		disable_percpu_irq(drvdata->irq);
> +		trbe_reset_local();
> +	}
> +	return 0;
> +}
> +
> +static int arm_trbe_probe_cpuhp(struct trbe_drvdata *drvdata)
> +{
> +	enum cpuhp_state trbe_online;
> +
> +	trbe_online = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
> +					arm_trbe_cpu_startup, arm_trbe_cpu_teardown);
> +	if (trbe_online < 0)
> +		return -EINVAL;
> +
> +	if (cpuhp_state_add_instance(trbe_online, &drvdata->hotplug_node))
> +		return -EINVAL;
> +
> +	drvdata->trbe_online = trbe_online;
> +	return 0;
> +}
> +
> +static void arm_trbe_remove_cpuhp(struct trbe_drvdata *drvdata)
> +{
> +	cpuhp_remove_multi_state(drvdata->trbe_online);
> +}
> +
> +static int arm_trbe_probe_irq(struct platform_device *pdev,
> +			      struct trbe_drvdata *drvdata)
> +{
> +	drvdata->irq = platform_get_irq(pdev, 0);
> +	if (!drvdata->irq) {
> +		pr_err("IRQ not found for the platform device\n");
> +		return -ENXIO;
> +	}
> +
> +	if (!irq_is_percpu(drvdata->irq)) {
> +		pr_err("IRQ is not a PPI\n");
> +		return -EINVAL;
> +	}
> +
> +	if (irq_get_percpu_devid_partition(drvdata->irq, &drvdata->supported_cpus))
> +		return -EINVAL;
> +
> +	drvdata->handle = alloc_percpu(typeof(*drvdata->handle));
> +	if (!drvdata->handle)
> +		return -ENOMEM;
> +
> +	if (request_percpu_irq(drvdata->irq, arm_trbe_irq_handler, DRVNAME, drvdata->handle)) {
> +		free_percpu(drvdata->handle);
> +		return -EINVAL;
> +	}
> +	return 0;
> +}
> +
> +static void arm_trbe_remove_irq(struct trbe_drvdata *drvdata)
> +{
> +	free_percpu_irq(drvdata->irq, drvdata->handle);
> +	free_percpu(drvdata->handle);
> +}
> +
> +static int arm_trbe_device_probe(struct platform_device *pdev)
> +{
> +	struct coresight_platform_data *pdata;
> +	struct trbe_drvdata *drvdata;
> +	struct device *dev = &pdev->dev;
> +	int ret;
> +
> +	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> +	if (IS_ERR(drvdata))
> +		return -ENOMEM;
> +
> +	pdata = coresight_get_platform_data(dev);
> +	if (IS_ERR(pdata)) {
> +		kfree(drvdata);
> +		return -ENOMEM;
> +	}
> +
> +	dev_set_drvdata(dev, drvdata);
> +	dev->platform_data = pdata;
> +	drvdata->pdev = pdev;
> +	ret = arm_trbe_probe_irq(pdev, drvdata);
> +	if (ret)
> +		goto irq_failed;
> +
> +	ret = arm_trbe_probe_coresight(drvdata);
> +	if (ret)
> +		goto probe_failed;
> +
> +	ret = arm_trbe_probe_cpuhp(drvdata);
> +	if (ret)
> +		goto cpuhp_failed;
> +
> +	return 0;
> +cpuhp_failed:
> +	arm_trbe_remove_coresight(drvdata);
> +probe_failed:
> +	arm_trbe_remove_irq(drvdata);
> +irq_failed:
> +	kfree(pdata);
> +	kfree(drvdata);
> +	return ret;
> +}
> +
> +static int arm_trbe_device_remove(struct platform_device *pdev)
> +{
> +	struct coresight_platform_data *pdata = dev_get_platdata(&pdev->dev);
> +	struct trbe_drvdata *drvdata = platform_get_drvdata(pdev);
> +
> +	arm_trbe_remove_coresight(drvdata);
> +	arm_trbe_remove_cpuhp(drvdata);
> +	arm_trbe_remove_irq(drvdata);
> +	kfree(pdata);
> +	kfree(drvdata);
> +	return 0;
> +}
> +
> +static const struct of_device_id arm_trbe_of_match[] = {
> +	{ .compatible = "arm,trace-buffer-extension"},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, arm_trbe_of_match);
> +
> +static struct platform_driver arm_trbe_driver = {
> +	.driver	= {
> +		.name = DRVNAME,
> +		.of_match_table = of_match_ptr(arm_trbe_of_match),
> +		.suppress_bind_attrs = true,
> +	},
> +	.probe	= arm_trbe_device_probe,
> +	.remove	= arm_trbe_device_remove,
> +};
> +
> +static int __init arm_trbe_init(void)
> +{
> +	int ret;
> +
> +	if (arm64_kernel_unmapped_at_el0()) {
> +		pr_err("TRBE wouldn't work if kernel gets unmapped at EL0\n");
> +		return -EOPNOTSUPP;
> +	}
> +
> +	ret = platform_driver_register(&arm_trbe_driver);
> +	if (!ret)
> +		return 0;
> +
> +	pr_err("Error registering %s platform driver\n", DRVNAME);
> +	return ret;
> +}
> +
> +static void __exit arm_trbe_exit(void)
> +{
> +	platform_driver_unregister(&arm_trbe_driver);
> +}
> +module_init(arm_trbe_init);
> +module_exit(arm_trbe_exit);
> +
> +MODULE_AUTHOR("Anshuman Khandual <anshuman.khandual@arm.com>");
> +MODULE_DESCRIPTION("Arm Trace Buffer Extension (TRBE) driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h
> new file mode 100644
> index 0000000..43308bc
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-trbe.h
> @@ -0,0 +1,160 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This contains all required hardware related helper functions for
> + * Trace Buffer Extension (TRBE) driver in the coresight framework.
> + *
> + * Copyright (C) 2020 ARM Ltd.
> + *
> + * Author: Anshuman Khandual <anshuman.khandual@arm.com>
> + */
> +#include <linux/coresight.h>
> +#include <linux/device.h>
> +#include <linux/irq.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/smp.h>
> +
> +#include "coresight-etm-perf.h"
> +
> +DECLARE_PER_CPU(struct coresight_device *, csdev_sink);
> +
> +static inline bool is_trbe_available(void)
> +{
> +	u64 aa64dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
> +	unsigned int trbe = cpuid_feature_extract_unsigned_field(aa64dfr0, ID_AA64DFR0_TRBE_SHIFT);
> +
> +	return trbe >= 0b0001;
> +}
> +
> +static inline bool is_trbe_enabled(void)
> +{
> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> +
> +	return trblimitr & TRBLIMITR_ENABLE;
> +}
> +
> +#define TRBE_EC_OTHERS		0
> +#define TRBE_EC_STAGE1_ABORT	36
> +#define TRBE_EC_STAGE2_ABORT	37
> +
> +static inline int get_trbe_ec(u64 trbsr)
> +{
> +	return (trbsr >> TRBSR_EC_SHIFT) & TRBSR_EC_MASK;
> +}
> +
> +#define TRBE_BSC_NOT_STOPPED	0
> +#define	TRBE_BSC_FILLED		1
> +#define TRBE_BSC_TRIGGERED	2
> +
> +static inline int get_trbe_bsc(u64 trbsr)
> +{
> +	return (trbsr >> TRBSR_BSC_SHIFT) & TRBSR_BSC_MASK;
> +}
> +
> +static inline void clr_trbe_irq(void)
> +{
> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
> +
> +	trbsr &= ~TRBSR_IRQ;
> +	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
> +}
> +
> +static inline bool is_trbe_irq(u64 trbsr)
> +{
> +	return trbsr & TRBSR_IRQ;
> +}
> +
> +static inline bool is_trbe_trg(u64 trbsr)
> +{
> +	return trbsr & TRBSR_TRG;
> +}
> +
> +static inline bool is_trbe_wrap(u64 trbsr)
> +{
> +	return trbsr & TRBSR_WRAP;
> +}
> +
> +static inline bool is_trbe_abort(u64 trbsr)
> +{
> +	return trbsr & TRBSR_ABORT;
> +}
> +
> +static inline bool is_trbe_running(u64 trbsr)
> +{
> +	return !(trbsr & TRBSR_STOP);
> +}
> +
> +#define TRBE_TRIG_MODE_STOP		0
> +#define TRBE_TRIG_MODE_IRQ		1
> +#define TRBE_TRIG_MODE_IGNORE		3
> +
> +#define TRBE_FILL_MODE_FILL		0
> +#define TRBE_FILL_MODE_WRAP		1
> +#define TRBE_FILL_MODE_CIRCULAR_BUFFER	3
> +
> +static inline void set_trbe_disabled(void)
> +{
> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> +
> +	trblimitr &= ~TRBLIMITR_ENABLE;
> +	write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
> +}
> +
> +static inline bool get_trbe_flag_update(u64 trbidr)
> +{
> +	return trbidr & TRBIDR_FLAG;
> +}
> +
> +static inline bool is_trbe_programmable(u64 trbidr)
> +{
> +	return !(trbidr & TRBIDR_PROG);
> +}
> +
> +static inline int get_trbe_address_align(u64 trbidr)
> +{
> +	return (trbidr >> TRBIDR_ALIGN_SHIFT) & TRBIDR_ALIGN_MASK;
> +}
> +
> +static inline unsigned long get_trbe_write_pointer(void)
> +{
> +	u64 trbptr = read_sysreg_s(SYS_TRBPTR_EL1);
> +	unsigned long addr = (trbptr >> TRBPTR_PTR_SHIFT) & TRBPTR_PTR_MASK;
> +
> +	return addr;
> +}
> +
> +static inline void set_trbe_write_pointer(unsigned long addr)
> +{
> +	WARN_ON(is_trbe_enabled());
> +	addr = (addr >> TRBPTR_PTR_SHIFT) & TRBPTR_PTR_MASK;
> +	write_sysreg_s(addr, SYS_TRBPTR_EL1);
> +}
> +
> +static inline unsigned long get_trbe_limit_pointer(void)
> +{
> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> +	unsigned long limit = (trblimitr >> TRBLIMITR_LIMIT_SHIFT) & TRBLIMITR_LIMIT_MASK;
> +	unsigned long addr = limit << TRBLIMITR_LIMIT_SHIFT;
> +
> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> +	return addr;
> +}
> +
> +static inline unsigned long get_trbe_base_pointer(void)
> +{
> +	u64 trbbaser = read_sysreg_s(SYS_TRBBASER_EL1);
> +	unsigned long addr = (trbbaser >> TRBBASER_BASE_SHIFT) & TRBBASER_BASE_MASK;
> +
> +	addr = addr << TRBBASER_BASE_SHIFT;
> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> +	return addr;
> +}
> +
> +static inline void set_trbe_base_pointer(unsigned long addr)
> +{
> +	WARN_ON(is_trbe_enabled());
> +	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> +	write_sysreg_s(addr, SYS_TRBBASER_EL1);
> +}
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-01-27  8:55 ` [PATCH V3 11/14] coresight: sink: Add TRBE driver Anshuman Khandual
                     ` (2 preceding siblings ...)
  2021-02-10 19:00   ` Mathieu Poirier
@ 2021-02-11 19:00   ` Mathieu Poirier
  2021-02-12  3:31     ` Anshuman Khandual
  2021-02-12 20:26   ` Mathieu Poirier
  4 siblings, 1 reply; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-11 19:00 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel

On Wed, Jan 27, 2021 at 02:25:35PM +0530, Anshuman Khandual wrote:
> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
> accessible via the system registers. The TRBE supports different addressing
> modes including CPU virtual address and buffer modes including the circular
> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
> access to the trace buffer could be prohibited by a higher exception level
> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
> private interrupt (PPI) on address translation errors and when the buffer
> is full. Overall implementation here is inspired from the Arm SPE driver.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> Changes in V3:
> 
> - Added new DT bindings document TRBE.yaml
> - Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3
> - Dropped isb() from trbe_reset_local()
> - Dropped gap between (void *) and buf->trbe_base
> - Changed 'int' to 'unsigned int' in is_trbe_available()
> - Dropped unused function set_trbe_running(), set_trbe_virtual_mode(),
>   set_trbe_enabled() and set_trbe_limit_pointer()
> - Changed get_trbe_flag_update(), is_trbe_programmable() and
>   get_trbe_address_align() to accept TRBIDR value
> - Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), is_trbe_trg(),
>   is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value
> - Dropped snapshot mode condition in arm_trbe_alloc_buffer()
> - Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled
> - Compute trbe_limit before trbe_write to get the updated handle
> - Added trbe_stop_and_truncate_event()
> - Dropped trbe_handle_fatal()
> 
>  Documentation/trace/coresight/coresight-trbe.rst |   39 +
>  arch/arm64/include/asm/sysreg.h                  |    1 +
>  drivers/hwtracing/coresight/Kconfig              |   11 +
>  drivers/hwtracing/coresight/Makefile             |    1 +
>  drivers/hwtracing/coresight/coresight-trbe.c     | 1023 ++++++++++++++++++++++
>  drivers/hwtracing/coresight/coresight-trbe.h     |  160 ++++
>  6 files changed, 1235 insertions(+)
>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
> 
> diff --git a/Documentation/trace/coresight/coresight-trbe.rst b/Documentation/trace/coresight/coresight-trbe.rst
> new file mode 100644
> index 0000000..1cbb819
> --- /dev/null
> +++ b/Documentation/trace/coresight/coresight-trbe.rst
> @@ -0,0 +1,39 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +==============================
> +Trace Buffer Extension (TRBE).
> +==============================
> +
> +    :Author:   Anshuman Khandual <anshuman.khandual@arm.com>
> +    :Date:     November 2020
> +
> +Hardware Description
> +--------------------
> +
> +Trace Buffer Extension (TRBE) is a percpu hardware which captures in system
> +memory, CPU traces generated from a corresponding percpu tracing unit. This
> +gets plugged in as a coresight sink device because the corresponding trace
> +genarators (ETE), are plugged in as source device.
> +
> +The TRBE is not compliant to CoreSight architecture specifications, but is
> +driven via the CoreSight driver framework to support the ETE (which is
> +CoreSight compliant) integration.
> +
> +Sysfs files and directories
> +---------------------------
> +
> +The TRBE devices appear on the existing coresight bus alongside the other
> +coresight devices::
> +
> +	>$ ls /sys/bus/coresight/devices
> +	trbe0  trbe1  trbe2 trbe3
> +
> +The ``trbe<N>`` named TRBEs are associated with a CPU.::
> +
> +	>$ ls /sys/bus/coresight/devices/trbe0/
> +        align dbm
> +
> +*Key file items are:-*
> +   * ``align``: TRBE write pointer alignment
> +   * ``dbm``: TRBE updates memory with access and dirty flags
> +
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 85ae4db..9e2e9b7 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -97,6 +97,7 @@
>  #define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
>  #define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
>  #define SET_PSTATE_TCO(x)		__emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
> +#define TSB_CSYNC			__emit_inst(0xd503225f)
>  
>  #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
>  #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> index f154ae7..aa657ab 100644
> --- a/drivers/hwtracing/coresight/Kconfig
> +++ b/drivers/hwtracing/coresight/Kconfig
> @@ -164,6 +164,17 @@ config CORESIGHT_CTI
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called coresight-cti.
>  
> +config CORESIGHT_TRBE
> +	bool "Trace Buffer Extension (TRBE) driver"
> +	depends on ARM64
> +	help
> +	  This driver provides support for percpu Trace Buffer Extension (TRBE).
> +	  TRBE always needs to be used along with it's corresponding percpu ETE
> +	  component. ETE generates trace data which is then captured with TRBE.
> +	  Unlike traditional sink devices, TRBE is a CPU feature accessible via
> +	  system registers. But it's explicit dependency with trace unit (ETE)
> +	  requires it to be plugged in as a coresight sink device.
> +
>  config CORESIGHT_CTI_INTEGRATION_REGS
>  	bool "Access CTI CoreSight Integration Registers"
>  	depends on CORESIGHT_CTI
> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
> index f20e357..d608165 100644
> --- a/drivers/hwtracing/coresight/Makefile
> +++ b/drivers/hwtracing/coresight/Makefile
> @@ -21,5 +21,6 @@ obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
>  obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
>  obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
>  obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
> +obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
>  coresight-cti-y := coresight-cti-core.o	coresight-cti-platform.o \
>  		   coresight-cti-sysfs.o
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> new file mode 100644
> index 0000000..1464d8b
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -0,0 +1,1023 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * This driver enables Trace Buffer Extension (TRBE) as a per-cpu coresight
> + * sink device could then pair with an appropriate per-cpu coresight source
> + * device (ETE) thus generating required trace data. Trace can be enabled
> + * via the perf framework.
> + *
> + * Copyright (C) 2020 ARM Ltd.
> + *
> + * Author: Anshuman Khandual <anshuman.khandual@arm.com>
> + */
> +#define DRVNAME "arm_trbe"
> +
> +#define pr_fmt(fmt) DRVNAME ": " fmt
> +
> +#include "coresight-trbe.h"
> +
> +#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
> +
> +/*
> + * A padding packet that will help the user space tools
> + * in skipping relevant sections in the captured trace
> + * data which could not be decoded. TRBE doesn't support
> + * formatting the trace data, unlike the legacy CoreSight
> + * sinks and thus we use ETE trace packets to pad the
> + * sections of the buffer.
> + */
> +#define ETE_IGNORE_PACKET 		0x70
> +
> +/*
> + * Minimum amount of meaningful trace will contain:
> + * A-Sync, Trace Info, Trace On, Address, Atom.
> + * This is about 44bytes of ETE trace. To be on
> + * the safer side, we assume 64bytes is the minimum
> + * space required for a meaningful session, before
> + * we hit a "WRAP" event.
> + */
> +#define TRBE_TRACE_MIN_BUF_SIZE		64
> +
> +enum trbe_fault_action {
> +	TRBE_FAULT_ACT_WRAP,
> +	TRBE_FAULT_ACT_SPURIOUS,
> +	TRBE_FAULT_ACT_FATAL,
> +};
> +
> +struct trbe_buf {
> +	unsigned long trbe_base;
> +	unsigned long trbe_limit;
> +	unsigned long trbe_write;
> +	int nr_pages;
> +	void **pages;
> +	bool snapshot;
> +	struct trbe_cpudata *cpudata;
> +};
> +
> +struct trbe_cpudata {
> +	bool trbe_dbm;
> +	u64 trbe_align;
> +	int cpu;
> +	enum cs_mode mode;
> +	struct trbe_buf *buf;
> +	struct trbe_drvdata *drvdata;
> +};
> +
> +struct trbe_drvdata {
> +	struct trbe_cpudata __percpu *cpudata;
> +	struct perf_output_handle __percpu **handle;
> +	struct hlist_node hotplug_node;
> +	int irq;
> +	cpumask_t supported_cpus;
> +	enum cpuhp_state trbe_online;
> +	struct platform_device *pdev;
> +};
> +
> +static int trbe_alloc_node(struct perf_event *event)
> +{
> +	if (event->cpu == -1)
> +		return NUMA_NO_NODE;
> +	return cpu_to_node(event->cpu);
> +}
> +
> +static void trbe_drain_buffer(void)
> +{
> +	asm(TSB_CSYNC);
> +	dsb(nsh);
> +}
> +
> +static void trbe_drain_and_disable_local(void)
> +{
> +	trbe_drain_buffer();
> +	write_sysreg_s(0, SYS_TRBLIMITR_EL1);
> +	isb();
> +}
> +
> +static void trbe_reset_local(void)
> +{
> +	trbe_drain_and_disable_local();
> +	write_sysreg_s(0, SYS_TRBPTR_EL1);
> +	write_sysreg_s(0, SYS_TRBBASER_EL1);
> +	write_sysreg_s(0, SYS_TRBSR_EL1);
> +}
> +
> +static void trbe_stop_and_truncate_event(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +
> +	/*
> +	 * We cannot proceed with the buffer collection and we
> +	 * do not have any data for the current session. The
> +	 * etm_perf driver expects to close out the aux_buffer
> +	 * at event_stop(). So disable the TRBE here and leave
> +	 * the update_buffer() to return a 0 size.
> +	 */
> +	trbe_drain_and_disable_local();
> +	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> +	*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
> +}
> +
> +/*
> + * TRBE Buffer Management
> + *
> + * The TRBE buffer spans from the base pointer till the limit pointer. When enabled,
> + * it starts writing trace data from the write pointer onward till the limit pointer.
> + * When the write pointer reaches the address just before the limit pointer, it gets
> + * wrapped around again to the base pointer. This is called a TRBE wrap event, which
> + * generates a maintenance interrupt when operated in WRAP or FILL mode. This driver
> + * uses FILL mode, where the TRBE stops the trace collection at wrap event. The IRQ
> + * handler updates the AUX buffer and re-enables the TRBE with updated WRITE and
> + * LIMIT pointers.
> + *
> + *	Wrap around with an IRQ
> + *	------ < ------ < ------- < ----- < -----
> + *	|					|
> + *	------ > ------ > ------- > ----- > -----
> + *
> + *	+---------------+-----------------------+
> + *	|		|			|
> + *	+---------------+-----------------------+
> + *	Base Pointer	Write Pointer		Limit Pointer
> + *
> + * The base and limit pointers always needs to be PAGE_SIZE aligned. But the write
> + * pointer can be aligned to the implementation defined TRBE trace buffer alignment
> + * as captured in trbe_cpudata->trbe_align.
> + *
> + *
> + *		head		tail		wakeup
> + *	+---------------------------------------+----- ~ ~ ------
> + *	|$$$$$$$|################|$$$$$$$$$$$$$$|		|
> + *	+---------------------------------------+----- ~ ~ ------
> + *	Base Pointer	Write Pointer		Limit Pointer
> + *
> + * The perf_output_handle indices (head, tail, wakeup) are monotonically increasing
> + * values which tracks all the driver writes and user reads from the perf auxiliary
> + * buffer. Generally [head..tail] is the area where the driver can write into unless
> + * the wakeup is behind the tail. Enabled TRBE buffer span needs to be adjusted and
> + * configured depending on the perf_output_handle indices, so that the driver does
> + * not override into areas in the perf auxiliary buffer which is being or yet to be
> + * consumed from the user space. The enabled TRBE buffer area is a moving subset of
> + * the allocated perf auxiliary buffer.
> + */
> +static void trbe_pad_buf(struct perf_output_handle *handle, int len)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	u64 head = PERF_IDX2OFF(handle->head, buf);
> +
> +	memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
> +	if (!buf->snapshot)
> +		perf_aux_output_skip(handle, len);
> +}
> +
> +static unsigned long trbe_snapshot_offset(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +
> +	/*
> +	 * The ETE trace has alignment synchronization packets allowing
> +	 * the decoder to reset in case of an overflow or corruption.
> +	 * So we can use the entire buffer for the snapshot mode.
> +	 */
> +	return buf->nr_pages * PAGE_SIZE;
> +}
> +
> +/*
> + * TRBE Limit Calculation
> + *
> + * The following markers are used to illustrate various TRBE buffer situations.
> + *
> + * $$$$ - Data area, unconsumed captured trace data, not to be overridden
> + * #### - Free area, enabled, trace will be written
> + * %%%% - Free area, disabled, trace will not be written
> + * ==== - Free area, padded with ETE_IGNORE_PACKET, trace will be skipped
> + */
> +static unsigned long __trbe_normal_offset(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	struct trbe_cpudata *cpudata = buf->cpudata;
> +	const u64 bufsize = buf->nr_pages * PAGE_SIZE;
> +	u64 limit = bufsize;
> +	u64 head, tail, wakeup;
> +
> +	head = PERF_IDX2OFF(handle->head, buf);
> +
> +	/*
> +	 *		head
> +	 *	------->|
> +	 *	|
> +	 *	head	TRBE align	tail
> +	 * +----|-------|---------------|-------+
> +	 * |$$$$|=======|###############|$$$$$$$|
> +	 * +----|-------|---------------|-------+
> +	 * trbe_base				trbe_base + nr_pages
> +	 *
> +	 * Perf aux buffer output head position can be misaligned depending on
> +	 * various factors including user space reads. In case misaligned, head
> +	 * needs to be aligned before TRBE can be configured. Pad the alignment
> +	 * gap with ETE_IGNORE_PACKET bytes that will be ignored by user tools
> +	 * and skip this section thus advancing the head.
> +	 */
> +	if (!IS_ALIGNED(head, cpudata->trbe_align)) {
> +		unsigned long delta = roundup(head, cpudata->trbe_align) - head;
> +
> +		delta = min(delta, handle->size);
> +		trbe_pad_buf(handle, delta);
> +		head = PERF_IDX2OFF(handle->head, buf);
> +	}
> +
> +	/*
> +	 *	head = tail (size = 0)
> +	 * +----|-------------------------------+
> +	 * |$$$$|$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$	|
> +	 * +----|-------------------------------+
> +	 * trbe_base				trbe_base + nr_pages
> +	 *
> +	 * Perf aux buffer does not have any space for the driver to write into.
> +	 * Just communicate trace truncation event to the user space by marking
> +	 * it with PERF_AUX_FLAG_TRUNCATED.
> +	 */
> +	if (!handle->size) {
> +		perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> +		return 0;
> +	}
> +
> +	/* Compute the tail and wakeup indices now that we've aligned head */
> +	tail = PERF_IDX2OFF(handle->head + handle->size, buf);
> +	wakeup = PERF_IDX2OFF(handle->wakeup, buf);
> +
> +	/*
> +	 * Lets calculate the buffer area which TRBE could write into. There
> +	 * are three possible scenarios here. Limit needs to be aligned with
> +	 * PAGE_SIZE per the TRBE requirement. Always avoid clobbering the
> +	 * unconsumed data.
> +	 *
> +	 * 1) head < tail
> +	 *
> +	 *	head			tail
> +	 * +----|-----------------------|-------+
> +	 * |$$$$|#######################|$$$$$$$|
> +	 * +----|-----------------------|-------+
> +	 * trbe_base			limit	trbe_base + nr_pages
> +	 *
> +	 * TRBE could write into [head..tail] area. Unless the tail is right at
> +	 * the end of the buffer, neither an wrap around nor an IRQ is expected
> +	 * while being enabled.
> +	 *
> +	 * 2) head == tail
> +	 *
> +	 *	head = tail (size > 0)
> +	 * +----|-------------------------------+
> +	 * |%%%%|###############################|
> +	 * +----|-------------------------------+
> +	 * trbe_base				limit = trbe_base + nr_pages
> +	 *
> +	 * TRBE should just write into [head..base + nr_pages] area even though
> +	 * the entire buffer is empty. Reason being, when the trace reaches the
> +	 * end of the buffer, it will just wrap around with an IRQ giving an
> +	 * opportunity to reconfigure the buffer.
> +	 *
> +	 * 3) tail < head
> +	 *
> +	 *	tail			head
> +	 * +----|-----------------------|-------+
> +	 * |%%%%|$$$$$$$$$$$$$$$$$$$$$$$|#######|
> +	 * +----|-----------------------|-------+
> +	 * trbe_base				limit = trbe_base + nr_pages
> +	 *
> +	 * TRBE should just write into [head..base + nr_pages] area even though
> +	 * the [trbe_base..tail] is also empty. Reason being, when the trace
> +	 * reaches the end of the buffer, it will just wrap around with an IRQ
> +	 * giving an opportunity to reconfigure the buffer.
> +	 */
> +	if (head < tail)
> +		limit = round_down(tail, PAGE_SIZE);
> +
> +	/*
> +	 * Wakeup may be arbitrarily far into the future. If it's not in the
> +	 * current generation, either we'll wrap before hitting it, or it's
> +	 * in the past and has been handled already.
> +	 *
> +	 * If there's a wakeup before we wrap, arrange to be woken up by the
> +	 * page boundary following it. Keep the tail boundary if that's lower.
> +	 *
> +	 *	head		wakeup	tail
> +	 * +----|---------------|-------|-------+
> +	 * |$$$$|###############|%%%%%%%|$$$$$$$|
> +	 * +----|---------------|-------|-------+
> +	 * trbe_base		limit		trbe_base + nr_pages
> +	 */
> +	if (handle->wakeup < (handle->head + handle->size) && head <= wakeup)
> +		limit = min(limit, round_up(wakeup, PAGE_SIZE));
> +
> +	/*
> +	 * There are two situation when this can happen i.e limit is before
> +	 * the head and hence TRBE cannot be configured.
> +	 *
> +	 * 1) head < tail (aligned down with PAGE_SIZE) and also they are both
> +	 * within the same PAGE size range.
> +	 *
> +	 *			PAGE_SIZE
> +	 *		|----------------------|
> +	 *
> +	 *		limit	head	tail
> +	 * +------------|------|--------|-------+
> +	 * |$$$$$$$$$$$$$$$$$$$|========|$$$$$$$|
> +	 * +------------|------|--------|-------+
> +	 * trbe_base				trbe_base + nr_pages
> +	 *
> +	 * 2) head < wakeup (aligned up with PAGE_SIZE) < tail and also both
> +	 * head and wakeup are within same PAGE size range.
> +	 *
> +	 *		PAGE_SIZE
> +	 *	|----------------------|
> +	 *
> +	 *	limit	head	wakeup  tail
> +	 * +----|------|-------|--------|-------+
> +	 * |$$$$$$$$$$$|=======|========|$$$$$$$|
> +	 * +----|------|-------|--------|-------+
> +	 * trbe_base				trbe_base + nr_pages
> +	 */
> +	if (limit > head)
> +		return limit;
> +
> +	trbe_pad_buf(handle, handle->size);
> +	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> +	return 0;
> +}
> +
> +static unsigned long trbe_normal_offset(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = perf_get_aux(handle);
> +	u64 limit = __trbe_normal_offset(handle);
> +	u64 head = PERF_IDX2OFF(handle->head, buf);
> +
> +	/*
> +	 * If the head is too close to the limit and we don't
> +	 * have space for a meaningful run, we rather pad it
> +	 * and start fresh.
> +	 */
> +	if (limit && (limit - head < TRBE_TRACE_MIN_BUF_SIZE)) {
> +		trbe_pad_buf(handle, limit - head);
> +		limit = __trbe_normal_offset(handle);
> +	}
> +	return limit;
> +}
> +
> +static unsigned long compute_trbe_buffer_limit(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	unsigned long offset;
> +
> +	if (buf->snapshot)
> +		offset = trbe_snapshot_offset(handle);
> +	else
> +		offset = trbe_normal_offset(handle);
> +	return buf->trbe_base + offset;
> +}
> +
> +static void clr_trbe_status(void)
> +{
> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
> +
> +	WARN_ON(is_trbe_enabled());
> +	trbsr &= ~TRBSR_IRQ;
> +	trbsr &= ~TRBSR_TRG;
> +	trbsr &= ~TRBSR_WRAP;
> +	trbsr &= ~(TRBSR_EC_MASK << TRBSR_EC_SHIFT);
> +	trbsr &= ~(TRBSR_BSC_MASK << TRBSR_BSC_SHIFT);
> +	trbsr &= ~TRBSR_STOP;
> +	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
> +}
> +
> +static void set_trbe_limit_pointer_enabled(unsigned long addr)
> +{
> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> +
> +	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> +
> +	trblimitr &= ~TRBLIMITR_NVM;
> +	trblimitr &= ~(TRBLIMITR_FILL_MODE_MASK << TRBLIMITR_FILL_MODE_SHIFT);
> +	trblimitr &= ~(TRBLIMITR_TRIG_MODE_MASK << TRBLIMITR_TRIG_MODE_SHIFT);
> +	trblimitr &= ~(TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT);
> +
> +	/*
> +	 * Fill trace buffer mode is used here while configuring the
> +	 * TRBE for trace capture. In this particular mode, the trace
> +	 * collection is stopped and a maintenance interrupt is raised
> +	 * when the current write pointer wraps. This pause in trace
> +	 * collection gives the software an opportunity to capture the
> +	 * trace data in the interrupt handler, before reconfiguring
> +	 * the TRBE.
> +	 */
> +	trblimitr |= (TRBE_FILL_MODE_FILL & TRBLIMITR_FILL_MODE_MASK) << TRBLIMITR_FILL_MODE_SHIFT;
> +
> +	/*
> +	 * Trigger mode is not used here while configuring the TRBE for
> +	 * the trace capture. Hence just keep this in the ignore mode.
> +	 */
> +	trblimitr |= (TRBE_TRIG_MODE_IGNORE & TRBLIMITR_TRIG_MODE_MASK) << TRBLIMITR_TRIG_MODE_SHIFT;
> +	trblimitr |= (addr & PAGE_MASK);
> +
> +	trblimitr |= TRBLIMITR_ENABLE;
> +	write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
> +}
> +
> +static void trbe_enable_hw(struct trbe_buf *buf)
> +{
> +	WARN_ON(buf->trbe_write < buf->trbe_base);
> +	WARN_ON(buf->trbe_write >= buf->trbe_limit);
> +	set_trbe_disabled();
> +	isb();
> +	clr_trbe_status();
> +	set_trbe_base_pointer(buf->trbe_base);
> +	set_trbe_write_pointer(buf->trbe_write);
> +
> +	/*
> +	 * Synchronize all the register updates
> +	 * till now before enabling the TRBE.
> +	 */
> +	isb();
> +	set_trbe_limit_pointer_enabled(buf->trbe_limit);
> +
> +	/* Synchronize the TRBE enable event */
> +	isb();
> +}
> +
> +static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
> +				   struct perf_event *event, void **pages,
> +				   int nr_pages, bool snapshot)
> +{
> +	struct trbe_buf *buf;
> +	struct page **pglist;
> +	int i;
> +
> +	/*
> +	 * TRBE LIMIT and TRBE WRITE pointers must be page aligned. But with
> +	 * just a single page, there is not much room left while writing into
> +	 * a partially filled TRBE buffer. Hence restrict the minimum buffer
> +	 * size as two pages.
> +	 */

I read this three times and event then I'm not sure to fully get it.  I
suggest re-working this paragraph.


> +	if (nr_pages < 2)
> +		return NULL;
> +
> +	buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
> +	if (IS_ERR(buf))
> +		return ERR_PTR(-ENOMEM);
> +
> +	pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
> +	if (IS_ERR(pglist)) {
> +		kfree(buf);
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	for (i = 0; i < nr_pages; i++)
> +		pglist[i] = virt_to_page(pages[i]);
> +
> +	buf->trbe_base = (unsigned long) vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
> +	if (IS_ERR((void *)buf->trbe_base)) {

Why not simply make buf->trbe_base a void * instead of having to do all this
casting?  And IS_ERR() doesn't work with vmap().

> +		kfree(pglist);
> +		kfree(buf);
> +		return ERR_PTR(buf->trbe_base);
> +	}
> +	buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
> +	buf->trbe_write = buf->trbe_base;
> +	buf->snapshot = snapshot;
> +	buf->nr_pages = nr_pages;
> +	buf->pages = pages;
> +	kfree(pglist);
> +	return buf;
> +}
> +
> +void arm_trbe_free_buffer(void *config)
> +{
> +	struct trbe_buf *buf = config;
> +
> +	vunmap((void *)buf->trbe_base);
> +	kfree(buf);
> +}
> +
> +static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
> +					    struct perf_output_handle *handle,
> +					    void *config)
> +{
> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> +	struct trbe_buf *buf = config;
> +	unsigned long size, offset;
> +
> +	WARN_ON(buf->cpudata != cpudata);
> +	WARN_ON(cpudata->cpu != smp_processor_id());
> +	WARN_ON(cpudata->drvdata != drvdata);
> +	if (cpudata->mode != CS_MODE_PERF)
> +		return -EINVAL;
> +
> +	/*
> +	 * If the TRBE was disabled due to lack of space in the AUX buffer or a
> +	 * spurious fault, the driver leaves it disabled, truncating the buffer.
> +	 * Since the etm_perf driver expects to close out the AUX buffer, the
> +	 * driver skips it. Thus, just pass in 0 size here to indicate that the
> +	 * buffer was truncated.
> +	 */
> +	if (!is_trbe_enabled())
> +		return 0;
> +	/*
> +	 * perf handle structure needs to be shared with the TRBE IRQ handler for
> +	 * capturing trace data and restarting the handle. There is a probability
> +	 * of an undefined reference based crash when etm event is being stopped
> +	 * while a TRBE IRQ also getting processed. This happens due the release
> +	 * of perf handle via perf_aux_output_end() in etm_event_stop(). Stopping
> +	 * the TRBE here will ensure that no IRQ could be generated when the perf
> +	 * handle gets freed in etm_event_stop().
> +	 */
> +	trbe_drain_and_disable_local();
> +	offset = get_trbe_write_pointer() - get_trbe_base_pointer();
> +	size = offset - PERF_IDX2OFF(handle->head, buf);
> +	if (buf->snapshot)
> +		handle->head += size;
> +	return size;
> +}
> +
> +static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)
> +{
> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> +	struct perf_output_handle *handle = data;
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +
> +	WARN_ON(cpudata->cpu != smp_processor_id());
> +	WARN_ON(cpudata->drvdata != drvdata);
> +	if (mode != CS_MODE_PERF)
> +		return -EINVAL;
> +
> +	*this_cpu_ptr(drvdata->handle) = handle;
> +	cpudata->buf = buf;
> +	cpudata->mode = mode;
> +	buf->cpudata = cpudata;
> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> +	if (buf->trbe_limit == buf->trbe_base) {
> +		trbe_stop_and_truncate_event(handle);
> +		return 0;
> +	}
> +	trbe_enable_hw(buf);
> +	return 0;
> +}
> +
> +static int arm_trbe_disable(struct coresight_device *csdev)
> +{
> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> +	struct trbe_buf *buf = cpudata->buf;
> +
> +	WARN_ON(buf->cpudata != cpudata);
> +	WARN_ON(cpudata->cpu != smp_processor_id());
> +	WARN_ON(cpudata->drvdata != drvdata);
> +	if (cpudata->mode != CS_MODE_PERF)
> +		return -EINVAL;
> +
> +	trbe_drain_and_disable_local();
> +	buf->cpudata = NULL;
> +	cpudata->buf = NULL;
> +	cpudata->mode = CS_MODE_DISABLED;
> +	return 0;
> +}
> +
> +static void trbe_handle_spurious(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +
> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> +	if (buf->trbe_limit == buf->trbe_base) {
> +		trbe_drain_and_disable_local();
> +		return;
> +	}
> +	trbe_enable_hw(buf);
> +}
> +
> +static void trbe_handle_overflow(struct perf_output_handle *handle)
> +{
> +	struct perf_event *event = handle->event;
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	unsigned long offset, size;
> +	struct etm_event_data *event_data;
> +
> +	offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
> +	size = offset - PERF_IDX2OFF(handle->head, buf);
> +	if (buf->snapshot)
> +		handle->head = offset;
> +	perf_aux_output_end(handle, size);
> +
> +	event_data = perf_aux_output_begin(handle, event);
> +	if (!event_data) {
> +		trbe_drain_and_disable_local();
> +		*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
> +		return;
> +	}
> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> +	if (buf->trbe_limit == buf->trbe_base) {
> +		trbe_stop_and_truncate_event(handle);
> +		return;
> +	}
> +	*this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;
> +	trbe_enable_hw(buf);
> +}
> +
> +static bool is_perf_trbe(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	struct trbe_cpudata *cpudata = buf->cpudata;
> +	struct trbe_drvdata *drvdata = cpudata->drvdata;
> +	int cpu = smp_processor_id();
> +
> +	WARN_ON(buf->trbe_base != get_trbe_base_pointer());
> +	WARN_ON(buf->trbe_limit != get_trbe_limit_pointer());
> +
> +	if (cpudata->mode != CS_MODE_PERF)
> +		return false;
> +
> +	if (cpudata->cpu != cpu)
> +		return false;
> +
> +	if (!cpumask_test_cpu(cpu, &drvdata->supported_cpus))
> +		return false;
> +
> +	return true;
> +}
> +
> +static enum trbe_fault_action trbe_get_fault_act(struct perf_output_handle *handle)
> +{
> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
> +	int ec = get_trbe_ec(trbsr);
> +	int bsc = get_trbe_bsc(trbsr);
> +
> +	WARN_ON(is_trbe_running(trbsr));
> +	if (is_trbe_trg(trbsr) || is_trbe_abort(trbsr))
> +		return TRBE_FAULT_ACT_FATAL;
> +
> +	if ((ec == TRBE_EC_STAGE1_ABORT) || (ec == TRBE_EC_STAGE2_ABORT))
> +		return TRBE_FAULT_ACT_FATAL;
> +
> +	if (is_trbe_wrap(trbsr) && (ec == TRBE_EC_OTHERS) && (bsc == TRBE_BSC_FILLED)) {
> +		if (get_trbe_write_pointer() == get_trbe_base_pointer())
> +			return TRBE_FAULT_ACT_WRAP;
> +	}
> +	return TRBE_FAULT_ACT_SPURIOUS;
> +}
> +
> +static irqreturn_t arm_trbe_irq_handler(int irq, void *dev)
> +{
> +	struct perf_output_handle **handle_ptr = dev;
> +	struct perf_output_handle *handle = *handle_ptr;
> +	enum trbe_fault_action act;
> +
> +	WARN_ON(!is_trbe_irq(read_sysreg_s(SYS_TRBSR_EL1)));
> +	clr_trbe_irq();
> +
> +	/*
> +	 * Ensure the trace is visible to the CPUs and
> +	 * any external aborts have been resolved.
> +	 */
> +	trbe_drain_buffer();
> +	isb();
> +
> +	if (!perf_get_aux(handle))
> +		return IRQ_NONE;
> +
> +	if (!is_perf_trbe(handle))
> +		return IRQ_NONE;
> +
> +	irq_work_run();
> +
> +	act = trbe_get_fault_act(handle);
> +	switch (act) {
> +	case TRBE_FAULT_ACT_WRAP:
> +		trbe_handle_overflow(handle);
> +		break;
> +	case TRBE_FAULT_ACT_SPURIOUS:
> +		trbe_handle_spurious(handle);
> +		break;
> +	case TRBE_FAULT_ACT_FATAL:
> +		trbe_stop_and_truncate_event(handle);
> +		break;
> +	}
> +	return IRQ_HANDLED;
> +}
> +
> +static const struct coresight_ops_sink arm_trbe_sink_ops = {
> +	.enable		= arm_trbe_enable,
> +	.disable	= arm_trbe_disable,
> +	.alloc_buffer	= arm_trbe_alloc_buffer,
> +	.free_buffer	= arm_trbe_free_buffer,
> +	.update_buffer	= arm_trbe_update_buffer,
> +};
> +
> +static const struct coresight_ops arm_trbe_cs_ops = {
> +	.sink_ops	= &arm_trbe_sink_ops,
> +};
> +
> +static ssize_t align_show(struct device *dev, struct device_attribute *attr, char *buf)
> +{
> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
> +
> +	return sprintf(buf, "%llx\n", cpudata->trbe_align);
> +}
> +static DEVICE_ATTR_RO(align);
> +
> +static ssize_t dbm_show(struct device *dev, struct device_attribute *attr, char *buf)
> +{
> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
> +
> +	return sprintf(buf, "%d\n", cpudata->trbe_dbm);
> +}
> +static DEVICE_ATTR_RO(dbm);

What does "dbm" stand for?  Looking at the documentation for TRBIDR_EL1.F, I
don't see what "dbm" relates to.

> +
> +static struct attribute *arm_trbe_attrs[] = {
> +	&dev_attr_align.attr,
> +	&dev_attr_dbm.attr,
> +	NULL,
> +};
> +
> +static const struct attribute_group arm_trbe_group = {
> +	.attrs = arm_trbe_attrs,
> +};
> +
> +static const struct attribute_group *arm_trbe_groups[] = {
> +	&arm_trbe_group,
> +	NULL,
> +};
> +
> +static void arm_trbe_probe_coresight_cpu(void *info)
> +{
> +	struct trbe_drvdata *drvdata = info;
> +	struct coresight_desc desc = { 0 };
> +	int cpu = smp_processor_id();
> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
> +	u64 trbidr = read_sysreg_s(SYS_TRBIDR_EL1);
> +	struct device *dev;
> +
> +	if (WARN_ON(!cpudata))
> +		goto cpu_clear;
> +
> +	if (trbe_csdev)
> +		return;
> +
> +	cpudata->cpu = smp_processor_id();
> +	cpudata->drvdata = drvdata;
> +	dev = &cpudata->drvdata->pdev->dev;
> +
> +	if (!is_trbe_available()) {
> +		pr_err("TRBE is not implemented on cpu %d\n", cpudata->cpu);
> +		goto cpu_clear;
> +	}
> +
> +	if (!is_trbe_programmable(trbidr)) {
> +		pr_err("TRBE is owned in higher exception level on cpu %d\n", cpudata->cpu);
> +		goto cpu_clear;
> +	}
> +	desc.name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", DRVNAME, smp_processor_id());
> +	if (IS_ERR(desc.name))
> +		goto cpu_clear;
> +
> +	desc.type = CORESIGHT_DEV_TYPE_SINK;
> +	desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
> +	desc.ops = &arm_trbe_cs_ops;
> +	desc.pdata = dev_get_platdata(dev);
> +	desc.groups = arm_trbe_groups;
> +	desc.dev = dev;
> +	trbe_csdev = coresight_register(&desc);
> +	if (IS_ERR(trbe_csdev))
> +		goto cpu_clear;
> +
> +	dev_set_drvdata(&trbe_csdev->dev, cpudata);
> +	cpudata->trbe_dbm = get_trbe_flag_update(trbidr);
> +	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
> +	if (cpudata->trbe_align > SZ_2K) {
> +		pr_err("Unsupported alignment on cpu %d\n", cpudata->cpu);
> +		goto cpu_clear;
> +	}
> +	per_cpu(csdev_sink, cpu) = trbe_csdev;
> +	trbe_reset_local();
> +	enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
> +	return;
> +cpu_clear:
> +	cpumask_clear_cpu(cpudata->cpu, &cpudata->drvdata->supported_cpus);
> +}
> +
> +static void arm_trbe_remove_coresight_cpu(void *info)
> +{
> +	int cpu = smp_processor_id();
> +	struct trbe_drvdata *drvdata = info;
> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
> +
> +	if (trbe_csdev) {
> +		coresight_unregister(trbe_csdev);
> +		cpudata->drvdata = NULL;
> +		per_cpu(csdev_sink, cpu) = NULL;
> +	}
> +	disable_percpu_irq(drvdata->irq);
> +	trbe_reset_local();
> +}
> +
> +static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata)
> +{
> +	drvdata->cpudata = alloc_percpu(typeof(*drvdata->cpudata));
> +	if (IS_ERR(drvdata->cpudata))
> +		return PTR_ERR(drvdata->cpudata);
> +
> +	arm_trbe_probe_coresight_cpu(drvdata);
> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_probe_coresight_cpu, drvdata, 1);
> +	return 0;
> +}
> +
> +static int arm_trbe_remove_coresight(struct trbe_drvdata *drvdata)
> +{
> +	arm_trbe_remove_coresight_cpu(drvdata);
> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_remove_coresight_cpu, drvdata, 1);
> +	free_percpu(drvdata->cpudata);
> +	return 0;
> +}
> +
> +static int arm_trbe_cpu_startup(unsigned int cpu, struct hlist_node *node)
> +{
> +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
> +
> +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
> +		if (!per_cpu(csdev_sink, cpu)) {
> +			arm_trbe_probe_coresight_cpu(drvdata);
> +		} else {
> +			trbe_reset_local();
> +			enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
> +		}
> +	}
> +	return 0;
> +}
> +
> +static int arm_trbe_cpu_teardown(unsigned int cpu, struct hlist_node *node)
> +{
> +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
> +
> +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
> +		disable_percpu_irq(drvdata->irq);
> +		trbe_reset_local();
> +	}
> +	return 0;
> +}
> +
> +static int arm_trbe_probe_cpuhp(struct trbe_drvdata *drvdata)
> +{
> +	enum cpuhp_state trbe_online;
> +
> +	trbe_online = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
> +					arm_trbe_cpu_startup, arm_trbe_cpu_teardown);

Indentation

        trbe_online = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
                                              arm_trbe_cpu_startup,
                                              arm_trbe_cpu_teardown);

> +	if (trbe_online < 0)
> +		return -EINVAL

Wrong error code 

> +
> +	if (cpuhp_state_add_instance(trbe_online, &drvdata->hotplug_node))
> +		return -EINVAL;

Wrong error code. Even if the callbacks aren't called it might be a good idea to
properly cleanup the with cpuhp_remove_multi_state().

More to come tomorrow.

Thanks,
Mathieu

> +
> +	drvdata->trbe_online = trbe_online;
> +	return 0;
> +}
> +
> +static void arm_trbe_remove_cpuhp(struct trbe_drvdata *drvdata)
> +{
> +	cpuhp_remove_multi_state(drvdata->trbe_online);
> +}
> +
> +static int arm_trbe_probe_irq(struct platform_device *pdev,
> +			      struct trbe_drvdata *drvdata)
> +{
> +	drvdata->irq = platform_get_irq(pdev, 0);
> +	if (!drvdata->irq) {
> +		pr_err("IRQ not found for the platform device\n");
> +		return -ENXIO;
> +	}
> +
> +	if (!irq_is_percpu(drvdata->irq)) {
> +		pr_err("IRQ is not a PPI\n");
> +		return -EINVAL;
> +	}
> +
> +	if (irq_get_percpu_devid_partition(drvdata->irq, &drvdata->supported_cpus))
> +		return -EINVAL;
> +
> +	drvdata->handle = alloc_percpu(typeof(*drvdata->handle));
> +	if (!drvdata->handle)
> +		return -ENOMEM;
> +
> +	if (request_percpu_irq(drvdata->irq, arm_trbe_irq_handler, DRVNAME, drvdata->handle)) {
> +		free_percpu(drvdata->handle);
> +		return -EINVAL;
> +	}
> +	return 0;
> +}
> +
> +static void arm_trbe_remove_irq(struct trbe_drvdata *drvdata)
> +{
> +	free_percpu_irq(drvdata->irq, drvdata->handle);
> +	free_percpu(drvdata->handle);
> +}
> +
> +static int arm_trbe_device_probe(struct platform_device *pdev)
> +{
> +	struct coresight_platform_data *pdata;
> +	struct trbe_drvdata *drvdata;
> +	struct device *dev = &pdev->dev;
> +	int ret;
> +
> +	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> +	if (IS_ERR(drvdata))
> +		return -ENOMEM;
> +
> +	pdata = coresight_get_platform_data(dev);
> +	if (IS_ERR(pdata)) {
> +		kfree(drvdata);
> +		return -ENOMEM;
> +	}
> +
> +	dev_set_drvdata(dev, drvdata);
> +	dev->platform_data = pdata;
> +	drvdata->pdev = pdev;
> +	ret = arm_trbe_probe_irq(pdev, drvdata);
> +	if (ret)
> +		goto irq_failed;
> +
> +	ret = arm_trbe_probe_coresight(drvdata);
> +	if (ret)
> +		goto probe_failed;
> +
> +	ret = arm_trbe_probe_cpuhp(drvdata);
> +	if (ret)
> +		goto cpuhp_failed;
> +
> +	return 0;
> +cpuhp_failed:
> +	arm_trbe_remove_coresight(drvdata);
> +probe_failed:
> +	arm_trbe_remove_irq(drvdata);
> +irq_failed:
> +	kfree(pdata);
> +	kfree(drvdata);
> +	return ret;
> +}
> +
> +static int arm_trbe_device_remove(struct platform_device *pdev)
> +{
> +	struct coresight_platform_data *pdata = dev_get_platdata(&pdev->dev);
> +	struct trbe_drvdata *drvdata = platform_get_drvdata(pdev);
> +
> +	arm_trbe_remove_coresight(drvdata);
> +	arm_trbe_remove_cpuhp(drvdata);

Shouldn't this be called before arm_trbe_remove_coresight()?

> +	arm_trbe_remove_irq(drvdata);
> +	kfree(pdata);
> +	kfree(drvdata);
> +	return 0;
> +}
> +
> +static const struct of_device_id arm_trbe_of_match[] = {
> +	{ .compatible = "arm,trace-buffer-extension"},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, arm_trbe_of_match);
> +
> +static struct platform_driver arm_trbe_driver = {
> +	.driver	= {
> +		.name = DRVNAME,
> +		.of_match_table = of_match_ptr(arm_trbe_of_match),
> +		.suppress_bind_attrs = true,
> +	},
> +	.probe	= arm_trbe_device_probe,
> +	.remove	= arm_trbe_device_remove,
> +};
> +
> +static int __init arm_trbe_init(void)
> +{
> +	int ret;
> +
> +	if (arm64_kernel_unmapped_at_el0()) {
> +		pr_err("TRBE wouldn't work if kernel gets unmapped at EL0\n");
> +		return -EOPNOTSUPP;
> +	}
> +
> +	ret = platform_driver_register(&arm_trbe_driver);
> +	if (!ret)
> +		return 0;
> +
> +	pr_err("Error registering %s platform driver\n", DRVNAME);
> +	return ret;
> +}
> +
> +static void __exit arm_trbe_exit(void)
> +{
> +	platform_driver_unregister(&arm_trbe_driver);
> +}
> +module_init(arm_trbe_init);
> +module_exit(arm_trbe_exit);
> +
> +MODULE_AUTHOR("Anshuman Khandual <anshuman.khandual@arm.com>");
> +MODULE_DESCRIPTION("Arm Trace Buffer Extension (TRBE) driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h
> new file mode 100644
> index 0000000..43308bc
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-trbe.h
> @@ -0,0 +1,160 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This contains all required hardware related helper functions for
> + * Trace Buffer Extension (TRBE) driver in the coresight framework.
> + *
> + * Copyright (C) 2020 ARM Ltd.
> + *
> + * Author: Anshuman Khandual <anshuman.khandual@arm.com>
> + */
> +#include <linux/coresight.h>
> +#include <linux/device.h>
> +#include <linux/irq.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/smp.h>
> +
> +#include "coresight-etm-perf.h"
> +
> +DECLARE_PER_CPU(struct coresight_device *, csdev_sink);
> +
> +static inline bool is_trbe_available(void)
> +{
> +	u64 aa64dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
> +	unsigned int trbe = cpuid_feature_extract_unsigned_field(aa64dfr0, ID_AA64DFR0_TRBE_SHIFT);
> +
> +	return trbe >= 0b0001;
> +}
> +
> +static inline bool is_trbe_enabled(void)
> +{
> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> +
> +	return trblimitr & TRBLIMITR_ENABLE;
> +}
> +
> +#define TRBE_EC_OTHERS		0
> +#define TRBE_EC_STAGE1_ABORT	36
> +#define TRBE_EC_STAGE2_ABORT	37
> +
> +static inline int get_trbe_ec(u64 trbsr)
> +{
> +	return (trbsr >> TRBSR_EC_SHIFT) & TRBSR_EC_MASK;
> +}
> +
> +#define TRBE_BSC_NOT_STOPPED	0
> +#define	TRBE_BSC_FILLED		1
> +#define TRBE_BSC_TRIGGERED	2
> +
> +static inline int get_trbe_bsc(u64 trbsr)
> +{
> +	return (trbsr >> TRBSR_BSC_SHIFT) & TRBSR_BSC_MASK;
> +}
> +
> +static inline void clr_trbe_irq(void)
> +{
> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
> +
> +	trbsr &= ~TRBSR_IRQ;
> +	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
> +}
> +
> +static inline bool is_trbe_irq(u64 trbsr)
> +{
> +	return trbsr & TRBSR_IRQ;
> +}
> +
> +static inline bool is_trbe_trg(u64 trbsr)
> +{
> +	return trbsr & TRBSR_TRG;
> +}
> +
> +static inline bool is_trbe_wrap(u64 trbsr)
> +{
> +	return trbsr & TRBSR_WRAP;
> +}
> +
> +static inline bool is_trbe_abort(u64 trbsr)
> +{
> +	return trbsr & TRBSR_ABORT;
> +}
> +
> +static inline bool is_trbe_running(u64 trbsr)
> +{
> +	return !(trbsr & TRBSR_STOP);
> +}
> +
> +#define TRBE_TRIG_MODE_STOP		0
> +#define TRBE_TRIG_MODE_IRQ		1
> +#define TRBE_TRIG_MODE_IGNORE		3
> +
> +#define TRBE_FILL_MODE_FILL		0
> +#define TRBE_FILL_MODE_WRAP		1
> +#define TRBE_FILL_MODE_CIRCULAR_BUFFER	3
> +
> +static inline void set_trbe_disabled(void)
> +{
> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> +
> +	trblimitr &= ~TRBLIMITR_ENABLE;
> +	write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
> +}
> +
> +static inline bool get_trbe_flag_update(u64 trbidr)
> +{
> +	return trbidr & TRBIDR_FLAG;
> +}
> +
> +static inline bool is_trbe_programmable(u64 trbidr)
> +{
> +	return !(trbidr & TRBIDR_PROG);
> +}
> +
> +static inline int get_trbe_address_align(u64 trbidr)
> +{
> +	return (trbidr >> TRBIDR_ALIGN_SHIFT) & TRBIDR_ALIGN_MASK;
> +}
> +
> +static inline unsigned long get_trbe_write_pointer(void)
> +{
> +	u64 trbptr = read_sysreg_s(SYS_TRBPTR_EL1);
> +	unsigned long addr = (trbptr >> TRBPTR_PTR_SHIFT) & TRBPTR_PTR_MASK;
> +
> +	return addr;
> +}
> +
> +static inline void set_trbe_write_pointer(unsigned long addr)
> +{
> +	WARN_ON(is_trbe_enabled());
> +	addr = (addr >> TRBPTR_PTR_SHIFT) & TRBPTR_PTR_MASK;
> +	write_sysreg_s(addr, SYS_TRBPTR_EL1);
> +}
> +
> +static inline unsigned long get_trbe_limit_pointer(void)
> +{
> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> +	unsigned long limit = (trblimitr >> TRBLIMITR_LIMIT_SHIFT) & TRBLIMITR_LIMIT_MASK;
> +	unsigned long addr = limit << TRBLIMITR_LIMIT_SHIFT;
> +
> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> +	return addr;
> +}
> +
> +static inline unsigned long get_trbe_base_pointer(void)
> +{
> +	u64 trbbaser = read_sysreg_s(SYS_TRBBASER_EL1);
> +	unsigned long addr = (trbbaser >> TRBBASER_BASE_SHIFT) & TRBBASER_BASE_MASK;
> +
> +	addr = addr << TRBBASER_BASE_SHIFT;
> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> +	return addr;
> +}
> +
> +static inline void set_trbe_base_pointer(unsigned long addr)
> +{
> +	WARN_ON(is_trbe_enabled());
> +	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> +	write_sysreg_s(addr, SYS_TRBBASER_EL1);
> +}
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-02-11 19:00   ` Mathieu Poirier
@ 2021-02-12  3:31     ` Anshuman Khandual
  2021-02-12 16:57       ` Mathieu Poirier
  0 siblings, 1 reply; 90+ messages in thread
From: Anshuman Khandual @ 2021-02-12  3:31 UTC (permalink / raw)
  To: Mathieu Poirier
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel



On 2/12/21 12:30 AM, Mathieu Poirier wrote:
> On Wed, Jan 27, 2021 at 02:25:35PM +0530, Anshuman Khandual wrote:
>> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
>> accessible via the system registers. The TRBE supports different addressing
>> modes including CPU virtual address and buffer modes including the circular
>> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
>> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
>> access to the trace buffer could be prohibited by a higher exception level
>> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
>> private interrupt (PPI) on address translation errors and when the buffer
>> is full. Overall implementation here is inspired from the Arm SPE driver.
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> Changes in V3:
>>
>> - Added new DT bindings document TRBE.yaml
>> - Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3
>> - Dropped isb() from trbe_reset_local()
>> - Dropped gap between (void *) and buf->trbe_base
>> - Changed 'int' to 'unsigned int' in is_trbe_available()
>> - Dropped unused function set_trbe_running(), set_trbe_virtual_mode(),
>>   set_trbe_enabled() and set_trbe_limit_pointer()
>> - Changed get_trbe_flag_update(), is_trbe_programmable() and
>>   get_trbe_address_align() to accept TRBIDR value
>> - Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), is_trbe_trg(),
>>   is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value
>> - Dropped snapshot mode condition in arm_trbe_alloc_buffer()
>> - Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled
>> - Compute trbe_limit before trbe_write to get the updated handle
>> - Added trbe_stop_and_truncate_event()
>> - Dropped trbe_handle_fatal()
>>
>>  Documentation/trace/coresight/coresight-trbe.rst |   39 +
>>  arch/arm64/include/asm/sysreg.h                  |    1 +
>>  drivers/hwtracing/coresight/Kconfig              |   11 +
>>  drivers/hwtracing/coresight/Makefile             |    1 +
>>  drivers/hwtracing/coresight/coresight-trbe.c     | 1023 ++++++++++++++++++++++
>>  drivers/hwtracing/coresight/coresight-trbe.h     |  160 ++++
>>  6 files changed, 1235 insertions(+)
>>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
>>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
>>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
>>
>> diff --git a/Documentation/trace/coresight/coresight-trbe.rst b/Documentation/trace/coresight/coresight-trbe.rst
>> new file mode 100644
>> index 0000000..1cbb819
>> --- /dev/null
>> +++ b/Documentation/trace/coresight/coresight-trbe.rst
>> @@ -0,0 +1,39 @@
>> +.. SPDX-License-Identifier: GPL-2.0
>> +
>> +==============================
>> +Trace Buffer Extension (TRBE).
>> +==============================
>> +
>> +    :Author:   Anshuman Khandual <anshuman.khandual@arm.com>
>> +    :Date:     November 2020
>> +
>> +Hardware Description
>> +--------------------
>> +
>> +Trace Buffer Extension (TRBE) is a percpu hardware which captures in system
>> +memory, CPU traces generated from a corresponding percpu tracing unit. This
>> +gets plugged in as a coresight sink device because the corresponding trace
>> +genarators (ETE), are plugged in as source device.
>> +
>> +The TRBE is not compliant to CoreSight architecture specifications, but is
>> +driven via the CoreSight driver framework to support the ETE (which is
>> +CoreSight compliant) integration.
>> +
>> +Sysfs files and directories
>> +---------------------------
>> +
>> +The TRBE devices appear on the existing coresight bus alongside the other
>> +coresight devices::
>> +
>> +	>$ ls /sys/bus/coresight/devices
>> +	trbe0  trbe1  trbe2 trbe3
>> +
>> +The ``trbe<N>`` named TRBEs are associated with a CPU.::
>> +
>> +	>$ ls /sys/bus/coresight/devices/trbe0/
>> +        align dbm
>> +
>> +*Key file items are:-*
>> +   * ``align``: TRBE write pointer alignment
>> +   * ``dbm``: TRBE updates memory with access and dirty flags
>> +
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 85ae4db..9e2e9b7 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -97,6 +97,7 @@
>>  #define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
>>  #define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
>>  #define SET_PSTATE_TCO(x)		__emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
>> +#define TSB_CSYNC			__emit_inst(0xd503225f)
>>  
>>  #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
>>  #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
>> index f154ae7..aa657ab 100644
>> --- a/drivers/hwtracing/coresight/Kconfig
>> +++ b/drivers/hwtracing/coresight/Kconfig
>> @@ -164,6 +164,17 @@ config CORESIGHT_CTI
>>  	  To compile this driver as a module, choose M here: the
>>  	  module will be called coresight-cti.
>>  
>> +config CORESIGHT_TRBE
>> +	bool "Trace Buffer Extension (TRBE) driver"
>> +	depends on ARM64
>> +	help
>> +	  This driver provides support for percpu Trace Buffer Extension (TRBE).
>> +	  TRBE always needs to be used along with it's corresponding percpu ETE
>> +	  component. ETE generates trace data which is then captured with TRBE.
>> +	  Unlike traditional sink devices, TRBE is a CPU feature accessible via
>> +	  system registers. But it's explicit dependency with trace unit (ETE)
>> +	  requires it to be plugged in as a coresight sink device.
>> +
>>  config CORESIGHT_CTI_INTEGRATION_REGS
>>  	bool "Access CTI CoreSight Integration Registers"
>>  	depends on CORESIGHT_CTI
>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
>> index f20e357..d608165 100644
>> --- a/drivers/hwtracing/coresight/Makefile
>> +++ b/drivers/hwtracing/coresight/Makefile
>> @@ -21,5 +21,6 @@ obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
>>  obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
>>  obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
>>  obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
>> +obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
>>  coresight-cti-y := coresight-cti-core.o	coresight-cti-platform.o \
>>  		   coresight-cti-sysfs.o
>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
>> new file mode 100644
>> index 0000000..1464d8b
>> --- /dev/null
>> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
>> @@ -0,0 +1,1023 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * This driver enables Trace Buffer Extension (TRBE) as a per-cpu coresight
>> + * sink device could then pair with an appropriate per-cpu coresight source
>> + * device (ETE) thus generating required trace data. Trace can be enabled
>> + * via the perf framework.
>> + *
>> + * Copyright (C) 2020 ARM Ltd.
>> + *
>> + * Author: Anshuman Khandual <anshuman.khandual@arm.com>
>> + */
>> +#define DRVNAME "arm_trbe"
>> +
>> +#define pr_fmt(fmt) DRVNAME ": " fmt
>> +
>> +#include "coresight-trbe.h"
>> +
>> +#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
>> +
>> +/*
>> + * A padding packet that will help the user space tools
>> + * in skipping relevant sections in the captured trace
>> + * data which could not be decoded. TRBE doesn't support
>> + * formatting the trace data, unlike the legacy CoreSight
>> + * sinks and thus we use ETE trace packets to pad the
>> + * sections of the buffer.
>> + */
>> +#define ETE_IGNORE_PACKET 		0x70
>> +
>> +/*
>> + * Minimum amount of meaningful trace will contain:
>> + * A-Sync, Trace Info, Trace On, Address, Atom.
>> + * This is about 44bytes of ETE trace. To be on
>> + * the safer side, we assume 64bytes is the minimum
>> + * space required for a meaningful session, before
>> + * we hit a "WRAP" event.
>> + */
>> +#define TRBE_TRACE_MIN_BUF_SIZE		64
>> +
>> +enum trbe_fault_action {
>> +	TRBE_FAULT_ACT_WRAP,
>> +	TRBE_FAULT_ACT_SPURIOUS,
>> +	TRBE_FAULT_ACT_FATAL,
>> +};
>> +
>> +struct trbe_buf {
>> +	unsigned long trbe_base;
>> +	unsigned long trbe_limit;
>> +	unsigned long trbe_write;
>> +	int nr_pages;
>> +	void **pages;
>> +	bool snapshot;
>> +	struct trbe_cpudata *cpudata;
>> +};
>> +
>> +struct trbe_cpudata {
>> +	bool trbe_dbm;
>> +	u64 trbe_align;
>> +	int cpu;
>> +	enum cs_mode mode;
>> +	struct trbe_buf *buf;
>> +	struct trbe_drvdata *drvdata;
>> +};
>> +
>> +struct trbe_drvdata {
>> +	struct trbe_cpudata __percpu *cpudata;
>> +	struct perf_output_handle __percpu **handle;
>> +	struct hlist_node hotplug_node;
>> +	int irq;
>> +	cpumask_t supported_cpus;
>> +	enum cpuhp_state trbe_online;
>> +	struct platform_device *pdev;
>> +};
>> +
>> +static int trbe_alloc_node(struct perf_event *event)
>> +{
>> +	if (event->cpu == -1)
>> +		return NUMA_NO_NODE;
>> +	return cpu_to_node(event->cpu);
>> +}
>> +
>> +static void trbe_drain_buffer(void)
>> +{
>> +	asm(TSB_CSYNC);
>> +	dsb(nsh);
>> +}
>> +
>> +static void trbe_drain_and_disable_local(void)
>> +{
>> +	trbe_drain_buffer();
>> +	write_sysreg_s(0, SYS_TRBLIMITR_EL1);
>> +	isb();
>> +}
>> +
>> +static void trbe_reset_local(void)
>> +{
>> +	trbe_drain_and_disable_local();
>> +	write_sysreg_s(0, SYS_TRBPTR_EL1);
>> +	write_sysreg_s(0, SYS_TRBBASER_EL1);
>> +	write_sysreg_s(0, SYS_TRBSR_EL1);
>> +}
>> +
>> +static void trbe_stop_and_truncate_event(struct perf_output_handle *handle)
>> +{
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +
>> +	/*
>> +	 * We cannot proceed with the buffer collection and we
>> +	 * do not have any data for the current session. The
>> +	 * etm_perf driver expects to close out the aux_buffer
>> +	 * at event_stop(). So disable the TRBE here and leave
>> +	 * the update_buffer() to return a 0 size.
>> +	 */
>> +	trbe_drain_and_disable_local();
>> +	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
>> +	*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
>> +}
>> +
>> +/*
>> + * TRBE Buffer Management
>> + *
>> + * The TRBE buffer spans from the base pointer till the limit pointer. When enabled,
>> + * it starts writing trace data from the write pointer onward till the limit pointer.
>> + * When the write pointer reaches the address just before the limit pointer, it gets
>> + * wrapped around again to the base pointer. This is called a TRBE wrap event, which
>> + * generates a maintenance interrupt when operated in WRAP or FILL mode. This driver
>> + * uses FILL mode, where the TRBE stops the trace collection at wrap event. The IRQ
>> + * handler updates the AUX buffer and re-enables the TRBE with updated WRITE and
>> + * LIMIT pointers.
>> + *
>> + *	Wrap around with an IRQ
>> + *	------ < ------ < ------- < ----- < -----
>> + *	|					|
>> + *	------ > ------ > ------- > ----- > -----
>> + *
>> + *	+---------------+-----------------------+
>> + *	|		|			|
>> + *	+---------------+-----------------------+
>> + *	Base Pointer	Write Pointer		Limit Pointer
>> + *
>> + * The base and limit pointers always needs to be PAGE_SIZE aligned. But the write
>> + * pointer can be aligned to the implementation defined TRBE trace buffer alignment
>> + * as captured in trbe_cpudata->trbe_align.
>> + *
>> + *
>> + *		head		tail		wakeup
>> + *	+---------------------------------------+----- ~ ~ ------
>> + *	|$$$$$$$|################|$$$$$$$$$$$$$$|		|
>> + *	+---------------------------------------+----- ~ ~ ------
>> + *	Base Pointer	Write Pointer		Limit Pointer
>> + *
>> + * The perf_output_handle indices (head, tail, wakeup) are monotonically increasing
>> + * values which tracks all the driver writes and user reads from the perf auxiliary
>> + * buffer. Generally [head..tail] is the area where the driver can write into unless
>> + * the wakeup is behind the tail. Enabled TRBE buffer span needs to be adjusted and
>> + * configured depending on the perf_output_handle indices, so that the driver does
>> + * not override into areas in the perf auxiliary buffer which is being or yet to be
>> + * consumed from the user space. The enabled TRBE buffer area is a moving subset of
>> + * the allocated perf auxiliary buffer.
>> + */
>> +static void trbe_pad_buf(struct perf_output_handle *handle, int len)
>> +{
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +	u64 head = PERF_IDX2OFF(handle->head, buf);
>> +
>> +	memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
>> +	if (!buf->snapshot)
>> +		perf_aux_output_skip(handle, len);
>> +}
>> +
>> +static unsigned long trbe_snapshot_offset(struct perf_output_handle *handle)
>> +{
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +
>> +	/*
>> +	 * The ETE trace has alignment synchronization packets allowing
>> +	 * the decoder to reset in case of an overflow or corruption.
>> +	 * So we can use the entire buffer for the snapshot mode.
>> +	 */
>> +	return buf->nr_pages * PAGE_SIZE;
>> +}
>> +
>> +/*
>> + * TRBE Limit Calculation
>> + *
>> + * The following markers are used to illustrate various TRBE buffer situations.
>> + *
>> + * $$$$ - Data area, unconsumed captured trace data, not to be overridden
>> + * #### - Free area, enabled, trace will be written
>> + * %%%% - Free area, disabled, trace will not be written
>> + * ==== - Free area, padded with ETE_IGNORE_PACKET, trace will be skipped
>> + */
>> +static unsigned long __trbe_normal_offset(struct perf_output_handle *handle)
>> +{
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +	struct trbe_cpudata *cpudata = buf->cpudata;
>> +	const u64 bufsize = buf->nr_pages * PAGE_SIZE;
>> +	u64 limit = bufsize;
>> +	u64 head, tail, wakeup;
>> +
>> +	head = PERF_IDX2OFF(handle->head, buf);
>> +
>> +	/*
>> +	 *		head
>> +	 *	------->|
>> +	 *	|
>> +	 *	head	TRBE align	tail
>> +	 * +----|-------|---------------|-------+
>> +	 * |$$$$|=======|###############|$$$$$$$|
>> +	 * +----|-------|---------------|-------+
>> +	 * trbe_base				trbe_base + nr_pages
>> +	 *
>> +	 * Perf aux buffer output head position can be misaligned depending on
>> +	 * various factors including user space reads. In case misaligned, head
>> +	 * needs to be aligned before TRBE can be configured. Pad the alignment
>> +	 * gap with ETE_IGNORE_PACKET bytes that will be ignored by user tools
>> +	 * and skip this section thus advancing the head.
>> +	 */
>> +	if (!IS_ALIGNED(head, cpudata->trbe_align)) {
>> +		unsigned long delta = roundup(head, cpudata->trbe_align) - head;
>> +
>> +		delta = min(delta, handle->size);
>> +		trbe_pad_buf(handle, delta);
>> +		head = PERF_IDX2OFF(handle->head, buf);
>> +	}
>> +
>> +	/*
>> +	 *	head = tail (size = 0)
>> +	 * +----|-------------------------------+
>> +	 * |$$$$|$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$	|
>> +	 * +----|-------------------------------+
>> +	 * trbe_base				trbe_base + nr_pages
>> +	 *
>> +	 * Perf aux buffer does not have any space for the driver to write into.
>> +	 * Just communicate trace truncation event to the user space by marking
>> +	 * it with PERF_AUX_FLAG_TRUNCATED.
>> +	 */
>> +	if (!handle->size) {
>> +		perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
>> +		return 0;
>> +	}
>> +
>> +	/* Compute the tail and wakeup indices now that we've aligned head */
>> +	tail = PERF_IDX2OFF(handle->head + handle->size, buf);
>> +	wakeup = PERF_IDX2OFF(handle->wakeup, buf);
>> +
>> +	/*
>> +	 * Lets calculate the buffer area which TRBE could write into. There
>> +	 * are three possible scenarios here. Limit needs to be aligned with
>> +	 * PAGE_SIZE per the TRBE requirement. Always avoid clobbering the
>> +	 * unconsumed data.
>> +	 *
>> +	 * 1) head < tail
>> +	 *
>> +	 *	head			tail
>> +	 * +----|-----------------------|-------+
>> +	 * |$$$$|#######################|$$$$$$$|
>> +	 * +----|-----------------------|-------+
>> +	 * trbe_base			limit	trbe_base + nr_pages
>> +	 *
>> +	 * TRBE could write into [head..tail] area. Unless the tail is right at
>> +	 * the end of the buffer, neither an wrap around nor an IRQ is expected
>> +	 * while being enabled.
>> +	 *
>> +	 * 2) head == tail
>> +	 *
>> +	 *	head = tail (size > 0)
>> +	 * +----|-------------------------------+
>> +	 * |%%%%|###############################|
>> +	 * +----|-------------------------------+
>> +	 * trbe_base				limit = trbe_base + nr_pages
>> +	 *
>> +	 * TRBE should just write into [head..base + nr_pages] area even though
>> +	 * the entire buffer is empty. Reason being, when the trace reaches the
>> +	 * end of the buffer, it will just wrap around with an IRQ giving an
>> +	 * opportunity to reconfigure the buffer.
>> +	 *
>> +	 * 3) tail < head
>> +	 *
>> +	 *	tail			head
>> +	 * +----|-----------------------|-------+
>> +	 * |%%%%|$$$$$$$$$$$$$$$$$$$$$$$|#######|
>> +	 * +----|-----------------------|-------+
>> +	 * trbe_base				limit = trbe_base + nr_pages
>> +	 *
>> +	 * TRBE should just write into [head..base + nr_pages] area even though
>> +	 * the [trbe_base..tail] is also empty. Reason being, when the trace
>> +	 * reaches the end of the buffer, it will just wrap around with an IRQ
>> +	 * giving an opportunity to reconfigure the buffer.
>> +	 */
>> +	if (head < tail)
>> +		limit = round_down(tail, PAGE_SIZE);
>> +
>> +	/*
>> +	 * Wakeup may be arbitrarily far into the future. If it's not in the
>> +	 * current generation, either we'll wrap before hitting it, or it's
>> +	 * in the past and has been handled already.
>> +	 *
>> +	 * If there's a wakeup before we wrap, arrange to be woken up by the
>> +	 * page boundary following it. Keep the tail boundary if that's lower.
>> +	 *
>> +	 *	head		wakeup	tail
>> +	 * +----|---------------|-------|-------+
>> +	 * |$$$$|###############|%%%%%%%|$$$$$$$|
>> +	 * +----|---------------|-------|-------+
>> +	 * trbe_base		limit		trbe_base + nr_pages
>> +	 */
>> +	if (handle->wakeup < (handle->head + handle->size) && head <= wakeup)
>> +		limit = min(limit, round_up(wakeup, PAGE_SIZE));
>> +
>> +	/*
>> +	 * There are two situation when this can happen i.e limit is before
>> +	 * the head and hence TRBE cannot be configured.
>> +	 *
>> +	 * 1) head < tail (aligned down with PAGE_SIZE) and also they are both
>> +	 * within the same PAGE size range.
>> +	 *
>> +	 *			PAGE_SIZE
>> +	 *		|----------------------|
>> +	 *
>> +	 *		limit	head	tail
>> +	 * +------------|------|--------|-------+
>> +	 * |$$$$$$$$$$$$$$$$$$$|========|$$$$$$$|
>> +	 * +------------|------|--------|-------+
>> +	 * trbe_base				trbe_base + nr_pages
>> +	 *
>> +	 * 2) head < wakeup (aligned up with PAGE_SIZE) < tail and also both
>> +	 * head and wakeup are within same PAGE size range.
>> +	 *
>> +	 *		PAGE_SIZE
>> +	 *	|----------------------|
>> +	 *
>> +	 *	limit	head	wakeup  tail
>> +	 * +----|------|-------|--------|-------+
>> +	 * |$$$$$$$$$$$|=======|========|$$$$$$$|
>> +	 * +----|------|-------|--------|-------+
>> +	 * trbe_base				trbe_base + nr_pages
>> +	 */
>> +	if (limit > head)
>> +		return limit;
>> +
>> +	trbe_pad_buf(handle, handle->size);
>> +	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
>> +	return 0;
>> +}
>> +
>> +static unsigned long trbe_normal_offset(struct perf_output_handle *handle)
>> +{
>> +	struct trbe_buf *buf = perf_get_aux(handle);
>> +	u64 limit = __trbe_normal_offset(handle);
>> +	u64 head = PERF_IDX2OFF(handle->head, buf);
>> +
>> +	/*
>> +	 * If the head is too close to the limit and we don't
>> +	 * have space for a meaningful run, we rather pad it
>> +	 * and start fresh.
>> +	 */
>> +	if (limit && (limit - head < TRBE_TRACE_MIN_BUF_SIZE)) {
>> +		trbe_pad_buf(handle, limit - head);
>> +		limit = __trbe_normal_offset(handle);
>> +	}
>> +	return limit;
>> +}
>> +
>> +static unsigned long compute_trbe_buffer_limit(struct perf_output_handle *handle)
>> +{
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +	unsigned long offset;
>> +
>> +	if (buf->snapshot)
>> +		offset = trbe_snapshot_offset(handle);
>> +	else
>> +		offset = trbe_normal_offset(handle);
>> +	return buf->trbe_base + offset;
>> +}
>> +
>> +static void clr_trbe_status(void)
>> +{
>> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
>> +
>> +	WARN_ON(is_trbe_enabled());
>> +	trbsr &= ~TRBSR_IRQ;
>> +	trbsr &= ~TRBSR_TRG;
>> +	trbsr &= ~TRBSR_WRAP;
>> +	trbsr &= ~(TRBSR_EC_MASK << TRBSR_EC_SHIFT);
>> +	trbsr &= ~(TRBSR_BSC_MASK << TRBSR_BSC_SHIFT);
>> +	trbsr &= ~TRBSR_STOP;
>> +	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
>> +}
>> +
>> +static void set_trbe_limit_pointer_enabled(unsigned long addr)
>> +{
>> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
>> +
>> +	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
>> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
>> +
>> +	trblimitr &= ~TRBLIMITR_NVM;
>> +	trblimitr &= ~(TRBLIMITR_FILL_MODE_MASK << TRBLIMITR_FILL_MODE_SHIFT);
>> +	trblimitr &= ~(TRBLIMITR_TRIG_MODE_MASK << TRBLIMITR_TRIG_MODE_SHIFT);
>> +	trblimitr &= ~(TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT);
>> +
>> +	/*
>> +	 * Fill trace buffer mode is used here while configuring the
>> +	 * TRBE for trace capture. In this particular mode, the trace
>> +	 * collection is stopped and a maintenance interrupt is raised
>> +	 * when the current write pointer wraps. This pause in trace
>> +	 * collection gives the software an opportunity to capture the
>> +	 * trace data in the interrupt handler, before reconfiguring
>> +	 * the TRBE.
>> +	 */
>> +	trblimitr |= (TRBE_FILL_MODE_FILL & TRBLIMITR_FILL_MODE_MASK) << TRBLIMITR_FILL_MODE_SHIFT;
>> +
>> +	/*
>> +	 * Trigger mode is not used here while configuring the TRBE for
>> +	 * the trace capture. Hence just keep this in the ignore mode.
>> +	 */
>> +	trblimitr |= (TRBE_TRIG_MODE_IGNORE & TRBLIMITR_TRIG_MODE_MASK) << TRBLIMITR_TRIG_MODE_SHIFT;
>> +	trblimitr |= (addr & PAGE_MASK);
>> +
>> +	trblimitr |= TRBLIMITR_ENABLE;
>> +	write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
>> +}
>> +
>> +static void trbe_enable_hw(struct trbe_buf *buf)
>> +{
>> +	WARN_ON(buf->trbe_write < buf->trbe_base);
>> +	WARN_ON(buf->trbe_write >= buf->trbe_limit);
>> +	set_trbe_disabled();
>> +	isb();
>> +	clr_trbe_status();
>> +	set_trbe_base_pointer(buf->trbe_base);
>> +	set_trbe_write_pointer(buf->trbe_write);
>> +
>> +	/*
>> +	 * Synchronize all the register updates
>> +	 * till now before enabling the TRBE.
>> +	 */
>> +	isb();
>> +	set_trbe_limit_pointer_enabled(buf->trbe_limit);
>> +
>> +	/* Synchronize the TRBE enable event */
>> +	isb();
>> +}
>> +
>> +static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
>> +				   struct perf_event *event, void **pages,
>> +				   int nr_pages, bool snapshot)
>> +{
>> +	struct trbe_buf *buf;
>> +	struct page **pglist;
>> +	int i;
>> +
>> +	/*
>> +	 * TRBE LIMIT and TRBE WRITE pointers must be page aligned. But with
>> +	 * just a single page, there is not much room left while writing into
>> +	 * a partially filled TRBE buffer. Hence restrict the minimum buffer
>> +	 * size as two pages.
>> +	 */
> 
> I read this three times and event then I'm not sure to fully get it.  I
> suggest re-working this paragraph.

I guess it should be "no room left" instead of "not much room left". If there
is only a single page and the buffer is partially filled, there wont be space
left to write the traces after the WRITE/LIMIT pointer's PAGE_SIZE alignment.

        /*
         * TRBE LIMIT and TRBE WRITE pointers must be page aligned. But with
         * just a single page, there would not be any room left while writing
         * into a partially filled TRBE buffer after the page size alignment.
         * Hence restrict the minimum buffer size as two pages.
         */

> 
> 
>> +	if (nr_pages < 2)
>> +		return NULL;
>> +
>> +	buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
>> +	if (IS_ERR(buf))
>> +		return ERR_PTR(-ENOMEM);
>> +
>> +	pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
>> +	if (IS_ERR(pglist)) {
>> +		kfree(buf);
>> +		return ERR_PTR(-ENOMEM);
>> +	}
>> +
>> +	for (i = 0; i < nr_pages; i++)
>> +		pglist[i] = virt_to_page(pages[i]);
>> +
>> +	buf->trbe_base = (unsigned long) vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
>> +	if (IS_ERR((void *)buf->trbe_base)) {
> 
> Why not simply make buf->trbe_base a void * instead of having to do all this

There are many arithmetic and comparison operations involving trbe_base
element. Hence it might be better to keep it as unsigned long, also to
keeps it consistent with other pointers i.e trbe_write, trbe_limit.

Snippet from $cat drivers/hwtracing/coresight/coresight-trbe.c | grep "trbe_base"
There are just two places type casting trbe_base back to (void *).

	memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
	return buf->trbe_base + offset;
	WARN_ON(buf->trbe_write < buf->trbe_base);
	set_trbe_base_pointer(buf->trbe_base);
	buf->trbe_base = (unsigned long)vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
	if (IS_ERR((void *)buf->trbe_base)) {
		return ERR_PTR(buf->trbe_base);
	buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
	buf->trbe_write = buf->trbe_base;
	vunmap((void *)buf->trbe_base);
	base = get_trbe_base_pointer();
	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
	if (buf->trbe_limit == buf->trbe_base) {
	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
	if (buf->trbe_limit == buf->trbe_base) {
	offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
	if (buf->trbe_limit == buf->trbe_base) {
	WARN_ON(buf->trbe_base != get_trbe_base_pointer());
		if (get_trbe_write_pointer() == get_trbe_base_pointer())
  
> casting?  And IS_ERR() doesn't work with vmap().

Sure, will drop IS_ERR() here.


> 
>> +		kfree(pglist);
>> +		kfree(buf);
>> +		return ERR_PTR(buf->trbe_base);
>> +	}
>> +	buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
>> +	buf->trbe_write = buf->trbe_base;
>> +	buf->snapshot = snapshot;
>> +	buf->nr_pages = nr_pages;
>> +	buf->pages = pages;
>> +	kfree(pglist);
>> +	return buf;
>> +}
>> +
>> +void arm_trbe_free_buffer(void *config)
>> +{
>> +	struct trbe_buf *buf = config;
>> +
>> +	vunmap((void *)buf->trbe_base);
>> +	kfree(buf);
>> +}
>> +
>> +static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
>> +					    struct perf_output_handle *handle,
>> +					    void *config)
>> +{
>> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
>> +	struct trbe_buf *buf = config;
>> +	unsigned long size, offset;
>> +
>> +	WARN_ON(buf->cpudata != cpudata);
>> +	WARN_ON(cpudata->cpu != smp_processor_id());
>> +	WARN_ON(cpudata->drvdata != drvdata);
>> +	if (cpudata->mode != CS_MODE_PERF)
>> +		return -EINVAL;
>> +
>> +	/*
>> +	 * If the TRBE was disabled due to lack of space in the AUX buffer or a
>> +	 * spurious fault, the driver leaves it disabled, truncating the buffer.
>> +	 * Since the etm_perf driver expects to close out the AUX buffer, the
>> +	 * driver skips it. Thus, just pass in 0 size here to indicate that the
>> +	 * buffer was truncated.
>> +	 */
>> +	if (!is_trbe_enabled())
>> +		return 0;
>> +	/*
>> +	 * perf handle structure needs to be shared with the TRBE IRQ handler for
>> +	 * capturing trace data and restarting the handle. There is a probability
>> +	 * of an undefined reference based crash when etm event is being stopped
>> +	 * while a TRBE IRQ also getting processed. This happens due the release
>> +	 * of perf handle via perf_aux_output_end() in etm_event_stop(). Stopping
>> +	 * the TRBE here will ensure that no IRQ could be generated when the perf
>> +	 * handle gets freed in etm_event_stop().
>> +	 */
>> +	trbe_drain_and_disable_local();
>> +	offset = get_trbe_write_pointer() - get_trbe_base_pointer();
>> +	size = offset - PERF_IDX2OFF(handle->head, buf);
>> +	if (buf->snapshot)
>> +		handle->head += size;
>> +	return size;
>> +}
>> +
>> +static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)
>> +{
>> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
>> +	struct perf_output_handle *handle = data;
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +
>> +	WARN_ON(cpudata->cpu != smp_processor_id());
>> +	WARN_ON(cpudata->drvdata != drvdata);
>> +	if (mode != CS_MODE_PERF)
>> +		return -EINVAL;
>> +
>> +	*this_cpu_ptr(drvdata->handle) = handle;
>> +	cpudata->buf = buf;
>> +	cpudata->mode = mode;
>> +	buf->cpudata = cpudata;
>> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
>> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
>> +	if (buf->trbe_limit == buf->trbe_base) {
>> +		trbe_stop_and_truncate_event(handle);
>> +		return 0;
>> +	}
>> +	trbe_enable_hw(buf);
>> +	return 0;
>> +}
>> +
>> +static int arm_trbe_disable(struct coresight_device *csdev)
>> +{
>> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
>> +	struct trbe_buf *buf = cpudata->buf;
>> +
>> +	WARN_ON(buf->cpudata != cpudata);
>> +	WARN_ON(cpudata->cpu != smp_processor_id());
>> +	WARN_ON(cpudata->drvdata != drvdata);
>> +	if (cpudata->mode != CS_MODE_PERF)
>> +		return -EINVAL;
>> +
>> +	trbe_drain_and_disable_local();
>> +	buf->cpudata = NULL;
>> +	cpudata->buf = NULL;
>> +	cpudata->mode = CS_MODE_DISABLED;
>> +	return 0;
>> +}
>> +
>> +static void trbe_handle_spurious(struct perf_output_handle *handle)
>> +{
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +
>> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
>> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
>> +	if (buf->trbe_limit == buf->trbe_base) {
>> +		trbe_drain_and_disable_local();
>> +		return;
>> +	}
>> +	trbe_enable_hw(buf);
>> +}
>> +
>> +static void trbe_handle_overflow(struct perf_output_handle *handle)
>> +{
>> +	struct perf_event *event = handle->event;
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +	unsigned long offset, size;
>> +	struct etm_event_data *event_data;
>> +
>> +	offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
>> +	size = offset - PERF_IDX2OFF(handle->head, buf);
>> +	if (buf->snapshot)
>> +		handle->head = offset;
>> +	perf_aux_output_end(handle, size);
>> +
>> +	event_data = perf_aux_output_begin(handle, event);
>> +	if (!event_data) {
>> +		trbe_drain_and_disable_local();
>> +		*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
>> +		return;
>> +	}
>> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
>> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
>> +	if (buf->trbe_limit == buf->trbe_base) {
>> +		trbe_stop_and_truncate_event(handle);
>> +		return;
>> +	}
>> +	*this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;
>> +	trbe_enable_hw(buf);
>> +}
>> +
>> +static bool is_perf_trbe(struct perf_output_handle *handle)
>> +{
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +	struct trbe_cpudata *cpudata = buf->cpudata;
>> +	struct trbe_drvdata *drvdata = cpudata->drvdata;
>> +	int cpu = smp_processor_id();
>> +
>> +	WARN_ON(buf->trbe_base != get_trbe_base_pointer());
>> +	WARN_ON(buf->trbe_limit != get_trbe_limit_pointer());
>> +
>> +	if (cpudata->mode != CS_MODE_PERF)
>> +		return false;
>> +
>> +	if (cpudata->cpu != cpu)
>> +		return false;
>> +
>> +	if (!cpumask_test_cpu(cpu, &drvdata->supported_cpus))
>> +		return false;
>> +
>> +	return true;
>> +}
>> +
>> +static enum trbe_fault_action trbe_get_fault_act(struct perf_output_handle *handle)
>> +{
>> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
>> +	int ec = get_trbe_ec(trbsr);
>> +	int bsc = get_trbe_bsc(trbsr);
>> +
>> +	WARN_ON(is_trbe_running(trbsr));
>> +	if (is_trbe_trg(trbsr) || is_trbe_abort(trbsr))
>> +		return TRBE_FAULT_ACT_FATAL;
>> +
>> +	if ((ec == TRBE_EC_STAGE1_ABORT) || (ec == TRBE_EC_STAGE2_ABORT))
>> +		return TRBE_FAULT_ACT_FATAL;
>> +
>> +	if (is_trbe_wrap(trbsr) && (ec == TRBE_EC_OTHERS) && (bsc == TRBE_BSC_FILLED)) {
>> +		if (get_trbe_write_pointer() == get_trbe_base_pointer())
>> +			return TRBE_FAULT_ACT_WRAP;
>> +	}
>> +	return TRBE_FAULT_ACT_SPURIOUS;
>> +}
>> +
>> +static irqreturn_t arm_trbe_irq_handler(int irq, void *dev)
>> +{
>> +	struct perf_output_handle **handle_ptr = dev;
>> +	struct perf_output_handle *handle = *handle_ptr;
>> +	enum trbe_fault_action act;
>> +
>> +	WARN_ON(!is_trbe_irq(read_sysreg_s(SYS_TRBSR_EL1)));
>> +	clr_trbe_irq();
>> +
>> +	/*
>> +	 * Ensure the trace is visible to the CPUs and
>> +	 * any external aborts have been resolved.
>> +	 */
>> +	trbe_drain_buffer();
>> +	isb();
>> +
>> +	if (!perf_get_aux(handle))
>> +		return IRQ_NONE;
>> +
>> +	if (!is_perf_trbe(handle))
>> +		return IRQ_NONE;
>> +
>> +	irq_work_run();
>> +
>> +	act = trbe_get_fault_act(handle);
>> +	switch (act) {
>> +	case TRBE_FAULT_ACT_WRAP:
>> +		trbe_handle_overflow(handle);
>> +		break;
>> +	case TRBE_FAULT_ACT_SPURIOUS:
>> +		trbe_handle_spurious(handle);
>> +		break;
>> +	case TRBE_FAULT_ACT_FATAL:
>> +		trbe_stop_and_truncate_event(handle);
>> +		break;
>> +	}
>> +	return IRQ_HANDLED;
>> +}
>> +
>> +static const struct coresight_ops_sink arm_trbe_sink_ops = {
>> +	.enable		= arm_trbe_enable,
>> +	.disable	= arm_trbe_disable,
>> +	.alloc_buffer	= arm_trbe_alloc_buffer,
>> +	.free_buffer	= arm_trbe_free_buffer,
>> +	.update_buffer	= arm_trbe_update_buffer,
>> +};
>> +
>> +static const struct coresight_ops arm_trbe_cs_ops = {
>> +	.sink_ops	= &arm_trbe_sink_ops,
>> +};
>> +
>> +static ssize_t align_show(struct device *dev, struct device_attribute *attr, char *buf)
>> +{
>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
>> +
>> +	return sprintf(buf, "%llx\n", cpudata->trbe_align);
>> +}
>> +static DEVICE_ATTR_RO(align);
>> +
>> +static ssize_t dbm_show(struct device *dev, struct device_attribute *attr, char *buf)
>> +{
>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
>> +
>> +	return sprintf(buf, "%d\n", cpudata->trbe_dbm);
>> +}
>> +static DEVICE_ATTR_RO(dbm);
> 
> What does "dbm" stand for?  Looking at the documentation for TRBIDR_EL1.F, I
> don't see what "dbm" relates to.

I made it up to refer TRBIDR_EL1.F as "Dirty (and Access Flag) Bit Management".
Could change it as "afdbm" to be more specific or if it is preferred.

> 
>> +
>> +static struct attribute *arm_trbe_attrs[] = {
>> +	&dev_attr_align.attr,
>> +	&dev_attr_dbm.attr,
>> +	NULL,
>> +};
>> +
>> +static const struct attribute_group arm_trbe_group = {
>> +	.attrs = arm_trbe_attrs,
>> +};
>> +
>> +static const struct attribute_group *arm_trbe_groups[] = {
>> +	&arm_trbe_group,
>> +	NULL,
>> +};
>> +
>> +static void arm_trbe_probe_coresight_cpu(void *info)
>> +{
>> +	struct trbe_drvdata *drvdata = info;
>> +	struct coresight_desc desc = { 0 };
>> +	int cpu = smp_processor_id();
>> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
>> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
>> +	u64 trbidr = read_sysreg_s(SYS_TRBIDR_EL1);
>> +	struct device *dev;
>> +
>> +	if (WARN_ON(!cpudata))
>> +		goto cpu_clear;
>> +
>> +	if (trbe_csdev)
>> +		return;
>> +
>> +	cpudata->cpu = smp_processor_id();
>> +	cpudata->drvdata = drvdata;
>> +	dev = &cpudata->drvdata->pdev->dev;
>> +
>> +	if (!is_trbe_available()) {
>> +		pr_err("TRBE is not implemented on cpu %d\n", cpudata->cpu);
>> +		goto cpu_clear;
>> +	}
>> +
>> +	if (!is_trbe_programmable(trbidr)) {
>> +		pr_err("TRBE is owned in higher exception level on cpu %d\n", cpudata->cpu);
>> +		goto cpu_clear;
>> +	}
>> +	desc.name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", DRVNAME, smp_processor_id());
>> +	if (IS_ERR(desc.name))
>> +		goto cpu_clear;
>> +
>> +	desc.type = CORESIGHT_DEV_TYPE_SINK;
>> +	desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
>> +	desc.ops = &arm_trbe_cs_ops;
>> +	desc.pdata = dev_get_platdata(dev);
>> +	desc.groups = arm_trbe_groups;
>> +	desc.dev = dev;
>> +	trbe_csdev = coresight_register(&desc);
>> +	if (IS_ERR(trbe_csdev))
>> +		goto cpu_clear;
>> +
>> +	dev_set_drvdata(&trbe_csdev->dev, cpudata);
>> +	cpudata->trbe_dbm = get_trbe_flag_update(trbidr);
>> +	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
>> +	if (cpudata->trbe_align > SZ_2K) {
>> +		pr_err("Unsupported alignment on cpu %d\n", cpudata->cpu);
>> +		goto cpu_clear;
>> +	}
>> +	per_cpu(csdev_sink, cpu) = trbe_csdev;
>> +	trbe_reset_local();
>> +	enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
>> +	return;
>> +cpu_clear:
>> +	cpumask_clear_cpu(cpudata->cpu, &cpudata->drvdata->supported_cpus);
>> +}
>> +
>> +static void arm_trbe_remove_coresight_cpu(void *info)
>> +{
>> +	int cpu = smp_processor_id();
>> +	struct trbe_drvdata *drvdata = info;
>> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
>> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
>> +
>> +	if (trbe_csdev) {
>> +		coresight_unregister(trbe_csdev);
>> +		cpudata->drvdata = NULL;
>> +		per_cpu(csdev_sink, cpu) = NULL;
>> +	}
>> +	disable_percpu_irq(drvdata->irq);
>> +	trbe_reset_local();
>> +}
>> +
>> +static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata)
>> +{
>> +	drvdata->cpudata = alloc_percpu(typeof(*drvdata->cpudata));
>> +	if (IS_ERR(drvdata->cpudata))
>> +		return PTR_ERR(drvdata->cpudata);
>> +
>> +	arm_trbe_probe_coresight_cpu(drvdata);
>> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_probe_coresight_cpu, drvdata, 1);
>> +	return 0;
>> +}
>> +
>> +static int arm_trbe_remove_coresight(struct trbe_drvdata *drvdata)
>> +{
>> +	arm_trbe_remove_coresight_cpu(drvdata);
>> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_remove_coresight_cpu, drvdata, 1);
>> +	free_percpu(drvdata->cpudata);
>> +	return 0;
>> +}
>> +
>> +static int arm_trbe_cpu_startup(unsigned int cpu, struct hlist_node *node)
>> +{
>> +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
>> +
>> +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
>> +		if (!per_cpu(csdev_sink, cpu)) {
>> +			arm_trbe_probe_coresight_cpu(drvdata);
>> +		} else {
>> +			trbe_reset_local();
>> +			enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
>> +		}
>> +	}
>> +	return 0;
>> +}
>> +
>> +static int arm_trbe_cpu_teardown(unsigned int cpu, struct hlist_node *node)
>> +{
>> +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
>> +
>> +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
>> +		disable_percpu_irq(drvdata->irq);
>> +		trbe_reset_local();
>> +	}
>> +	return 0;
>> +}
>> +
>> +static int arm_trbe_probe_cpuhp(struct trbe_drvdata *drvdata)
>> +{
>> +	enum cpuhp_state trbe_online;
>> +
>> +	trbe_online = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
>> +					arm_trbe_cpu_startup, arm_trbe_cpu_teardown);
> 
> Indentation

Sure, will do.

> 
>         trbe_online = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
>                                               arm_trbe_cpu_startup,
>                                               arm_trbe_cpu_teardown);
> 
>> +	if (trbe_online < 0)
>> +		return -EINVAL
> 
> Wrong error code 

Okay, will return trbe_online here.

> 
>> +
>> +	if (cpuhp_state_add_instance(trbe_online, &drvdata->hotplug_node))
>> +		return -EINVAL;
> 
> Wrong error code. Even if the callbacks aren't called it might be a good idea to
> properly cleanup the with cpuhp_remove_multi_state().

Okay, will do the following change.

--- a/drivers/hwtracing/coresight/coresight-trbe.c
+++ b/drivers/hwtracing/coresight/coresight-trbe.c
@@ -916,15 +916,18 @@ static int arm_trbe_cpu_teardown(unsigned int cpu, struct hlist_node *node)
 static int arm_trbe_probe_cpuhp(struct trbe_drvdata *drvdata)
 {
        enum cpuhp_state trbe_online;
+       int ret;
 
        trbe_online = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
                                              arm_trbe_cpu_startup, arm_trbe_cpu_teardown);
        if (trbe_online < 0)
                return trbe_online;
 
-       if (cpuhp_state_add_instance(trbe_online, &drvdata->hotplug_node))
-               return -EINVAL;
-
+       ret = cpuhp_state_add_instance(trbe_online, &drvdata->hotplug_node);
+       if (ret) {
+               cpuhp_remove_multi_state(trbe_online);
+               return ret;
+       }
        drvdata->trbe_online = trbe_online;
        return 0;
 }

> 
> More to come tomorrow.
> 
> Thanks,
> Mathieu
> 
>> +
>> +	drvdata->trbe_online = trbe_online;
>> +	return 0;
>> +}
>> +
>> +static void arm_trbe_remove_cpuhp(struct trbe_drvdata *drvdata)
>> +{
>> +	cpuhp_remove_multi_state(drvdata->trbe_online);
>> +}
>> +
>> +static int arm_trbe_probe_irq(struct platform_device *pdev,
>> +			      struct trbe_drvdata *drvdata)
>> +{
>> +	drvdata->irq = platform_get_irq(pdev, 0);
>> +	if (!drvdata->irq) {
>> +		pr_err("IRQ not found for the platform device\n");
>> +		return -ENXIO;
>> +	}
>> +
>> +	if (!irq_is_percpu(drvdata->irq)) {
>> +		pr_err("IRQ is not a PPI\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	if (irq_get_percpu_devid_partition(drvdata->irq, &drvdata->supported_cpus))
>> +		return -EINVAL;
>> +
>> +	drvdata->handle = alloc_percpu(typeof(*drvdata->handle));
>> +	if (!drvdata->handle)
>> +		return -ENOMEM;
>> +
>> +	if (request_percpu_irq(drvdata->irq, arm_trbe_irq_handler, DRVNAME, drvdata->handle)) {
>> +		free_percpu(drvdata->handle);
>> +		return -EINVAL;
>> +	}
>> +	return 0;
>> +}
>> +
>> +static void arm_trbe_remove_irq(struct trbe_drvdata *drvdata)
>> +{
>> +	free_percpu_irq(drvdata->irq, drvdata->handle);
>> +	free_percpu(drvdata->handle);
>> +}
>> +
>> +static int arm_trbe_device_probe(struct platform_device *pdev)
>> +{
>> +	struct coresight_platform_data *pdata;
>> +	struct trbe_drvdata *drvdata;
>> +	struct device *dev = &pdev->dev;
>> +	int ret;
>> +
>> +	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
>> +	if (IS_ERR(drvdata))
>> +		return -ENOMEM;
>> +
>> +	pdata = coresight_get_platform_data(dev);
>> +	if (IS_ERR(pdata)) {
>> +		kfree(drvdata);
>> +		return -ENOMEM;
>> +	}
>> +
>> +	dev_set_drvdata(dev, drvdata);
>> +	dev->platform_data = pdata;
>> +	drvdata->pdev = pdev;
>> +	ret = arm_trbe_probe_irq(pdev, drvdata);
>> +	if (ret)
>> +		goto irq_failed;
>> +
>> +	ret = arm_trbe_probe_coresight(drvdata);
>> +	if (ret)
>> +		goto probe_failed;
>> +
>> +	ret = arm_trbe_probe_cpuhp(drvdata);
>> +	if (ret)
>> +		goto cpuhp_failed;
>> +
>> +	return 0;
>> +cpuhp_failed:
>> +	arm_trbe_remove_coresight(drvdata);
>> +probe_failed:
>> +	arm_trbe_remove_irq(drvdata);
>> +irq_failed:
>> +	kfree(pdata);
>> +	kfree(drvdata);
>> +	return ret;
>> +}
>> +
>> +static int arm_trbe_device_remove(struct platform_device *pdev)
>> +{
>> +	struct coresight_platform_data *pdata = dev_get_platdata(&pdev->dev);
>> +	struct trbe_drvdata *drvdata = platform_get_drvdata(pdev);
>> +
>> +	arm_trbe_remove_coresight(drvdata);
>> +	arm_trbe_remove_cpuhp(drvdata);
> 
> Shouldn't this be called before arm_trbe_remove_coresight()?

Yes, will change the order.

- Anshuman

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-02-10 19:00   ` Mathieu Poirier
@ 2021-02-12  5:43     ` Anshuman Khandual
  2021-02-12 17:02       ` Mathieu Poirier
  0 siblings, 1 reply; 90+ messages in thread
From: Anshuman Khandual @ 2021-02-12  5:43 UTC (permalink / raw)
  To: Mathieu Poirier
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel



On 2/11/21 12:30 AM, Mathieu Poirier wrote:
> On Wed, Jan 27, 2021 at 02:25:35PM +0530, Anshuman Khandual wrote:
>> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
>> accessible via the system registers. The TRBE supports different addressing
>> modes including CPU virtual address and buffer modes including the circular
>> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
>> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
>> access to the trace buffer could be prohibited by a higher exception level
>> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
>> private interrupt (PPI) on address translation errors and when the buffer
>> is full. Overall implementation here is inspired from the Arm SPE driver.
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> Changes in V3:
>>
>> - Added new DT bindings document TRBE.yaml
>> - Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3
>> - Dropped isb() from trbe_reset_local()
>> - Dropped gap between (void *) and buf->trbe_base
>> - Changed 'int' to 'unsigned int' in is_trbe_available()
>> - Dropped unused function set_trbe_running(), set_trbe_virtual_mode(),
>>   set_trbe_enabled() and set_trbe_limit_pointer()
>> - Changed get_trbe_flag_update(), is_trbe_programmable() and
>>   get_trbe_address_align() to accept TRBIDR value
>> - Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), is_trbe_trg(),
>>   is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value
>> - Dropped snapshot mode condition in arm_trbe_alloc_buffer()
>> - Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled
>> - Compute trbe_limit before trbe_write to get the updated handle
>> - Added trbe_stop_and_truncate_event()
>> - Dropped trbe_handle_fatal()
>>
>>  Documentation/trace/coresight/coresight-trbe.rst |   39 +
>>  arch/arm64/include/asm/sysreg.h                  |    1 +
>>  drivers/hwtracing/coresight/Kconfig              |   11 +
>>  drivers/hwtracing/coresight/Makefile             |    1 +
>>  drivers/hwtracing/coresight/coresight-trbe.c     | 1023 ++++++++++++++++++++++
>>  drivers/hwtracing/coresight/coresight-trbe.h     |  160 ++++
>>  6 files changed, 1235 insertions(+)
>>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
>>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
>>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
>> +
> 
> [...]
> 
>> +static void arm_trbe_probe_coresight_cpu(void *info)
>> +{
>> +	struct trbe_drvdata *drvdata = info;
>> +	struct coresight_desc desc = { 0 };
>> +	int cpu = smp_processor_id();
>> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
>> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
>> +	u64 trbidr = read_sysreg_s(SYS_TRBIDR_EL1);
>> +	struct device *dev;
>> +
>> +	if (WARN_ON(!cpudata))
>> +		goto cpu_clear;
> 
> There is already a check for this in arm_trbe_probe_coresight(), we couldn't be
> here if there was a problem with the allocation.

Right but just to be extra cautious. Do you really want this to be dropped ?

> 
>> +
>> +	if (trbe_csdev)
>> +		return;
> 
> Now that's a reason to have a WARN_ON().  If we are probing and a sink is
> already present in this cpu's slot, something went seriously wrong and we should
> be clear about it.

Right, will add an WARN_ON().

> 
>> +
>> +	cpudata->cpu = smp_processor_id();
>> +	cpudata->drvdata = drvdata;
>> +	dev = &cpudata->drvdata->pdev->dev;
>> +
>> +	if (!is_trbe_available()) {
>> +		pr_err("TRBE is not implemented on cpu %d\n", cpudata->cpu);
>> +		goto cpu_clear;
>> +	}
>> +
>> +	if (!is_trbe_programmable(trbidr)) {
>> +		pr_err("TRBE is owned in higher exception level on cpu %d\n", cpudata->cpu);
>> +		goto cpu_clear;
>> +	}
>> +	desc.name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", DRVNAME, smp_processor_id());
> 
> We will end up with "arm_trbe0", "arm_trbe1" and so on in sysfs...  Is the
> "arm_" part absolutely needed?  I think this should be like what we do for etmv3
> and etmv4 where only "etmX" shows up in sysfs.

Okay, will drop arm_ here. IIRC this was originally trbeX where X is the cpu number
but then ended up using DRVNAME as prefix.

> 
>> +	if (IS_ERR(desc.name))
>> +		goto cpu_clear;
>> +
>> +	desc.type = CORESIGHT_DEV_TYPE_SINK;
>> +	desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
>> +	desc.ops = &arm_trbe_cs_ops;
>> +	desc.pdata = dev_get_platdata(dev);
>> +	desc.groups = arm_trbe_groups;
>> +	desc.dev = dev;
>> +	trbe_csdev = coresight_register(&desc);
>> +	if (IS_ERR(trbe_csdev))
>> +		goto cpu_clear;
>> +
>> +	dev_set_drvdata(&trbe_csdev->dev, cpudata);
>> +	cpudata->trbe_dbm = get_trbe_flag_update(trbidr);
>> +	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
>> +	if (cpudata->trbe_align > SZ_2K) {
>> +		pr_err("Unsupported alignment on cpu %d\n", cpudata->cpu);
>> +		goto cpu_clear;
> 
> Here coresight_unregister() should be called.  The other option is to call
> coresight_register() when everything else is known to be fine, which is the
> favoured approach.

Okay, will change accordingly.

> 
>> +	}
>> +	per_cpu(csdev_sink, cpu) = trbe_csdev;
>> +	trbe_reset_local();
>> +	enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
>> +	return;
>> +cpu_clear:
>> +	cpumask_clear_cpu(cpudata->cpu, &cpudata->drvdata->supported_cpus);
>> +}
>> +
>> +static void arm_trbe_remove_coresight_cpu(void *info)
>> +{
>> +	int cpu = smp_processor_id();
>> +	struct trbe_drvdata *drvdata = info;
>> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
>> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
>> +
>> +	if (trbe_csdev) {
> 
> In what scenario do you see not having a trbe_csdev and still needing to disable
> IRQs for the HW?  If there is a such a case then a few lines of comment is
> needed.
> 
>> +		coresight_unregister(trbe_csdev);
>> +		cpudata->drvdata = NULL;
>> +		per_cpu(csdev_sink, cpu) = NULL;
>> +	}
>> +	disable_percpu_irq(drvdata->irq);
>> +	trbe_reset_local();
> 
> Theoretically this code shouldn't run when the TRBE is enabled, because the CS
> core will prevent that from happening.  As sush disabling interrupts after
> coresight_unregister() has been called and setting cpudata->drvdata to NULL
> should be fine.  But from an outsider's point of view it will look very bizarre.
> Either write a comment to explain all that or call the above two before doing
> the cleanup.

Okay, will move them before the cleanup.

> 
>> +}
>> +
>> +static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata)
>> +{
>> +	drvdata->cpudata = alloc_percpu(typeof(*drvdata->cpudata));
>> +	if (IS_ERR(drvdata->cpudata))
>> +		return PTR_ERR(drvdata->cpudata);
> 
> As far as I can tell alloc_percpu() returns NULL on failure and nothing else.

Sure, will change the return code as -ENOMEM when alloc_percpu() returns NULL.

> 
>> +
>> +	arm_trbe_probe_coresight_cpu(drvdata);
>> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_probe_coresight_cpu, drvdata, 1);
> 
> The above two calls look racy to me.  The executing process could be moved to
> another CPU between the call to arm_trbe_probe_coresight_cpu() and
> smp_call_function_many(), which would prevent the initialisation of the TRBE on
> the new CPU to be done.  I suggest using a for_each_cpu() loop where
> smp_call_function_single() would be used.  That way we are guaranteed all the
> TRBEs will be initialised.

Okay, will change.

> 
>> +	return 0;
>> +}
>> +
>> +static int arm_trbe_remove_coresight(struct trbe_drvdata *drvdata)
>> +{
>> +	arm_trbe_remove_coresight_cpu(drvdata);
>> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_remove_coresight_cpu, drvdata, 1);
> 
> Same as above.

Okay, will do.

> 
> I'm out of time for today, more to come tomorrow.

Okay.

> 
> Mathieu

- Anshuman

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-02-12  3:31     ` Anshuman Khandual
@ 2021-02-12 16:57       ` Mathieu Poirier
  2021-02-15  9:26         ` Anshuman Khandual
  0 siblings, 1 reply; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-12 16:57 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel

[...]

> > 
> > 
> >> +	if (nr_pages < 2)
> >> +		return NULL;
> >> +
> >> +	buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
> >> +	if (IS_ERR(buf))
> >> +		return ERR_PTR(-ENOMEM);
> >> +
> >> +	pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
> >> +	if (IS_ERR(pglist)) {
> >> +		kfree(buf);
> >> +		return ERR_PTR(-ENOMEM);
> >> +	}
> >> +
> >> +	for (i = 0; i < nr_pages; i++)
> >> +		pglist[i] = virt_to_page(pages[i]);
> >> +
> >> +	buf->trbe_base = (unsigned long) vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
> >> +	if (IS_ERR((void *)buf->trbe_base)) {
> > 
> > Why not simply make buf->trbe_base a void * instead of having to do all this
> 
> There are many arithmetic and comparison operations involving trbe_base
> element. Hence it might be better to keep it as unsigned long, also to
> keeps it consistent with other pointers i.e trbe_write, trbe_limit.

That is a fair point.  Please add a comment to explain your design choice and
make sure the sparse checker is happy with all of it.

> 
> Snippet from $cat drivers/hwtracing/coresight/coresight-trbe.c | grep "trbe_base"
> There are just two places type casting trbe_base back to (void *).
> 
> 	memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
> 	return buf->trbe_base + offset;
> 	WARN_ON(buf->trbe_write < buf->trbe_base);
> 	set_trbe_base_pointer(buf->trbe_base);
> 	buf->trbe_base = (unsigned long)vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
> 	if (IS_ERR((void *)buf->trbe_base)) {
> 		return ERR_PTR(buf->trbe_base);
> 	buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
> 	buf->trbe_write = buf->trbe_base;
> 	vunmap((void *)buf->trbe_base);
> 	base = get_trbe_base_pointer();
> 	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> 	if (buf->trbe_limit == buf->trbe_base) {
> 	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> 	if (buf->trbe_limit == buf->trbe_base) {
> 	offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
> 	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> 	if (buf->trbe_limit == buf->trbe_base) {
> 	WARN_ON(buf->trbe_base != get_trbe_base_pointer());
> 		if (get_trbe_write_pointer() == get_trbe_base_pointer())
>   
> > casting?  And IS_ERR() doesn't work with vmap().
> 
> Sure, will drop IS_ERR() here.
> 

[...]


> > 
> >> +
> >> +static ssize_t dbm_show(struct device *dev, struct device_attribute *attr, char *buf)
> >> +{
> >> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
> >> +
> >> +	return sprintf(buf, "%d\n", cpudata->trbe_dbm);
> >> +}
> >> +static DEVICE_ATTR_RO(dbm);
> > 
> > What does "dbm" stand for?  Looking at the documentation for TRBIDR_EL1.F, I
> > don't see what "dbm" relates to.
> 
> I made it up to refer TRBIDR_EL1.F as "Dirty (and Access Flag) Bit Management".
> Could change it as "afdbm" to be more specific or if it is preferred.
> 

I don't see "afdbm" being a better solution - why not simply "flag"?


^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-02-12  5:43     ` Anshuman Khandual
@ 2021-02-12 17:02       ` Mathieu Poirier
  0 siblings, 0 replies; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-12 17:02 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel

On Fri, Feb 12, 2021 at 11:13:01AM +0530, Anshuman Khandual wrote:
> 
> 
> On 2/11/21 12:30 AM, Mathieu Poirier wrote:
> > On Wed, Jan 27, 2021 at 02:25:35PM +0530, Anshuman Khandual wrote:
> >> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
> >> accessible via the system registers. The TRBE supports different addressing
> >> modes including CPU virtual address and buffer modes including the circular
> >> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
> >> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
> >> access to the trace buffer could be prohibited by a higher exception level
> >> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
> >> private interrupt (PPI) on address translation errors and when the buffer
> >> is full. Overall implementation here is inspired from the Arm SPE driver.
> >>
> >> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> >> Cc: Mike Leach <mike.leach@linaro.org>
> >> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> >> ---
> >> Changes in V3:
> >>
> >> - Added new DT bindings document TRBE.yaml
> >> - Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3
> >> - Dropped isb() from trbe_reset_local()
> >> - Dropped gap between (void *) and buf->trbe_base
> >> - Changed 'int' to 'unsigned int' in is_trbe_available()
> >> - Dropped unused function set_trbe_running(), set_trbe_virtual_mode(),
> >>   set_trbe_enabled() and set_trbe_limit_pointer()
> >> - Changed get_trbe_flag_update(), is_trbe_programmable() and
> >>   get_trbe_address_align() to accept TRBIDR value
> >> - Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), is_trbe_trg(),
> >>   is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value
> >> - Dropped snapshot mode condition in arm_trbe_alloc_buffer()
> >> - Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled
> >> - Compute trbe_limit before trbe_write to get the updated handle
> >> - Added trbe_stop_and_truncate_event()
> >> - Dropped trbe_handle_fatal()
> >>
> >>  Documentation/trace/coresight/coresight-trbe.rst |   39 +
> >>  arch/arm64/include/asm/sysreg.h                  |    1 +
> >>  drivers/hwtracing/coresight/Kconfig              |   11 +
> >>  drivers/hwtracing/coresight/Makefile             |    1 +
> >>  drivers/hwtracing/coresight/coresight-trbe.c     | 1023 ++++++++++++++++++++++
> >>  drivers/hwtracing/coresight/coresight-trbe.h     |  160 ++++
> >>  6 files changed, 1235 insertions(+)
> >>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
> >>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
> >>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
> >> +
> > 
> > [...]
> > 
> >> +static void arm_trbe_probe_coresight_cpu(void *info)
> >> +{
> >> +	struct trbe_drvdata *drvdata = info;
> >> +	struct coresight_desc desc = { 0 };
> >> +	int cpu = smp_processor_id();
> >> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
> >> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
> >> +	u64 trbidr = read_sysreg_s(SYS_TRBIDR_EL1);
> >> +	struct device *dev;
> >> +
> >> +	if (WARN_ON(!cpudata))
> >> +		goto cpu_clear;
> > 
> > There is already a check for this in arm_trbe_probe_coresight(), we couldn't be
> > here if there was a problem with the allocation.
> 
> Right but just to be extra cautious. Do you really want this to be dropped ?

I don't think it is necessary but there is no harm in keeping it if you are keen
on it.

> 
> > 
> >> +
> >> +	if (trbe_csdev)
> >> +		return;
> > 
> > Now that's a reason to have a WARN_ON().  If we are probing and a sink is
> > already present in this cpu's slot, something went seriously wrong and we should
> > be clear about it.
> 
> Right, will add an WARN_ON().
> 
> > 
> >> +
> >> +	cpudata->cpu = smp_processor_id();
> >> +	cpudata->drvdata = drvdata;
> >> +	dev = &cpudata->drvdata->pdev->dev;
> >> +
> >> +	if (!is_trbe_available()) {
> >> +		pr_err("TRBE is not implemented on cpu %d\n", cpudata->cpu);
> >> +		goto cpu_clear;
> >> +	}
> >> +
> >> +	if (!is_trbe_programmable(trbidr)) {
> >> +		pr_err("TRBE is owned in higher exception level on cpu %d\n", cpudata->cpu);
> >> +		goto cpu_clear;
> >> +	}
> >> +	desc.name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", DRVNAME, smp_processor_id());
> > 
> > We will end up with "arm_trbe0", "arm_trbe1" and so on in sysfs...  Is the
> > "arm_" part absolutely needed?  I think this should be like what we do for etmv3
> > and etmv4 where only "etmX" shows up in sysfs.
> 
> Okay, will drop arm_ here. IIRC this was originally trbeX where X is the cpu number
> but then ended up using DRVNAME as prefix.
> 
> > 
> >> +	if (IS_ERR(desc.name))
> >> +		goto cpu_clear;
> >> +
> >> +	desc.type = CORESIGHT_DEV_TYPE_SINK;
> >> +	desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
> >> +	desc.ops = &arm_trbe_cs_ops;
> >> +	desc.pdata = dev_get_platdata(dev);
> >> +	desc.groups = arm_trbe_groups;
> >> +	desc.dev = dev;
> >> +	trbe_csdev = coresight_register(&desc);
> >> +	if (IS_ERR(trbe_csdev))
> >> +		goto cpu_clear;
> >> +
> >> +	dev_set_drvdata(&trbe_csdev->dev, cpudata);
> >> +	cpudata->trbe_dbm = get_trbe_flag_update(trbidr);
> >> +	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
> >> +	if (cpudata->trbe_align > SZ_2K) {
> >> +		pr_err("Unsupported alignment on cpu %d\n", cpudata->cpu);
> >> +		goto cpu_clear;
> > 
> > Here coresight_unregister() should be called.  The other option is to call
> > coresight_register() when everything else is known to be fine, which is the
> > favoured approach.
> 
> Okay, will change accordingly.
> 
> > 
> >> +	}
> >> +	per_cpu(csdev_sink, cpu) = trbe_csdev;
> >> +	trbe_reset_local();
> >> +	enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
> >> +	return;
> >> +cpu_clear:
> >> +	cpumask_clear_cpu(cpudata->cpu, &cpudata->drvdata->supported_cpus);
> >> +}
> >> +
> >> +static void arm_trbe_remove_coresight_cpu(void *info)
> >> +{
> >> +	int cpu = smp_processor_id();
> >> +	struct trbe_drvdata *drvdata = info;
> >> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
> >> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
> >> +
> >> +	if (trbe_csdev) {
> > 
> > In what scenario do you see not having a trbe_csdev and still needing to disable
> > IRQs for the HW?  If there is a such a case then a few lines of comment is
> > needed.
> > 
> >> +		coresight_unregister(trbe_csdev);
> >> +		cpudata->drvdata = NULL;
> >> +		per_cpu(csdev_sink, cpu) = NULL;
> >> +	}
> >> +	disable_percpu_irq(drvdata->irq);
> >> +	trbe_reset_local();
> > 
> > Theoretically this code shouldn't run when the TRBE is enabled, because the CS
> > core will prevent that from happening.  As sush disabling interrupts after
> > coresight_unregister() has been called and setting cpudata->drvdata to NULL
> > should be fine.  But from an outsider's point of view it will look very bizarre.
> > Either write a comment to explain all that or call the above two before doing
> > the cleanup.
> 
> Okay, will move them before the cleanup.
> 
> > 
> >> +}
> >> +
> >> +static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata)
> >> +{
> >> +	drvdata->cpudata = alloc_percpu(typeof(*drvdata->cpudata));
> >> +	if (IS_ERR(drvdata->cpudata))
> >> +		return PTR_ERR(drvdata->cpudata);
> > 
> > As far as I can tell alloc_percpu() returns NULL on failure and nothing else.
> 
> Sure, will change the return code as -ENOMEM when alloc_percpu() returns NULL.
> 
> > 
> >> +
> >> +	arm_trbe_probe_coresight_cpu(drvdata);
> >> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_probe_coresight_cpu, drvdata, 1);
> > 
> > The above two calls look racy to me.  The executing process could be moved to
> > another CPU between the call to arm_trbe_probe_coresight_cpu() and
> > smp_call_function_many(), which would prevent the initialisation of the TRBE on
> > the new CPU to be done.  I suggest using a for_each_cpu() loop where
> > smp_call_function_single() would be used.  That way we are guaranteed all the
> > TRBEs will be initialised.
> 
> Okay, will change.
> 
> > 
> >> +	return 0;
> >> +}
> >> +
> >> +static int arm_trbe_remove_coresight(struct trbe_drvdata *drvdata)
> >> +{
> >> +	arm_trbe_remove_coresight_cpu(drvdata);
> >> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_remove_coresight_cpu, drvdata, 1);
> > 
> > Same as above.
> 
> Okay, will do.
> 
> > 
> > I'm out of time for today, more to come tomorrow.
> 
> Okay.
> 
> > 
> > Mathieu
> 
> - Anshuman

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-01-27  8:55 ` [PATCH V3 11/14] coresight: sink: Add TRBE driver Anshuman Khandual
                     ` (3 preceding siblings ...)
  2021-02-11 19:00   ` Mathieu Poirier
@ 2021-02-12 20:26   ` Mathieu Poirier
  2021-02-15  9:46     ` Anshuman Khandual
  4 siblings, 1 reply; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-12 20:26 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel

On Wed, Jan 27, 2021 at 02:25:35PM +0530, Anshuman Khandual wrote:
> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
> accessible via the system registers. The TRBE supports different addressing
> modes including CPU virtual address and buffer modes including the circular
> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
> access to the trace buffer could be prohibited by a higher exception level
> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
> private interrupt (PPI) on address translation errors and when the buffer
> is full. Overall implementation here is inspired from the Arm SPE driver.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> Changes in V3:
> 
> - Added new DT bindings document TRBE.yaml
> - Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3
> - Dropped isb() from trbe_reset_local()
> - Dropped gap between (void *) and buf->trbe_base
> - Changed 'int' to 'unsigned int' in is_trbe_available()
> - Dropped unused function set_trbe_running(), set_trbe_virtual_mode(),
>   set_trbe_enabled() and set_trbe_limit_pointer()
> - Changed get_trbe_flag_update(), is_trbe_programmable() and
>   get_trbe_address_align() to accept TRBIDR value
> - Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), is_trbe_trg(),
>   is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value
> - Dropped snapshot mode condition in arm_trbe_alloc_buffer()
> - Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled
> - Compute trbe_limit before trbe_write to get the updated handle
> - Added trbe_stop_and_truncate_event()
> - Dropped trbe_handle_fatal()
> 
>  Documentation/trace/coresight/coresight-trbe.rst |   39 +
>  arch/arm64/include/asm/sysreg.h                  |    1 +
>  drivers/hwtracing/coresight/Kconfig              |   11 +
>  drivers/hwtracing/coresight/Makefile             |    1 +
>  drivers/hwtracing/coresight/coresight-trbe.c     | 1023 ++++++++++++++++++++++
>  drivers/hwtracing/coresight/coresight-trbe.h     |  160 ++++
>  6 files changed, 1235 insertions(+)
>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
> 
> diff --git a/Documentation/trace/coresight/coresight-trbe.rst b/Documentation/trace/coresight/coresight-trbe.rst
> new file mode 100644
> index 0000000..1cbb819
> --- /dev/null
> +++ b/Documentation/trace/coresight/coresight-trbe.rst
> @@ -0,0 +1,39 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +==============================
> +Trace Buffer Extension (TRBE).
> +==============================
> +
> +    :Author:   Anshuman Khandual <anshuman.khandual@arm.com>
> +    :Date:     November 2020
> +
> +Hardware Description
> +--------------------
> +
> +Trace Buffer Extension (TRBE) is a percpu hardware which captures in system
> +memory, CPU traces generated from a corresponding percpu tracing unit. This
> +gets plugged in as a coresight sink device because the corresponding trace
> +genarators (ETE), are plugged in as source device.
> +
> +The TRBE is not compliant to CoreSight architecture specifications, but is
> +driven via the CoreSight driver framework to support the ETE (which is
> +CoreSight compliant) integration.
> +
> +Sysfs files and directories
> +---------------------------
> +
> +The TRBE devices appear on the existing coresight bus alongside the other
> +coresight devices::
> +
> +	>$ ls /sys/bus/coresight/devices
> +	trbe0  trbe1  trbe2 trbe3
> +
> +The ``trbe<N>`` named TRBEs are associated with a CPU.::
> +
> +	>$ ls /sys/bus/coresight/devices/trbe0/
> +        align dbm
> +
> +*Key file items are:-*
> +   * ``align``: TRBE write pointer alignment
> +   * ``dbm``: TRBE updates memory with access and dirty flags
> +
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 85ae4db..9e2e9b7 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -97,6 +97,7 @@
>  #define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
>  #define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
>  #define SET_PSTATE_TCO(x)		__emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
> +#define TSB_CSYNC			__emit_inst(0xd503225f)
>  
>  #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
>  #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> index f154ae7..aa657ab 100644
> --- a/drivers/hwtracing/coresight/Kconfig
> +++ b/drivers/hwtracing/coresight/Kconfig
> @@ -164,6 +164,17 @@ config CORESIGHT_CTI
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called coresight-cti.
>  
> +config CORESIGHT_TRBE
> +	bool "Trace Buffer Extension (TRBE) driver"
> +	depends on ARM64
> +	help
> +	  This driver provides support for percpu Trace Buffer Extension (TRBE).
> +	  TRBE always needs to be used along with it's corresponding percpu ETE
> +	  component. ETE generates trace data which is then captured with TRBE.
> +	  Unlike traditional sink devices, TRBE is a CPU feature accessible via
> +	  system registers. But it's explicit dependency with trace unit (ETE)
> +	  requires it to be plugged in as a coresight sink device.
> +
>  config CORESIGHT_CTI_INTEGRATION_REGS
>  	bool "Access CTI CoreSight Integration Registers"
>  	depends on CORESIGHT_CTI
> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
> index f20e357..d608165 100644
> --- a/drivers/hwtracing/coresight/Makefile
> +++ b/drivers/hwtracing/coresight/Makefile
> @@ -21,5 +21,6 @@ obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
>  obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
>  obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
>  obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
> +obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
>  coresight-cti-y := coresight-cti-core.o	coresight-cti-platform.o \
>  		   coresight-cti-sysfs.o
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> new file mode 100644
> index 0000000..1464d8b
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -0,0 +1,1023 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * This driver enables Trace Buffer Extension (TRBE) as a per-cpu coresight
> + * sink device could then pair with an appropriate per-cpu coresight source
> + * device (ETE) thus generating required trace data. Trace can be enabled
> + * via the perf framework.
> + *
> + * Copyright (C) 2020 ARM Ltd.
> + *
> + * Author: Anshuman Khandual <anshuman.khandual@arm.com>
> + */
> +#define DRVNAME "arm_trbe"
> +
> +#define pr_fmt(fmt) DRVNAME ": " fmt
> +
> +#include "coresight-trbe.h"
> +
> +#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
> +
> +/*
> + * A padding packet that will help the user space tools
> + * in skipping relevant sections in the captured trace
> + * data which could not be decoded. TRBE doesn't support
> + * formatting the trace data, unlike the legacy CoreSight
> + * sinks and thus we use ETE trace packets to pad the
> + * sections of the buffer.
> + */
> +#define ETE_IGNORE_PACKET 		0x70
> +
> +/*
> + * Minimum amount of meaningful trace will contain:
> + * A-Sync, Trace Info, Trace On, Address, Atom.
> + * This is about 44bytes of ETE trace. To be on
> + * the safer side, we assume 64bytes is the minimum
> + * space required for a meaningful session, before
> + * we hit a "WRAP" event.
> + */
> +#define TRBE_TRACE_MIN_BUF_SIZE		64
> +
> +enum trbe_fault_action {
> +	TRBE_FAULT_ACT_WRAP,
> +	TRBE_FAULT_ACT_SPURIOUS,
> +	TRBE_FAULT_ACT_FATAL,
> +};
> +
> +struct trbe_buf {
> +	unsigned long trbe_base;
> +	unsigned long trbe_limit;
> +	unsigned long trbe_write;
> +	int nr_pages;
> +	void **pages;
> +	bool snapshot;
> +	struct trbe_cpudata *cpudata;
> +};
> +
> +struct trbe_cpudata {
> +	bool trbe_dbm;
> +	u64 trbe_align;
> +	int cpu;
> +	enum cs_mode mode;
> +	struct trbe_buf *buf;
> +	struct trbe_drvdata *drvdata;
> +};
> +
> +struct trbe_drvdata {
> +	struct trbe_cpudata __percpu *cpudata;
> +	struct perf_output_handle __percpu **handle;
> +	struct hlist_node hotplug_node;
> +	int irq;
> +	cpumask_t supported_cpus;
> +	enum cpuhp_state trbe_online;
> +	struct platform_device *pdev;
> +};
> +
> +static int trbe_alloc_node(struct perf_event *event)
> +{
> +	if (event->cpu == -1)
> +		return NUMA_NO_NODE;
> +	return cpu_to_node(event->cpu);
> +}
> +
> +static void trbe_drain_buffer(void)
> +{
> +	asm(TSB_CSYNC);
> +	dsb(nsh);
> +}
> +
> +static void trbe_drain_and_disable_local(void)
> +{
> +	trbe_drain_buffer();
> +	write_sysreg_s(0, SYS_TRBLIMITR_EL1);
> +	isb();
> +}
> +
> +static void trbe_reset_local(void)
> +{
> +	trbe_drain_and_disable_local();
> +	write_sysreg_s(0, SYS_TRBPTR_EL1);
> +	write_sysreg_s(0, SYS_TRBBASER_EL1);
> +	write_sysreg_s(0, SYS_TRBSR_EL1);
> +}
> +
> +static void trbe_stop_and_truncate_event(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +
> +	/*
> +	 * We cannot proceed with the buffer collection and we
> +	 * do not have any data for the current session. The
> +	 * etm_perf driver expects to close out the aux_buffer
> +	 * at event_stop(). So disable the TRBE here and leave
> +	 * the update_buffer() to return a 0 size.
> +	 */
> +	trbe_drain_and_disable_local();
> +	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> +	*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
> +}
> +
> +/*
> + * TRBE Buffer Management
> + *
> + * The TRBE buffer spans from the base pointer till the limit pointer. When enabled,
> + * it starts writing trace data from the write pointer onward till the limit pointer.
> + * When the write pointer reaches the address just before the limit pointer, it gets
> + * wrapped around again to the base pointer. This is called a TRBE wrap event, which
> + * generates a maintenance interrupt when operated in WRAP or FILL mode. This driver
> + * uses FILL mode, where the TRBE stops the trace collection at wrap event. The IRQ
> + * handler updates the AUX buffer and re-enables the TRBE with updated WRITE and
> + * LIMIT pointers.
> + *
> + *	Wrap around with an IRQ
> + *	------ < ------ < ------- < ----- < -----
> + *	|					|
> + *	------ > ------ > ------- > ----- > -----
> + *
> + *	+---------------+-----------------------+
> + *	|		|			|
> + *	+---------------+-----------------------+
> + *	Base Pointer	Write Pointer		Limit Pointer
> + *
> + * The base and limit pointers always needs to be PAGE_SIZE aligned. But the write
> + * pointer can be aligned to the implementation defined TRBE trace buffer alignment
> + * as captured in trbe_cpudata->trbe_align.
> + *
> + *
> + *		head		tail		wakeup
> + *	+---------------------------------------+----- ~ ~ ------
> + *	|$$$$$$$|################|$$$$$$$$$$$$$$|		|
> + *	+---------------------------------------+----- ~ ~ ------
> + *	Base Pointer	Write Pointer		Limit Pointer
> + *
> + * The perf_output_handle indices (head, tail, wakeup) are monotonically increasing
> + * values which tracks all the driver writes and user reads from the perf auxiliary
> + * buffer. Generally [head..tail] is the area where the driver can write into unless
> + * the wakeup is behind the tail. Enabled TRBE buffer span needs to be adjusted and
> + * configured depending on the perf_output_handle indices, so that the driver does
> + * not override into areas in the perf auxiliary buffer which is being or yet to be
> + * consumed from the user space. The enabled TRBE buffer area is a moving subset of
> + * the allocated perf auxiliary buffer.
> + */
> +static void trbe_pad_buf(struct perf_output_handle *handle, int len)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	u64 head = PERF_IDX2OFF(handle->head, buf);
> +
> +	memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
> +	if (!buf->snapshot)
> +		perf_aux_output_skip(handle, len);
> +}
> +
> +static unsigned long trbe_snapshot_offset(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +
> +	/*
> +	 * The ETE trace has alignment synchronization packets allowing
> +	 * the decoder to reset in case of an overflow or corruption.
> +	 * So we can use the entire buffer for the snapshot mode.
> +	 */
> +	return buf->nr_pages * PAGE_SIZE;
> +}
> +
> +/*
> + * TRBE Limit Calculation
> + *
> + * The following markers are used to illustrate various TRBE buffer situations.
> + *
> + * $$$$ - Data area, unconsumed captured trace data, not to be overridden
> + * #### - Free area, enabled, trace will be written
> + * %%%% - Free area, disabled, trace will not be written
> + * ==== - Free area, padded with ETE_IGNORE_PACKET, trace will be skipped
> + */
> +static unsigned long __trbe_normal_offset(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	struct trbe_cpudata *cpudata = buf->cpudata;
> +	const u64 bufsize = buf->nr_pages * PAGE_SIZE;
> +	u64 limit = bufsize;
> +	u64 head, tail, wakeup;
> +
> +	head = PERF_IDX2OFF(handle->head, buf);
> +
> +	/*
> +	 *		head
> +	 *	------->|
> +	 *	|
> +	 *	head	TRBE align	tail
> +	 * +----|-------|---------------|-------+
> +	 * |$$$$|=======|###############|$$$$$$$|
> +	 * +----|-------|---------------|-------+
> +	 * trbe_base				trbe_base + nr_pages
> +	 *
> +	 * Perf aux buffer output head position can be misaligned depending on
> +	 * various factors including user space reads. In case misaligned, head
> +	 * needs to be aligned before TRBE can be configured. Pad the alignment
> +	 * gap with ETE_IGNORE_PACKET bytes that will be ignored by user tools
> +	 * and skip this section thus advancing the head.
> +	 */
> +	if (!IS_ALIGNED(head, cpudata->trbe_align)) {
> +		unsigned long delta = roundup(head, cpudata->trbe_align) - head;
> +
> +		delta = min(delta, handle->size);
> +		trbe_pad_buf(handle, delta);
> +		head = PERF_IDX2OFF(handle->head, buf);
> +	}
> +
> +	/*
> +	 *	head = tail (size = 0)
> +	 * +----|-------------------------------+
> +	 * |$$$$|$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$	|
> +	 * +----|-------------------------------+
> +	 * trbe_base				trbe_base + nr_pages
> +	 *
> +	 * Perf aux buffer does not have any space for the driver to write into.
> +	 * Just communicate trace truncation event to the user space by marking
> +	 * it with PERF_AUX_FLAG_TRUNCATED.
> +	 */
> +	if (!handle->size) {
> +		perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> +		return 0;
> +	}
> +
> +	/* Compute the tail and wakeup indices now that we've aligned head */
> +	tail = PERF_IDX2OFF(handle->head + handle->size, buf);
> +	wakeup = PERF_IDX2OFF(handle->wakeup, buf);
> +
> +	/*
> +	 * Lets calculate the buffer area which TRBE could write into. There
> +	 * are three possible scenarios here. Limit needs to be aligned with
> +	 * PAGE_SIZE per the TRBE requirement. Always avoid clobbering the
> +	 * unconsumed data.
> +	 *
> +	 * 1) head < tail
> +	 *
> +	 *	head			tail
> +	 * +----|-----------------------|-------+
> +	 * |$$$$|#######################|$$$$$$$|
> +	 * +----|-----------------------|-------+
> +	 * trbe_base			limit	trbe_base + nr_pages
> +	 *
> +	 * TRBE could write into [head..tail] area. Unless the tail is right at
> +	 * the end of the buffer, neither an wrap around nor an IRQ is expected
> +	 * while being enabled.
> +	 *
> +	 * 2) head == tail
> +	 *
> +	 *	head = tail (size > 0)
> +	 * +----|-------------------------------+
> +	 * |%%%%|###############################|
> +	 * +----|-------------------------------+
> +	 * trbe_base				limit = trbe_base + nr_pages
> +	 *
> +	 * TRBE should just write into [head..base + nr_pages] area even though
> +	 * the entire buffer is empty. Reason being, when the trace reaches the
> +	 * end of the buffer, it will just wrap around with an IRQ giving an
> +	 * opportunity to reconfigure the buffer.
> +	 *
> +	 * 3) tail < head
> +	 *
> +	 *	tail			head
> +	 * +----|-----------------------|-------+
> +	 * |%%%%|$$$$$$$$$$$$$$$$$$$$$$$|#######|
> +	 * +----|-----------------------|-------+
> +	 * trbe_base				limit = trbe_base + nr_pages
> +	 *
> +	 * TRBE should just write into [head..base + nr_pages] area even though
> +	 * the [trbe_base..tail] is also empty. Reason being, when the trace
> +	 * reaches the end of the buffer, it will just wrap around with an IRQ
> +	 * giving an opportunity to reconfigure the buffer.
> +	 */
> +	if (head < tail)
> +		limit = round_down(tail, PAGE_SIZE);
> +
> +	/*
> +	 * Wakeup may be arbitrarily far into the future. If it's not in the
> +	 * current generation, either we'll wrap before hitting it, or it's
> +	 * in the past and has been handled already.
> +	 *
> +	 * If there's a wakeup before we wrap, arrange to be woken up by the
> +	 * page boundary following it. Keep the tail boundary if that's lower.
> +	 *
> +	 *	head		wakeup	tail
> +	 * +----|---------------|-------|-------+
> +	 * |$$$$|###############|%%%%%%%|$$$$$$$|
> +	 * +----|---------------|-------|-------+
> +	 * trbe_base		limit		trbe_base + nr_pages
> +	 */
> +	if (handle->wakeup < (handle->head + handle->size) && head <= wakeup)
> +		limit = min(limit, round_up(wakeup, PAGE_SIZE));
> +
> +	/*
> +	 * There are two situation when this can happen i.e limit is before
> +	 * the head and hence TRBE cannot be configured.
> +	 *
> +	 * 1) head < tail (aligned down with PAGE_SIZE) and also they are both
> +	 * within the same PAGE size range.
> +	 *
> +	 *			PAGE_SIZE
> +	 *		|----------------------|
> +	 *
> +	 *		limit	head	tail
> +	 * +------------|------|--------|-------+
> +	 * |$$$$$$$$$$$$$$$$$$$|========|$$$$$$$|
> +	 * +------------|------|--------|-------+
> +	 * trbe_base				trbe_base + nr_pages
> +	 *
> +	 * 2) head < wakeup (aligned up with PAGE_SIZE) < tail and also both
> +	 * head and wakeup are within same PAGE size range.
> +	 *
> +	 *		PAGE_SIZE
> +	 *	|----------------------|
> +	 *
> +	 *	limit	head	wakeup  tail
> +	 * +----|------|-------|--------|-------+
> +	 * |$$$$$$$$$$$|=======|========|$$$$$$$|
> +	 * +----|------|-------|--------|-------+
> +	 * trbe_base				trbe_base + nr_pages
> +	 */
> +	if (limit > head)
> +		return limit;
> +
> +	trbe_pad_buf(handle, handle->size);
> +	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> +	return 0;
> +}
> +
> +static unsigned long trbe_normal_offset(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = perf_get_aux(handle);
> +	u64 limit = __trbe_normal_offset(handle);
> +	u64 head = PERF_IDX2OFF(handle->head, buf);
> +
> +	/*
> +	 * If the head is too close to the limit and we don't
> +	 * have space for a meaningful run, we rather pad it
> +	 * and start fresh.
> +	 */
> +	if (limit && (limit - head < TRBE_TRACE_MIN_BUF_SIZE)) {
> +		trbe_pad_buf(handle, limit - head);
> +		limit = __trbe_normal_offset(handle);
> +	}
> +	return limit;
> +}
> +
> +static unsigned long compute_trbe_buffer_limit(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	unsigned long offset;
> +
> +	if (buf->snapshot)
> +		offset = trbe_snapshot_offset(handle);
> +	else
> +		offset = trbe_normal_offset(handle);
> +	return buf->trbe_base + offset;
> +}

I won't review the trace buffer management functions in this revision, I will
leave that for the next version.

> +
> +static void clr_trbe_status(void)
> +{
> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
> +
> +	WARN_ON(is_trbe_enabled());
> +	trbsr &= ~TRBSR_IRQ;
> +	trbsr &= ~TRBSR_TRG;
> +	trbsr &= ~TRBSR_WRAP;
> +	trbsr &= ~(TRBSR_EC_MASK << TRBSR_EC_SHIFT);
> +	trbsr &= ~(TRBSR_BSC_MASK << TRBSR_BSC_SHIFT);
> +	trbsr &= ~TRBSR_STOP;
> +	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
> +}

I haven't read the TRBE progammer's manual but looking a the documentation the above
looks good.

> +
> +static void set_trbe_limit_pointer_enabled(unsigned long addr)
> +{
> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> +
> +	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> +
> +	trblimitr &= ~TRBLIMITR_NVM;
> +	trblimitr &= ~(TRBLIMITR_FILL_MODE_MASK << TRBLIMITR_FILL_MODE_SHIFT);
> +	trblimitr &= ~(TRBLIMITR_TRIG_MODE_MASK << TRBLIMITR_TRIG_MODE_SHIFT);
> +	trblimitr &= ~(TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT);
> +
> +	/*
> +	 * Fill trace buffer mode is used here while configuring the
> +	 * TRBE for trace capture. In this particular mode, the trace
> +	 * collection is stopped and a maintenance interrupt is raised
> +	 * when the current write pointer wraps. This pause in trace
> +	 * collection gives the software an opportunity to capture the
> +	 * trace data in the interrupt handler, before reconfiguring
> +	 * the TRBE.
> +	 */
> +	trblimitr |= (TRBE_FILL_MODE_FILL & TRBLIMITR_FILL_MODE_MASK) << TRBLIMITR_FILL_MODE_SHIFT;
> +
> +	/*
> +	 * Trigger mode is not used here while configuring the TRBE for
> +	 * the trace capture. Hence just keep this in the ignore mode.
> +	 */
> +	trblimitr |= (TRBE_TRIG_MODE_IGNORE & TRBLIMITR_TRIG_MODE_MASK) << TRBLIMITR_TRIG_MODE_SHIFT;
> +	trblimitr |= (addr & PAGE_MASK);
> +
> +	trblimitr |= TRBLIMITR_ENABLE;
> +	write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
> +}

Same here

> +
> +static void trbe_enable_hw(struct trbe_buf *buf)
> +{
> +	WARN_ON(buf->trbe_write < buf->trbe_base);
> +	WARN_ON(buf->trbe_write >= buf->trbe_limit);
> +	set_trbe_disabled();
> +	isb();
> +	clr_trbe_status();
> +	set_trbe_base_pointer(buf->trbe_base);
> +	set_trbe_write_pointer(buf->trbe_write);
> +
> +	/*
> +	 * Synchronize all the register updates
> +	 * till now before enabling the TRBE.
> +	 */
> +	isb();
> +	set_trbe_limit_pointer_enabled(buf->trbe_limit);
> +
> +	/* Synchronize the TRBE enable event */
> +	isb();
> +}

Ok

> +
> +static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
> +				   struct perf_event *event, void **pages,
> +				   int nr_pages, bool snapshot)
> +{
> +	struct trbe_buf *buf;
> +	struct page **pglist;
> +	int i;
> +
> +	/*
> +	 * TRBE LIMIT and TRBE WRITE pointers must be page aligned. But with
> +	 * just a single page, there is not much room left while writing into
> +	 * a partially filled TRBE buffer. Hence restrict the minimum buffer
> +	 * size as two pages.
> +	 */
> +	if (nr_pages < 2)
> +		return NULL;
> +
> +	buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
> +	if (IS_ERR(buf))
> +		return ERR_PTR(-ENOMEM);

You know what do to.

> +
> +	pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
> +	if (IS_ERR(pglist)) {
> +		kfree(buf);
> +		return ERR_PTR(-ENOMEM);
> +	}

Here too.

> +
> +	for (i = 0; i < nr_pages; i++)
> +		pglist[i] = virt_to_page(pages[i]);
> +
> +	buf->trbe_base = (unsigned long) vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
> +	if (IS_ERR((void *)buf->trbe_base)) {
> +		kfree(pglist);
> +		kfree(buf);
> +		return ERR_PTR(buf->trbe_base);
> +	}

Here too.

> +	buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
> +	buf->trbe_write = buf->trbe_base;
> +	buf->snapshot = snapshot;
> +	buf->nr_pages = nr_pages;
> +	buf->pages = pages;
> +	kfree(pglist);
> +	return buf;
> +}
> +
> +void arm_trbe_free_buffer(void *config)
> +{
> +	struct trbe_buf *buf = config;
> +
> +	vunmap((void *)buf->trbe_base);
> +	kfree(buf);
> +}

Ok

> +
> +static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
> +					    struct perf_output_handle *handle,
> +					    void *config)
> +{
> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> +	struct trbe_buf *buf = config;
> +	unsigned long size, offset;
> +
> +	WARN_ON(buf->cpudata != cpudata);
> +	WARN_ON(cpudata->cpu != smp_processor_id());
> +	WARN_ON(cpudata->drvdata != drvdata);
> +	if (cpudata->mode != CS_MODE_PERF)
> +		return -EINVAL;
> +
> +	/*
> +	 * If the TRBE was disabled due to lack of space in the AUX buffer or a
> +	 * spurious fault, the driver leaves it disabled, truncating the buffer.
> +	 * Since the etm_perf driver expects to close out the AUX buffer, the
> +	 * driver skips it. Thus, just pass in 0 size here to indicate that the
> +	 * buffer was truncated.
> +	 */
> +	if (!is_trbe_enabled())
> +		return 0;
> +	/*
> +	 * perf handle structure needs to be shared with the TRBE IRQ handler for
> +	 * capturing trace data and restarting the handle. There is a probability
> +	 * of an undefined reference based crash when etm event is being stopped
> +	 * while a TRBE IRQ also getting processed. This happens due the release
> +	 * of perf handle via perf_aux_output_end() in etm_event_stop(). Stopping
> +	 * the TRBE here will ensure that no IRQ could be generated when the perf
> +	 * handle gets freed in etm_event_stop().
> +	 */
> +	trbe_drain_and_disable_local();
> +	offset = get_trbe_write_pointer() - get_trbe_base_pointer();
> +	size = offset - PERF_IDX2OFF(handle->head, buf);
> +	if (buf->snapshot)
> +		handle->head += size;
> +	return size;
> +}

Ok - I really appreciate the comments.

> +
> +static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)
> +{
> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> +	struct perf_output_handle *handle = data;
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +
> +	WARN_ON(cpudata->cpu != smp_processor_id());
> +	WARN_ON(cpudata->drvdata != drvdata);
> +	if (mode != CS_MODE_PERF)
> +		return -EINVAL;
> +
> +	*this_cpu_ptr(drvdata->handle) = handle;
> +	cpudata->buf = buf;
> +	cpudata->mode = mode;
> +	buf->cpudata = cpudata;
> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> +	if (buf->trbe_limit == buf->trbe_base) {
> +		trbe_stop_and_truncate_event(handle);
> +		return 0;
> +	}
> +	trbe_enable_hw(buf);
> +	return 0;
> +}

Ok

> +
> +static int arm_trbe_disable(struct coresight_device *csdev)
> +{
> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> +	struct trbe_buf *buf = cpudata->buf;
> +
> +	WARN_ON(buf->cpudata != cpudata);
> +	WARN_ON(cpudata->cpu != smp_processor_id());
> +	WARN_ON(cpudata->drvdata != drvdata);
> +	if (cpudata->mode != CS_MODE_PERF)
> +		return -EINVAL;
> +
> +	trbe_drain_and_disable_local();
> +	buf->cpudata = NULL;
> +	cpudata->buf = NULL;
> +	cpudata->mode = CS_MODE_DISABLED;
> +	return 0;
> +}

Ok

> +
> +static void trbe_handle_spurious(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +
> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> +	if (buf->trbe_limit == buf->trbe_base) {
> +		trbe_drain_and_disable_local();
> +		return;
> +	}
> +	trbe_enable_hw(buf);
> +}
> +
> +static void trbe_handle_overflow(struct perf_output_handle *handle)
> +{
> +	struct perf_event *event = handle->event;
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	unsigned long offset, size;
> +	struct etm_event_data *event_data;
> +
> +	offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
> +	size = offset - PERF_IDX2OFF(handle->head, buf);
> +	if (buf->snapshot)
> +		handle->head = offset;
> +	perf_aux_output_end(handle, size);
> +
> +	event_data = perf_aux_output_begin(handle, event);
> +	if (!event_data) {
> +		trbe_drain_and_disable_local();
> +		*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
> +		return;
> +	}
> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> +	if (buf->trbe_limit == buf->trbe_base) {
> +		trbe_stop_and_truncate_event(handle);
> +		return;
> +	}
> +	*this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;
> +	trbe_enable_hw(buf);
> +}
> +
> +static bool is_perf_trbe(struct perf_output_handle *handle)
> +{
> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
> +	struct trbe_cpudata *cpudata = buf->cpudata;
> +	struct trbe_drvdata *drvdata = cpudata->drvdata;
> +	int cpu = smp_processor_id();
> +
> +	WARN_ON(buf->trbe_base != get_trbe_base_pointer());
> +	WARN_ON(buf->trbe_limit != get_trbe_limit_pointer());
> +
> +	if (cpudata->mode != CS_MODE_PERF)
> +		return false;
> +
> +	if (cpudata->cpu != cpu)
> +		return false;
> +
> +	if (!cpumask_test_cpu(cpu, &drvdata->supported_cpus))
> +		return false;
> +
> +	return true;
> +}
> +
> +static enum trbe_fault_action trbe_get_fault_act(struct perf_output_handle *handle)

@handle isn't used for anything.

> +{
> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
> +	int ec = get_trbe_ec(trbsr);
> +	int bsc = get_trbe_bsc(trbsr);
> +
> +	WARN_ON(is_trbe_running(trbsr));
> +	if (is_trbe_trg(trbsr) || is_trbe_abort(trbsr))
> +		return TRBE_FAULT_ACT_FATAL;
> +
> +	if ((ec == TRBE_EC_STAGE1_ABORT) || (ec == TRBE_EC_STAGE2_ABORT))
> +		return TRBE_FAULT_ACT_FATAL;
> +
> +	if (is_trbe_wrap(trbsr) && (ec == TRBE_EC_OTHERS) && (bsc == TRBE_BSC_FILLED)) {
> +		if (get_trbe_write_pointer() == get_trbe_base_pointer())
> +			return TRBE_FAULT_ACT_WRAP;
> +	}
> +	return TRBE_FAULT_ACT_SPURIOUS;
> +}
> +
> +static irqreturn_t arm_trbe_irq_handler(int irq, void *dev)
> +{
> +	struct perf_output_handle **handle_ptr = dev;
> +	struct perf_output_handle *handle = *handle_ptr;
> +	enum trbe_fault_action act;
> +
> +	WARN_ON(!is_trbe_irq(read_sysreg_s(SYS_TRBSR_EL1)));
> +	clr_trbe_irq();
> +
> +	/*
> +	 * Ensure the trace is visible to the CPUs and
> +	 * any external aborts have been resolved.
> +	 */
> +	trbe_drain_buffer();
> +	isb();
> +
> +	if (!perf_get_aux(handle))
> +		return IRQ_NONE;
> +
> +	if (!is_perf_trbe(handle))
> +		return IRQ_NONE;
> +
> +	irq_work_run();

I trust Will that this is the right thing to do.

I will stop here for this revision.  I will dive more in the mechanic of the
TRBE on the next revision.

Thanks,
Mathieu

> +
> +	act = trbe_get_fault_act(handle);
> +	switch (act) {
> +	case TRBE_FAULT_ACT_WRAP:
> +		trbe_handle_overflow(handle);
> +		break;
> +	case TRBE_FAULT_ACT_SPURIOUS:
> +		trbe_handle_spurious(handle);
> +		break;
> +	case TRBE_FAULT_ACT_FATAL:
> +		trbe_stop_and_truncate_event(handle);
> +		break;
> +	}
> +	return IRQ_HANDLED;
> +}
> +
> +static const struct coresight_ops_sink arm_trbe_sink_ops = {
> +	.enable		= arm_trbe_enable,
> +	.disable	= arm_trbe_disable,
> +	.alloc_buffer	= arm_trbe_alloc_buffer,
> +	.free_buffer	= arm_trbe_free_buffer,
> +	.update_buffer	= arm_trbe_update_buffer,
> +};
> +
> +static const struct coresight_ops arm_trbe_cs_ops = {
> +	.sink_ops	= &arm_trbe_sink_ops,
> +};
> +
> +static ssize_t align_show(struct device *dev, struct device_attribute *attr, char *buf)
> +{
> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
> +
> +	return sprintf(buf, "%llx\n", cpudata->trbe_align);
> +}
> +static DEVICE_ATTR_RO(align);
> +
> +static ssize_t dbm_show(struct device *dev, struct device_attribute *attr, char *buf)
> +{
> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
> +
> +	return sprintf(buf, "%d\n", cpudata->trbe_dbm);
> +}
> +static DEVICE_ATTR_RO(dbm);
> +
> +static struct attribute *arm_trbe_attrs[] = {
> +	&dev_attr_align.attr,
> +	&dev_attr_dbm.attr,
> +	NULL,
> +};
> +
> +static const struct attribute_group arm_trbe_group = {
> +	.attrs = arm_trbe_attrs,
> +};
> +
> +static const struct attribute_group *arm_trbe_groups[] = {
> +	&arm_trbe_group,
> +	NULL,
> +};
> +
> +static void arm_trbe_probe_coresight_cpu(void *info)
> +{
> +	struct trbe_drvdata *drvdata = info;
> +	struct coresight_desc desc = { 0 };
> +	int cpu = smp_processor_id();
> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
> +	u64 trbidr = read_sysreg_s(SYS_TRBIDR_EL1);
> +	struct device *dev;
> +
> +	if (WARN_ON(!cpudata))
> +		goto cpu_clear;
> +
> +	if (trbe_csdev)
> +		return;
> +
> +	cpudata->cpu = smp_processor_id();
> +	cpudata->drvdata = drvdata;
> +	dev = &cpudata->drvdata->pdev->dev;
> +
> +	if (!is_trbe_available()) {
> +		pr_err("TRBE is not implemented on cpu %d\n", cpudata->cpu);
> +		goto cpu_clear;
> +	}
> +
> +	if (!is_trbe_programmable(trbidr)) {
> +		pr_err("TRBE is owned in higher exception level on cpu %d\n", cpudata->cpu);
> +		goto cpu_clear;
> +	}
> +	desc.name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", DRVNAME, smp_processor_id());
> +	if (IS_ERR(desc.name))
> +		goto cpu_clear;
> +
> +	desc.type = CORESIGHT_DEV_TYPE_SINK;
> +	desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
> +	desc.ops = &arm_trbe_cs_ops;
> +	desc.pdata = dev_get_platdata(dev);
> +	desc.groups = arm_trbe_groups;
> +	desc.dev = dev;
> +	trbe_csdev = coresight_register(&desc);
> +	if (IS_ERR(trbe_csdev))
> +		goto cpu_clear;
> +
> +	dev_set_drvdata(&trbe_csdev->dev, cpudata);
> +	cpudata->trbe_dbm = get_trbe_flag_update(trbidr);
> +	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
> +	if (cpudata->trbe_align > SZ_2K) {
> +		pr_err("Unsupported alignment on cpu %d\n", cpudata->cpu);
> +		goto cpu_clear;
> +	}
> +	per_cpu(csdev_sink, cpu) = trbe_csdev;
> +	trbe_reset_local();
> +	enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
> +	return;
> +cpu_clear:
> +	cpumask_clear_cpu(cpudata->cpu, &cpudata->drvdata->supported_cpus);
> +}
> +
> +static void arm_trbe_remove_coresight_cpu(void *info)
> +{
> +	int cpu = smp_processor_id();
> +	struct trbe_drvdata *drvdata = info;
> +	struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu);
> +	struct coresight_device *trbe_csdev = per_cpu(csdev_sink, cpu);
> +
> +	if (trbe_csdev) {
> +		coresight_unregister(trbe_csdev);
> +		cpudata->drvdata = NULL;
> +		per_cpu(csdev_sink, cpu) = NULL;
> +	}
> +	disable_percpu_irq(drvdata->irq);
> +	trbe_reset_local();
> +}
> +
> +static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata)
> +{
> +	drvdata->cpudata = alloc_percpu(typeof(*drvdata->cpudata));
> +	if (IS_ERR(drvdata->cpudata))
> +		return PTR_ERR(drvdata->cpudata);
> +
> +	arm_trbe_probe_coresight_cpu(drvdata);
> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_probe_coresight_cpu, drvdata, 1);
> +	return 0;
> +}
> +
> +static int arm_trbe_remove_coresight(struct trbe_drvdata *drvdata)
> +{
> +	arm_trbe_remove_coresight_cpu(drvdata);
> +	smp_call_function_many(&drvdata->supported_cpus, arm_trbe_remove_coresight_cpu, drvdata, 1);
> +	free_percpu(drvdata->cpudata);
> +	return 0;
> +}
> +
> +static int arm_trbe_cpu_startup(unsigned int cpu, struct hlist_node *node)
> +{
> +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
> +
> +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
> +		if (!per_cpu(csdev_sink, cpu)) {
> +			arm_trbe_probe_coresight_cpu(drvdata);
> +		} else {
> +			trbe_reset_local();
> +			enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE);
> +		}
> +	}
> +	return 0;
> +}
> +
> +static int arm_trbe_cpu_teardown(unsigned int cpu, struct hlist_node *node)
> +{
> +	struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node);
> +
> +	if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) {
> +		disable_percpu_irq(drvdata->irq);
> +		trbe_reset_local();
> +	}
> +	return 0;
> +}
> +
> +static int arm_trbe_probe_cpuhp(struct trbe_drvdata *drvdata)
> +{
> +	enum cpuhp_state trbe_online;
> +
> +	trbe_online = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
> +					arm_trbe_cpu_startup, arm_trbe_cpu_teardown);
> +	if (trbe_online < 0)
> +		return -EINVAL;
> +
> +	if (cpuhp_state_add_instance(trbe_online, &drvdata->hotplug_node))
> +		return -EINVAL;
> +
> +	drvdata->trbe_online = trbe_online;
> +	return 0;
> +}
> +
> +static void arm_trbe_remove_cpuhp(struct trbe_drvdata *drvdata)
> +{
> +	cpuhp_remove_multi_state(drvdata->trbe_online);
> +}
> +
> +static int arm_trbe_probe_irq(struct platform_device *pdev,
> +			      struct trbe_drvdata *drvdata)
> +{
> +	drvdata->irq = platform_get_irq(pdev, 0);
> +	if (!drvdata->irq) {
> +		pr_err("IRQ not found for the platform device\n");
> +		return -ENXIO;
> +	}
> +
> +	if (!irq_is_percpu(drvdata->irq)) {
> +		pr_err("IRQ is not a PPI\n");
> +		return -EINVAL;
> +	}
> +
> +	if (irq_get_percpu_devid_partition(drvdata->irq, &drvdata->supported_cpus))
> +		return -EINVAL;
> +
> +	drvdata->handle = alloc_percpu(typeof(*drvdata->handle));
> +	if (!drvdata->handle)
> +		return -ENOMEM;
> +
> +	if (request_percpu_irq(drvdata->irq, arm_trbe_irq_handler, DRVNAME, drvdata->handle)) {
> +		free_percpu(drvdata->handle);
> +		return -EINVAL;
> +	}
> +	return 0;
> +}
> +
> +static void arm_trbe_remove_irq(struct trbe_drvdata *drvdata)
> +{
> +	free_percpu_irq(drvdata->irq, drvdata->handle);
> +	free_percpu(drvdata->handle);
> +}
> +
> +static int arm_trbe_device_probe(struct platform_device *pdev)
> +{
> +	struct coresight_platform_data *pdata;
> +	struct trbe_drvdata *drvdata;
> +	struct device *dev = &pdev->dev;
> +	int ret;
> +
> +	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> +	if (IS_ERR(drvdata))
> +		return -ENOMEM;
> +
> +	pdata = coresight_get_platform_data(dev);
> +	if (IS_ERR(pdata)) {
> +		kfree(drvdata);
> +		return -ENOMEM;
> +	}
> +
> +	dev_set_drvdata(dev, drvdata);
> +	dev->platform_data = pdata;
> +	drvdata->pdev = pdev;
> +	ret = arm_trbe_probe_irq(pdev, drvdata);
> +	if (ret)
> +		goto irq_failed;
> +
> +	ret = arm_trbe_probe_coresight(drvdata);
> +	if (ret)
> +		goto probe_failed;
> +
> +	ret = arm_trbe_probe_cpuhp(drvdata);
> +	if (ret)
> +		goto cpuhp_failed;
> +
> +	return 0;
> +cpuhp_failed:
> +	arm_trbe_remove_coresight(drvdata);
> +probe_failed:
> +	arm_trbe_remove_irq(drvdata);
> +irq_failed:
> +	kfree(pdata);
> +	kfree(drvdata);
> +	return ret;
> +}
> +
> +static int arm_trbe_device_remove(struct platform_device *pdev)
> +{
> +	struct coresight_platform_data *pdata = dev_get_platdata(&pdev->dev);
> +	struct trbe_drvdata *drvdata = platform_get_drvdata(pdev);
> +
> +	arm_trbe_remove_coresight(drvdata);
> +	arm_trbe_remove_cpuhp(drvdata);
> +	arm_trbe_remove_irq(drvdata);
> +	kfree(pdata);
> +	kfree(drvdata);
> +	return 0;
> +}
> +
> +static const struct of_device_id arm_trbe_of_match[] = {
> +	{ .compatible = "arm,trace-buffer-extension"},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, arm_trbe_of_match);
> +
> +static struct platform_driver arm_trbe_driver = {
> +	.driver	= {
> +		.name = DRVNAME,
> +		.of_match_table = of_match_ptr(arm_trbe_of_match),
> +		.suppress_bind_attrs = true,
> +	},
> +	.probe	= arm_trbe_device_probe,
> +	.remove	= arm_trbe_device_remove,
> +};
> +
> +static int __init arm_trbe_init(void)
> +{
> +	int ret;
> +
> +	if (arm64_kernel_unmapped_at_el0()) {
> +		pr_err("TRBE wouldn't work if kernel gets unmapped at EL0\n");
> +		return -EOPNOTSUPP;
> +	}
> +
> +	ret = platform_driver_register(&arm_trbe_driver);
> +	if (!ret)
> +		return 0;
> +
> +	pr_err("Error registering %s platform driver\n", DRVNAME);
> +	return ret;
> +}
> +
> +static void __exit arm_trbe_exit(void)
> +{
> +	platform_driver_unregister(&arm_trbe_driver);
> +}
> +module_init(arm_trbe_init);
> +module_exit(arm_trbe_exit);
> +
> +MODULE_AUTHOR("Anshuman Khandual <anshuman.khandual@arm.com>");
> +MODULE_DESCRIPTION("Arm Trace Buffer Extension (TRBE) driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h
> new file mode 100644
> index 0000000..43308bc
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-trbe.h
> @@ -0,0 +1,160 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This contains all required hardware related helper functions for
> + * Trace Buffer Extension (TRBE) driver in the coresight framework.
> + *
> + * Copyright (C) 2020 ARM Ltd.
> + *
> + * Author: Anshuman Khandual <anshuman.khandual@arm.com>
> + */
> +#include <linux/coresight.h>
> +#include <linux/device.h>
> +#include <linux/irq.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/smp.h>
> +
> +#include "coresight-etm-perf.h"
> +
> +DECLARE_PER_CPU(struct coresight_device *, csdev_sink);
> +
> +static inline bool is_trbe_available(void)
> +{
> +	u64 aa64dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
> +	unsigned int trbe = cpuid_feature_extract_unsigned_field(aa64dfr0, ID_AA64DFR0_TRBE_SHIFT);
> +
> +	return trbe >= 0b0001;
> +}
> +
> +static inline bool is_trbe_enabled(void)
> +{
> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> +
> +	return trblimitr & TRBLIMITR_ENABLE;
> +}
> +
> +#define TRBE_EC_OTHERS		0
> +#define TRBE_EC_STAGE1_ABORT	36
> +#define TRBE_EC_STAGE2_ABORT	37
> +
> +static inline int get_trbe_ec(u64 trbsr)
> +{
> +	return (trbsr >> TRBSR_EC_SHIFT) & TRBSR_EC_MASK;
> +}
> +
> +#define TRBE_BSC_NOT_STOPPED	0
> +#define	TRBE_BSC_FILLED		1
> +#define TRBE_BSC_TRIGGERED	2
> +
> +static inline int get_trbe_bsc(u64 trbsr)
> +{
> +	return (trbsr >> TRBSR_BSC_SHIFT) & TRBSR_BSC_MASK;
> +}
> +
> +static inline void clr_trbe_irq(void)
> +{
> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
> +
> +	trbsr &= ~TRBSR_IRQ;
> +	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
> +}
> +
> +static inline bool is_trbe_irq(u64 trbsr)
> +{
> +	return trbsr & TRBSR_IRQ;
> +}
> +
> +static inline bool is_trbe_trg(u64 trbsr)
> +{
> +	return trbsr & TRBSR_TRG;
> +}
> +
> +static inline bool is_trbe_wrap(u64 trbsr)
> +{
> +	return trbsr & TRBSR_WRAP;
> +}
> +
> +static inline bool is_trbe_abort(u64 trbsr)
> +{
> +	return trbsr & TRBSR_ABORT;
> +}
> +
> +static inline bool is_trbe_running(u64 trbsr)
> +{
> +	return !(trbsr & TRBSR_STOP);
> +}
> +
> +#define TRBE_TRIG_MODE_STOP		0
> +#define TRBE_TRIG_MODE_IRQ		1
> +#define TRBE_TRIG_MODE_IGNORE		3
> +
> +#define TRBE_FILL_MODE_FILL		0
> +#define TRBE_FILL_MODE_WRAP		1
> +#define TRBE_FILL_MODE_CIRCULAR_BUFFER	3
> +
> +static inline void set_trbe_disabled(void)
> +{
> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> +
> +	trblimitr &= ~TRBLIMITR_ENABLE;
> +	write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
> +}
> +
> +static inline bool get_trbe_flag_update(u64 trbidr)
> +{
> +	return trbidr & TRBIDR_FLAG;
> +}
> +
> +static inline bool is_trbe_programmable(u64 trbidr)
> +{
> +	return !(trbidr & TRBIDR_PROG);
> +}
> +
> +static inline int get_trbe_address_align(u64 trbidr)
> +{
> +	return (trbidr >> TRBIDR_ALIGN_SHIFT) & TRBIDR_ALIGN_MASK;
> +}
> +
> +static inline unsigned long get_trbe_write_pointer(void)
> +{
> +	u64 trbptr = read_sysreg_s(SYS_TRBPTR_EL1);
> +	unsigned long addr = (trbptr >> TRBPTR_PTR_SHIFT) & TRBPTR_PTR_MASK;
> +
> +	return addr;
> +}
> +
> +static inline void set_trbe_write_pointer(unsigned long addr)
> +{
> +	WARN_ON(is_trbe_enabled());
> +	addr = (addr >> TRBPTR_PTR_SHIFT) & TRBPTR_PTR_MASK;
> +	write_sysreg_s(addr, SYS_TRBPTR_EL1);
> +}
> +
> +static inline unsigned long get_trbe_limit_pointer(void)
> +{
> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> +	unsigned long limit = (trblimitr >> TRBLIMITR_LIMIT_SHIFT) & TRBLIMITR_LIMIT_MASK;
> +	unsigned long addr = limit << TRBLIMITR_LIMIT_SHIFT;
> +
> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> +	return addr;
> +}
> +
> +static inline unsigned long get_trbe_base_pointer(void)
> +{
> +	u64 trbbaser = read_sysreg_s(SYS_TRBBASER_EL1);
> +	unsigned long addr = (trbbaser >> TRBBASER_BASE_SHIFT) & TRBBASER_BASE_MASK;
> +
> +	addr = addr << TRBBASER_BASE_SHIFT;
> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> +	return addr;
> +}
> +
> +static inline void set_trbe_base_pointer(unsigned long addr)
> +{
> +	WARN_ON(is_trbe_enabled());
> +	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> +	write_sysreg_s(addr, SYS_TRBBASER_EL1);
> +}
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-02-12 16:57       ` Mathieu Poirier
@ 2021-02-15  9:26         ` Anshuman Khandual
  0 siblings, 0 replies; 90+ messages in thread
From: Anshuman Khandual @ 2021-02-15  9:26 UTC (permalink / raw)
  To: Mathieu Poirier
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel



On 2/12/21 10:27 PM, Mathieu Poirier wrote:
> [...]
> 
>>>
>>>
>>>> +	if (nr_pages < 2)
>>>> +		return NULL;
>>>> +
>>>> +	buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
>>>> +	if (IS_ERR(buf))
>>>> +		return ERR_PTR(-ENOMEM);
>>>> +
>>>> +	pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
>>>> +	if (IS_ERR(pglist)) {
>>>> +		kfree(buf);
>>>> +		return ERR_PTR(-ENOMEM);
>>>> +	}
>>>> +
>>>> +	for (i = 0; i < nr_pages; i++)
>>>> +		pglist[i] = virt_to_page(pages[i]);
>>>> +
>>>> +	buf->trbe_base = (unsigned long) vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
>>>> +	if (IS_ERR((void *)buf->trbe_base)) {
>>>
>>> Why not simply make buf->trbe_base a void * instead of having to do all this
>>
>> There are many arithmetic and comparison operations involving trbe_base
>> element. Hence it might be better to keep it as unsigned long, also to
>> keeps it consistent with other pointers i.e trbe_write, trbe_limit.
> 
> That is a fair point.  Please add a comment to explain your design choice and
> make sure the sparse checker is happy with all of it.

Added a comment.

> 
>>
>> Snippet from $cat drivers/hwtracing/coresight/coresight-trbe.c | grep "trbe_base"
>> There are just two places type casting trbe_base back to (void *).
>>
>> 	memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
>> 	return buf->trbe_base + offset;
>> 	WARN_ON(buf->trbe_write < buf->trbe_base);
>> 	set_trbe_base_pointer(buf->trbe_base);
>> 	buf->trbe_base = (unsigned long)vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
>> 	if (IS_ERR((void *)buf->trbe_base)) {
>> 		return ERR_PTR(buf->trbe_base);
>> 	buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
>> 	buf->trbe_write = buf->trbe_base;
>> 	vunmap((void *)buf->trbe_base);
>> 	base = get_trbe_base_pointer();
>> 	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
>> 	if (buf->trbe_limit == buf->trbe_base) {
>> 	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
>> 	if (buf->trbe_limit == buf->trbe_base) {
>> 	offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
>> 	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
>> 	if (buf->trbe_limit == buf->trbe_base) {
>> 	WARN_ON(buf->trbe_base != get_trbe_base_pointer());
>> 		if (get_trbe_write_pointer() == get_trbe_base_pointer())
>>   
>>> casting?  And IS_ERR() doesn't work with vmap().
>>
>> Sure, will drop IS_ERR() here.
>>
> 
> [...]
> 
> 
>>>
>>>> +
>>>> +static ssize_t dbm_show(struct device *dev, struct device_attribute *attr, char *buf)
>>>> +{
>>>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
>>>> +
>>>> +	return sprintf(buf, "%d\n", cpudata->trbe_dbm);
>>>> +}
>>>> +static DEVICE_ATTR_RO(dbm);
>>>
>>> What does "dbm" stand for?  Looking at the documentation for TRBIDR_EL1.F, I
>>> don't see what "dbm" relates to.
>>
>> I made it up to refer TRBIDR_EL1.F as "Dirty (and Access Flag) Bit Management".
>> Could change it as "afdbm" to be more specific or if it is preferred.
>>
> 
> I don't see "afdbm" being a better solution - why not simply "flag"?

Replaced all reference for "dbm" with "flag".

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-02-12 20:26   ` Mathieu Poirier
@ 2021-02-15  9:46     ` Anshuman Khandual
  2021-02-16  9:00       ` Mike Leach
  0 siblings, 1 reply; 90+ messages in thread
From: Anshuman Khandual @ 2021-02-15  9:46 UTC (permalink / raw)
  To: Mathieu Poirier
  Cc: linux-arm-kernel, coresight, suzuki.poulose, mike.leach,
	lcherian, linux-kernel


On 2/13/21 1:56 AM, Mathieu Poirier wrote:
> On Wed, Jan 27, 2021 at 02:25:35PM +0530, Anshuman Khandual wrote:
>> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
>> accessible via the system registers. The TRBE supports different addressing
>> modes including CPU virtual address and buffer modes including the circular
>> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
>> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
>> access to the trace buffer could be prohibited by a higher exception level
>> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
>> private interrupt (PPI) on address translation errors and when the buffer
>> is full. Overall implementation here is inspired from the Arm SPE driver.
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Mike Leach <mike.leach@linaro.org>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> Changes in V3:
>>
>> - Added new DT bindings document TRBE.yaml
>> - Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3
>> - Dropped isb() from trbe_reset_local()
>> - Dropped gap between (void *) and buf->trbe_base
>> - Changed 'int' to 'unsigned int' in is_trbe_available()
>> - Dropped unused function set_trbe_running(), set_trbe_virtual_mode(),
>>   set_trbe_enabled() and set_trbe_limit_pointer()
>> - Changed get_trbe_flag_update(), is_trbe_programmable() and
>>   get_trbe_address_align() to accept TRBIDR value
>> - Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), is_trbe_trg(),
>>   is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value
>> - Dropped snapshot mode condition in arm_trbe_alloc_buffer()
>> - Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled
>> - Compute trbe_limit before trbe_write to get the updated handle
>> - Added trbe_stop_and_truncate_event()
>> - Dropped trbe_handle_fatal()
>>
>>  Documentation/trace/coresight/coresight-trbe.rst |   39 +
>>  arch/arm64/include/asm/sysreg.h                  |    1 +
>>  drivers/hwtracing/coresight/Kconfig              |   11 +
>>  drivers/hwtracing/coresight/Makefile             |    1 +
>>  drivers/hwtracing/coresight/coresight-trbe.c     | 1023 ++++++++++++++++++++++
>>  drivers/hwtracing/coresight/coresight-trbe.h     |  160 ++++
>>  6 files changed, 1235 insertions(+)
>>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
>>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
>>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
>>
>> diff --git a/Documentation/trace/coresight/coresight-trbe.rst b/Documentation/trace/coresight/coresight-trbe.rst
>> new file mode 100644
>> index 0000000..1cbb819
>> --- /dev/null
>> +++ b/Documentation/trace/coresight/coresight-trbe.rst
>> @@ -0,0 +1,39 @@
>> +.. SPDX-License-Identifier: GPL-2.0
>> +
>> +==============================
>> +Trace Buffer Extension (TRBE).
>> +==============================
>> +
>> +    :Author:   Anshuman Khandual <anshuman.khandual@arm.com>
>> +    :Date:     November 2020
>> +
>> +Hardware Description
>> +--------------------
>> +
>> +Trace Buffer Extension (TRBE) is a percpu hardware which captures in system
>> +memory, CPU traces generated from a corresponding percpu tracing unit. This
>> +gets plugged in as a coresight sink device because the corresponding trace
>> +genarators (ETE), are plugged in as source device.
>> +
>> +The TRBE is not compliant to CoreSight architecture specifications, but is
>> +driven via the CoreSight driver framework to support the ETE (which is
>> +CoreSight compliant) integration.
>> +
>> +Sysfs files and directories
>> +---------------------------
>> +
>> +The TRBE devices appear on the existing coresight bus alongside the other
>> +coresight devices::
>> +
>> +	>$ ls /sys/bus/coresight/devices
>> +	trbe0  trbe1  trbe2 trbe3
>> +
>> +The ``trbe<N>`` named TRBEs are associated with a CPU.::
>> +
>> +	>$ ls /sys/bus/coresight/devices/trbe0/
>> +        align dbm
>> +
>> +*Key file items are:-*
>> +   * ``align``: TRBE write pointer alignment
>> +   * ``dbm``: TRBE updates memory with access and dirty flags
>> +
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 85ae4db..9e2e9b7 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -97,6 +97,7 @@
>>  #define SET_PSTATE_UAO(x)		__emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
>>  #define SET_PSTATE_SSBS(x)		__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
>>  #define SET_PSTATE_TCO(x)		__emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
>> +#define TSB_CSYNC			__emit_inst(0xd503225f)
>>  
>>  #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
>>  #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
>> index f154ae7..aa657ab 100644
>> --- a/drivers/hwtracing/coresight/Kconfig
>> +++ b/drivers/hwtracing/coresight/Kconfig
>> @@ -164,6 +164,17 @@ config CORESIGHT_CTI
>>  	  To compile this driver as a module, choose M here: the
>>  	  module will be called coresight-cti.
>>  
>> +config CORESIGHT_TRBE
>> +	bool "Trace Buffer Extension (TRBE) driver"
>> +	depends on ARM64
>> +	help
>> +	  This driver provides support for percpu Trace Buffer Extension (TRBE).
>> +	  TRBE always needs to be used along with it's corresponding percpu ETE
>> +	  component. ETE generates trace data which is then captured with TRBE.
>> +	  Unlike traditional sink devices, TRBE is a CPU feature accessible via
>> +	  system registers. But it's explicit dependency with trace unit (ETE)
>> +	  requires it to be plugged in as a coresight sink device.
>> +
>>  config CORESIGHT_CTI_INTEGRATION_REGS
>>  	bool "Access CTI CoreSight Integration Registers"
>>  	depends on CORESIGHT_CTI
>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
>> index f20e357..d608165 100644
>> --- a/drivers/hwtracing/coresight/Makefile
>> +++ b/drivers/hwtracing/coresight/Makefile
>> @@ -21,5 +21,6 @@ obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
>>  obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
>>  obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
>>  obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
>> +obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
>>  coresight-cti-y := coresight-cti-core.o	coresight-cti-platform.o \
>>  		   coresight-cti-sysfs.o
>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
>> new file mode 100644
>> index 0000000..1464d8b
>> --- /dev/null
>> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
>> @@ -0,0 +1,1023 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * This driver enables Trace Buffer Extension (TRBE) as a per-cpu coresight
>> + * sink device could then pair with an appropriate per-cpu coresight source
>> + * device (ETE) thus generating required trace data. Trace can be enabled
>> + * via the perf framework.
>> + *
>> + * Copyright (C) 2020 ARM Ltd.
>> + *
>> + * Author: Anshuman Khandual <anshuman.khandual@arm.com>
>> + */
>> +#define DRVNAME "arm_trbe"
>> +
>> +#define pr_fmt(fmt) DRVNAME ": " fmt
>> +
>> +#include "coresight-trbe.h"
>> +
>> +#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
>> +
>> +/*
>> + * A padding packet that will help the user space tools
>> + * in skipping relevant sections in the captured trace
>> + * data which could not be decoded. TRBE doesn't support
>> + * formatting the trace data, unlike the legacy CoreSight
>> + * sinks and thus we use ETE trace packets to pad the
>> + * sections of the buffer.
>> + */
>> +#define ETE_IGNORE_PACKET 		0x70
>> +
>> +/*
>> + * Minimum amount of meaningful trace will contain:
>> + * A-Sync, Trace Info, Trace On, Address, Atom.
>> + * This is about 44bytes of ETE trace. To be on
>> + * the safer side, we assume 64bytes is the minimum
>> + * space required for a meaningful session, before
>> + * we hit a "WRAP" event.
>> + */
>> +#define TRBE_TRACE_MIN_BUF_SIZE		64
>> +
>> +enum trbe_fault_action {
>> +	TRBE_FAULT_ACT_WRAP,
>> +	TRBE_FAULT_ACT_SPURIOUS,
>> +	TRBE_FAULT_ACT_FATAL,
>> +};
>> +
>> +struct trbe_buf {
>> +	unsigned long trbe_base;
>> +	unsigned long trbe_limit;
>> +	unsigned long trbe_write;
>> +	int nr_pages;
>> +	void **pages;
>> +	bool snapshot;
>> +	struct trbe_cpudata *cpudata;
>> +};
>> +
>> +struct trbe_cpudata {
>> +	bool trbe_dbm;
>> +	u64 trbe_align;
>> +	int cpu;
>> +	enum cs_mode mode;
>> +	struct trbe_buf *buf;
>> +	struct trbe_drvdata *drvdata;
>> +};
>> +
>> +struct trbe_drvdata {
>> +	struct trbe_cpudata __percpu *cpudata;
>> +	struct perf_output_handle __percpu **handle;
>> +	struct hlist_node hotplug_node;
>> +	int irq;
>> +	cpumask_t supported_cpus;
>> +	enum cpuhp_state trbe_online;
>> +	struct platform_device *pdev;
>> +};
>> +
>> +static int trbe_alloc_node(struct perf_event *event)
>> +{
>> +	if (event->cpu == -1)
>> +		return NUMA_NO_NODE;
>> +	return cpu_to_node(event->cpu);
>> +}
>> +
>> +static void trbe_drain_buffer(void)
>> +{
>> +	asm(TSB_CSYNC);
>> +	dsb(nsh);
>> +}
>> +
>> +static void trbe_drain_and_disable_local(void)
>> +{
>> +	trbe_drain_buffer();
>> +	write_sysreg_s(0, SYS_TRBLIMITR_EL1);
>> +	isb();
>> +}
>> +
>> +static void trbe_reset_local(void)
>> +{
>> +	trbe_drain_and_disable_local();
>> +	write_sysreg_s(0, SYS_TRBPTR_EL1);
>> +	write_sysreg_s(0, SYS_TRBBASER_EL1);
>> +	write_sysreg_s(0, SYS_TRBSR_EL1);
>> +}
>> +
>> +static void trbe_stop_and_truncate_event(struct perf_output_handle *handle)
>> +{
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +
>> +	/*
>> +	 * We cannot proceed with the buffer collection and we
>> +	 * do not have any data for the current session. The
>> +	 * etm_perf driver expects to close out the aux_buffer
>> +	 * at event_stop(). So disable the TRBE here and leave
>> +	 * the update_buffer() to return a 0 size.
>> +	 */
>> +	trbe_drain_and_disable_local();
>> +	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
>> +	*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
>> +}
>> +
>> +/*
>> + * TRBE Buffer Management
>> + *
>> + * The TRBE buffer spans from the base pointer till the limit pointer. When enabled,
>> + * it starts writing trace data from the write pointer onward till the limit pointer.
>> + * When the write pointer reaches the address just before the limit pointer, it gets
>> + * wrapped around again to the base pointer. This is called a TRBE wrap event, which
>> + * generates a maintenance interrupt when operated in WRAP or FILL mode. This driver
>> + * uses FILL mode, where the TRBE stops the trace collection at wrap event. The IRQ
>> + * handler updates the AUX buffer and re-enables the TRBE with updated WRITE and
>> + * LIMIT pointers.
>> + *
>> + *	Wrap around with an IRQ
>> + *	------ < ------ < ------- < ----- < -----
>> + *	|					|
>> + *	------ > ------ > ------- > ----- > -----
>> + *
>> + *	+---------------+-----------------------+
>> + *	|		|			|
>> + *	+---------------+-----------------------+
>> + *	Base Pointer	Write Pointer		Limit Pointer
>> + *
>> + * The base and limit pointers always needs to be PAGE_SIZE aligned. But the write
>> + * pointer can be aligned to the implementation defined TRBE trace buffer alignment
>> + * as captured in trbe_cpudata->trbe_align.
>> + *
>> + *
>> + *		head		tail		wakeup
>> + *	+---------------------------------------+----- ~ ~ ------
>> + *	|$$$$$$$|################|$$$$$$$$$$$$$$|		|
>> + *	+---------------------------------------+----- ~ ~ ------
>> + *	Base Pointer	Write Pointer		Limit Pointer
>> + *
>> + * The perf_output_handle indices (head, tail, wakeup) are monotonically increasing
>> + * values which tracks all the driver writes and user reads from the perf auxiliary
>> + * buffer. Generally [head..tail] is the area where the driver can write into unless
>> + * the wakeup is behind the tail. Enabled TRBE buffer span needs to be adjusted and
>> + * configured depending on the perf_output_handle indices, so that the driver does
>> + * not override into areas in the perf auxiliary buffer which is being or yet to be
>> + * consumed from the user space. The enabled TRBE buffer area is a moving subset of
>> + * the allocated perf auxiliary buffer.
>> + */
>> +static void trbe_pad_buf(struct perf_output_handle *handle, int len)
>> +{
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +	u64 head = PERF_IDX2OFF(handle->head, buf);
>> +
>> +	memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
>> +	if (!buf->snapshot)
>> +		perf_aux_output_skip(handle, len);
>> +}
>> +
>> +static unsigned long trbe_snapshot_offset(struct perf_output_handle *handle)
>> +{
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +
>> +	/*
>> +	 * The ETE trace has alignment synchronization packets allowing
>> +	 * the decoder to reset in case of an overflow or corruption.
>> +	 * So we can use the entire buffer for the snapshot mode.
>> +	 */
>> +	return buf->nr_pages * PAGE_SIZE;
>> +}
>> +
>> +/*
>> + * TRBE Limit Calculation
>> + *
>> + * The following markers are used to illustrate various TRBE buffer situations.
>> + *
>> + * $$$$ - Data area, unconsumed captured trace data, not to be overridden
>> + * #### - Free area, enabled, trace will be written
>> + * %%%% - Free area, disabled, trace will not be written
>> + * ==== - Free area, padded with ETE_IGNORE_PACKET, trace will be skipped
>> + */
>> +static unsigned long __trbe_normal_offset(struct perf_output_handle *handle)
>> +{
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +	struct trbe_cpudata *cpudata = buf->cpudata;
>> +	const u64 bufsize = buf->nr_pages * PAGE_SIZE;
>> +	u64 limit = bufsize;
>> +	u64 head, tail, wakeup;
>> +
>> +	head = PERF_IDX2OFF(handle->head, buf);
>> +
>> +	/*
>> +	 *		head
>> +	 *	------->|
>> +	 *	|
>> +	 *	head	TRBE align	tail
>> +	 * +----|-------|---------------|-------+
>> +	 * |$$$$|=======|###############|$$$$$$$|
>> +	 * +----|-------|---------------|-------+
>> +	 * trbe_base				trbe_base + nr_pages
>> +	 *
>> +	 * Perf aux buffer output head position can be misaligned depending on
>> +	 * various factors including user space reads. In case misaligned, head
>> +	 * needs to be aligned before TRBE can be configured. Pad the alignment
>> +	 * gap with ETE_IGNORE_PACKET bytes that will be ignored by user tools
>> +	 * and skip this section thus advancing the head.
>> +	 */
>> +	if (!IS_ALIGNED(head, cpudata->trbe_align)) {
>> +		unsigned long delta = roundup(head, cpudata->trbe_align) - head;
>> +
>> +		delta = min(delta, handle->size);
>> +		trbe_pad_buf(handle, delta);
>> +		head = PERF_IDX2OFF(handle->head, buf);
>> +	}
>> +
>> +	/*
>> +	 *	head = tail (size = 0)
>> +	 * +----|-------------------------------+
>> +	 * |$$$$|$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$	|
>> +	 * +----|-------------------------------+
>> +	 * trbe_base				trbe_base + nr_pages
>> +	 *
>> +	 * Perf aux buffer does not have any space for the driver to write into.
>> +	 * Just communicate trace truncation event to the user space by marking
>> +	 * it with PERF_AUX_FLAG_TRUNCATED.
>> +	 */
>> +	if (!handle->size) {
>> +		perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
>> +		return 0;
>> +	}
>> +
>> +	/* Compute the tail and wakeup indices now that we've aligned head */
>> +	tail = PERF_IDX2OFF(handle->head + handle->size, buf);
>> +	wakeup = PERF_IDX2OFF(handle->wakeup, buf);
>> +
>> +	/*
>> +	 * Lets calculate the buffer area which TRBE could write into. There
>> +	 * are three possible scenarios here. Limit needs to be aligned with
>> +	 * PAGE_SIZE per the TRBE requirement. Always avoid clobbering the
>> +	 * unconsumed data.
>> +	 *
>> +	 * 1) head < tail
>> +	 *
>> +	 *	head			tail
>> +	 * +----|-----------------------|-------+
>> +	 * |$$$$|#######################|$$$$$$$|
>> +	 * +----|-----------------------|-------+
>> +	 * trbe_base			limit	trbe_base + nr_pages
>> +	 *
>> +	 * TRBE could write into [head..tail] area. Unless the tail is right at
>> +	 * the end of the buffer, neither an wrap around nor an IRQ is expected
>> +	 * while being enabled.
>> +	 *
>> +	 * 2) head == tail
>> +	 *
>> +	 *	head = tail (size > 0)
>> +	 * +----|-------------------------------+
>> +	 * |%%%%|###############################|
>> +	 * +----|-------------------------------+
>> +	 * trbe_base				limit = trbe_base + nr_pages
>> +	 *
>> +	 * TRBE should just write into [head..base + nr_pages] area even though
>> +	 * the entire buffer is empty. Reason being, when the trace reaches the
>> +	 * end of the buffer, it will just wrap around with an IRQ giving an
>> +	 * opportunity to reconfigure the buffer.
>> +	 *
>> +	 * 3) tail < head
>> +	 *
>> +	 *	tail			head
>> +	 * +----|-----------------------|-------+
>> +	 * |%%%%|$$$$$$$$$$$$$$$$$$$$$$$|#######|
>> +	 * +----|-----------------------|-------+
>> +	 * trbe_base				limit = trbe_base + nr_pages
>> +	 *
>> +	 * TRBE should just write into [head..base + nr_pages] area even though
>> +	 * the [trbe_base..tail] is also empty. Reason being, when the trace
>> +	 * reaches the end of the buffer, it will just wrap around with an IRQ
>> +	 * giving an opportunity to reconfigure the buffer.
>> +	 */
>> +	if (head < tail)
>> +		limit = round_down(tail, PAGE_SIZE);
>> +
>> +	/*
>> +	 * Wakeup may be arbitrarily far into the future. If it's not in the
>> +	 * current generation, either we'll wrap before hitting it, or it's
>> +	 * in the past and has been handled already.
>> +	 *
>> +	 * If there's a wakeup before we wrap, arrange to be woken up by the
>> +	 * page boundary following it. Keep the tail boundary if that's lower.
>> +	 *
>> +	 *	head		wakeup	tail
>> +	 * +----|---------------|-------|-------+
>> +	 * |$$$$|###############|%%%%%%%|$$$$$$$|
>> +	 * +----|---------------|-------|-------+
>> +	 * trbe_base		limit		trbe_base + nr_pages
>> +	 */
>> +	if (handle->wakeup < (handle->head + handle->size) && head <= wakeup)
>> +		limit = min(limit, round_up(wakeup, PAGE_SIZE));
>> +
>> +	/*
>> +	 * There are two situation when this can happen i.e limit is before
>> +	 * the head and hence TRBE cannot be configured.
>> +	 *
>> +	 * 1) head < tail (aligned down with PAGE_SIZE) and also they are both
>> +	 * within the same PAGE size range.
>> +	 *
>> +	 *			PAGE_SIZE
>> +	 *		|----------------------|
>> +	 *
>> +	 *		limit	head	tail
>> +	 * +------------|------|--------|-------+
>> +	 * |$$$$$$$$$$$$$$$$$$$|========|$$$$$$$|
>> +	 * +------------|------|--------|-------+
>> +	 * trbe_base				trbe_base + nr_pages
>> +	 *
>> +	 * 2) head < wakeup (aligned up with PAGE_SIZE) < tail and also both
>> +	 * head and wakeup are within same PAGE size range.
>> +	 *
>> +	 *		PAGE_SIZE
>> +	 *	|----------------------|
>> +	 *
>> +	 *	limit	head	wakeup  tail
>> +	 * +----|------|-------|--------|-------+
>> +	 * |$$$$$$$$$$$|=======|========|$$$$$$$|
>> +	 * +----|------|-------|--------|-------+
>> +	 * trbe_base				trbe_base + nr_pages
>> +	 */
>> +	if (limit > head)
>> +		return limit;
>> +
>> +	trbe_pad_buf(handle, handle->size);
>> +	perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
>> +	return 0;
>> +}
>> +
>> +static unsigned long trbe_normal_offset(struct perf_output_handle *handle)
>> +{
>> +	struct trbe_buf *buf = perf_get_aux(handle);
>> +	u64 limit = __trbe_normal_offset(handle);
>> +	u64 head = PERF_IDX2OFF(handle->head, buf);
>> +
>> +	/*
>> +	 * If the head is too close to the limit and we don't
>> +	 * have space for a meaningful run, we rather pad it
>> +	 * and start fresh.
>> +	 */
>> +	if (limit && (limit - head < TRBE_TRACE_MIN_BUF_SIZE)) {
>> +		trbe_pad_buf(handle, limit - head);
>> +		limit = __trbe_normal_offset(handle);
>> +	}
>> +	return limit;
>> +}
>> +
>> +static unsigned long compute_trbe_buffer_limit(struct perf_output_handle *handle)
>> +{
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +	unsigned long offset;
>> +
>> +	if (buf->snapshot)
>> +		offset = trbe_snapshot_offset(handle);
>> +	else
>> +		offset = trbe_normal_offset(handle);
>> +	return buf->trbe_base + offset;
>> +}
> 
> I won't review the trace buffer management functions in this revision, I will
> leave that for the next version.

Okay.

> 
>> +
>> +static void clr_trbe_status(void)
>> +{
>> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
>> +
>> +	WARN_ON(is_trbe_enabled());
>> +	trbsr &= ~TRBSR_IRQ;
>> +	trbsr &= ~TRBSR_TRG;
>> +	trbsr &= ~TRBSR_WRAP;
>> +	trbsr &= ~(TRBSR_EC_MASK << TRBSR_EC_SHIFT);
>> +	trbsr &= ~(TRBSR_BSC_MASK << TRBSR_BSC_SHIFT);
>> +	trbsr &= ~TRBSR_STOP;
>> +	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
>> +}
> 
> I haven't read the TRBE progammer's manual but looking a the documentation the above
> looks good.
> 
>> +
>> +static void set_trbe_limit_pointer_enabled(unsigned long addr)
>> +{
>> +	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
>> +
>> +	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
>> +	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
>> +
>> +	trblimitr &= ~TRBLIMITR_NVM;
>> +	trblimitr &= ~(TRBLIMITR_FILL_MODE_MASK << TRBLIMITR_FILL_MODE_SHIFT);
>> +	trblimitr &= ~(TRBLIMITR_TRIG_MODE_MASK << TRBLIMITR_TRIG_MODE_SHIFT);
>> +	trblimitr &= ~(TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT);
>> +
>> +	/*
>> +	 * Fill trace buffer mode is used here while configuring the
>> +	 * TRBE for trace capture. In this particular mode, the trace
>> +	 * collection is stopped and a maintenance interrupt is raised
>> +	 * when the current write pointer wraps. This pause in trace
>> +	 * collection gives the software an opportunity to capture the
>> +	 * trace data in the interrupt handler, before reconfiguring
>> +	 * the TRBE.
>> +	 */
>> +	trblimitr |= (TRBE_FILL_MODE_FILL & TRBLIMITR_FILL_MODE_MASK) << TRBLIMITR_FILL_MODE_SHIFT;
>> +
>> +	/*
>> +	 * Trigger mode is not used here while configuring the TRBE for
>> +	 * the trace capture. Hence just keep this in the ignore mode.
>> +	 */
>> +	trblimitr |= (TRBE_TRIG_MODE_IGNORE & TRBLIMITR_TRIG_MODE_MASK) << TRBLIMITR_TRIG_MODE_SHIFT;
>> +	trblimitr |= (addr & PAGE_MASK);
>> +
>> +	trblimitr |= TRBLIMITR_ENABLE;
>> +	write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
>> +}
> 
> Same here
> 
>> +
>> +static void trbe_enable_hw(struct trbe_buf *buf)
>> +{
>> +	WARN_ON(buf->trbe_write < buf->trbe_base);
>> +	WARN_ON(buf->trbe_write >= buf->trbe_limit);
>> +	set_trbe_disabled();
>> +	isb();
>> +	clr_trbe_status();
>> +	set_trbe_base_pointer(buf->trbe_base);
>> +	set_trbe_write_pointer(buf->trbe_write);
>> +
>> +	/*
>> +	 * Synchronize all the register updates
>> +	 * till now before enabling the TRBE.
>> +	 */
>> +	isb();
>> +	set_trbe_limit_pointer_enabled(buf->trbe_limit);
>> +
>> +	/* Synchronize the TRBE enable event */
>> +	isb();
>> +}
> 
> Ok
> 
>> +
>> +static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
>> +				   struct perf_event *event, void **pages,
>> +				   int nr_pages, bool snapshot)
>> +{
>> +	struct trbe_buf *buf;
>> +	struct page **pglist;
>> +	int i;
>> +
>> +	/*
>> +	 * TRBE LIMIT and TRBE WRITE pointers must be page aligned. But with
>> +	 * just a single page, there is not much room left while writing into
>> +	 * a partially filled TRBE buffer. Hence restrict the minimum buffer
>> +	 * size as two pages.
>> +	 */
>> +	if (nr_pages < 2)
>> +		return NULL;
>> +
>> +	buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
>> +	if (IS_ERR(buf))
>> +		return ERR_PTR(-ENOMEM);
> 
> You know what do to.

Right, will check for NULL instead and return ERR_PTR(-ENOMEM) as
the function return type is (void *).

> 
>> +
>> +	pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
>> +	if (IS_ERR(pglist)) {
>> +		kfree(buf);
>> +		return ERR_PTR(-ENOMEM);
>> +	}
> 
> Here too.

Yes, changed.

> 
>> +
>> +	for (i = 0; i < nr_pages; i++)
>> +		pglist[i] = virt_to_page(pages[i]);
>> +
>> +	buf->trbe_base = (unsigned long) vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
>> +	if (IS_ERR((void *)buf->trbe_base)) {
>> +		kfree(pglist);
>> +		kfree(buf);
>> +		return ERR_PTR(buf->trbe_base);
>> +	}
> 
> Here too.

Yes, changed.

> 
>> +	buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
>> +	buf->trbe_write = buf->trbe_base;
>> +	buf->snapshot = snapshot;
>> +	buf->nr_pages = nr_pages;
>> +	buf->pages = pages;
>> +	kfree(pglist);
>> +	return buf;
>> +}
>> +
>> +void arm_trbe_free_buffer(void *config)

Added the missing 'static' here.

>> +{
>> +	struct trbe_buf *buf = config;
>> +
>> +	vunmap((void *)buf->trbe_base);
>> +	kfree(buf);
>> +}
> 
> Ok
> 
>> +
>> +static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
>> +					    struct perf_output_handle *handle,
>> +					    void *config)
>> +{
>> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
>> +	struct trbe_buf *buf = config;
>> +	unsigned long size, offset;
>> +
>> +	WARN_ON(buf->cpudata != cpudata);
>> +	WARN_ON(cpudata->cpu != smp_processor_id());
>> +	WARN_ON(cpudata->drvdata != drvdata);
>> +	if (cpudata->mode != CS_MODE_PERF)
>> +		return -EINVAL;
>> +
>> +	/*
>> +	 * If the TRBE was disabled due to lack of space in the AUX buffer or a
>> +	 * spurious fault, the driver leaves it disabled, truncating the buffer.
>> +	 * Since the etm_perf driver expects to close out the AUX buffer, the
>> +	 * driver skips it. Thus, just pass in 0 size here to indicate that the
>> +	 * buffer was truncated.
>> +	 */
>> +	if (!is_trbe_enabled())
>> +		return 0;
>> +	/*
>> +	 * perf handle structure needs to be shared with the TRBE IRQ handler for
>> +	 * capturing trace data and restarting the handle. There is a probability
>> +	 * of an undefined reference based crash when etm event is being stopped
>> +	 * while a TRBE IRQ also getting processed. This happens due the release
>> +	 * of perf handle via perf_aux_output_end() in etm_event_stop(). Stopping
>> +	 * the TRBE here will ensure that no IRQ could be generated when the perf
>> +	 * handle gets freed in etm_event_stop().
>> +	 */
>> +	trbe_drain_and_disable_local();
>> +	offset = get_trbe_write_pointer() - get_trbe_base_pointer();
>> +	size = offset - PERF_IDX2OFF(handle->head, buf);
>> +	if (buf->snapshot)
>> +		handle->head += size;
>> +	return size;
>> +}
> 
> Ok - I really appreciate the comments.
> 
>> +
>> +static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)
>> +{
>> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
>> +	struct perf_output_handle *handle = data;
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +
>> +	WARN_ON(cpudata->cpu != smp_processor_id());
>> +	WARN_ON(cpudata->drvdata != drvdata);
>> +	if (mode != CS_MODE_PERF)
>> +		return -EINVAL;
>> +
>> +	*this_cpu_ptr(drvdata->handle) = handle;
>> +	cpudata->buf = buf;
>> +	cpudata->mode = mode;
>> +	buf->cpudata = cpudata;
>> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
>> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
>> +	if (buf->trbe_limit == buf->trbe_base) {
>> +		trbe_stop_and_truncate_event(handle);
>> +		return 0;
>> +	}
>> +	trbe_enable_hw(buf);
>> +	return 0;
>> +}
> 
> Ok
> 
>> +
>> +static int arm_trbe_disable(struct coresight_device *csdev)
>> +{
>> +	struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> +	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
>> +	struct trbe_buf *buf = cpudata->buf;
>> +
>> +	WARN_ON(buf->cpudata != cpudata);
>> +	WARN_ON(cpudata->cpu != smp_processor_id());
>> +	WARN_ON(cpudata->drvdata != drvdata);
>> +	if (cpudata->mode != CS_MODE_PERF)
>> +		return -EINVAL;
>> +
>> +	trbe_drain_and_disable_local();
>> +	buf->cpudata = NULL;
>> +	cpudata->buf = NULL;
>> +	cpudata->mode = CS_MODE_DISABLED;
>> +	return 0;
>> +}
> 
> Ok
> 
>> +
>> +static void trbe_handle_spurious(struct perf_output_handle *handle)
>> +{
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +
>> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
>> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
>> +	if (buf->trbe_limit == buf->trbe_base) {
>> +		trbe_drain_and_disable_local();
>> +		return;
>> +	}
>> +	trbe_enable_hw(buf);
>> +}
>> +
>> +static void trbe_handle_overflow(struct perf_output_handle *handle)
>> +{
>> +	struct perf_event *event = handle->event;
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +	unsigned long offset, size;
>> +	struct etm_event_data *event_data;
>> +
>> +	offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
>> +	size = offset - PERF_IDX2OFF(handle->head, buf);
>> +	if (buf->snapshot)
>> +		handle->head = offset;
>> +	perf_aux_output_end(handle, size);
>> +
>> +	event_data = perf_aux_output_begin(handle, event);
>> +	if (!event_data) {
>> +		trbe_drain_and_disable_local();
>> +		*this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
>> +		return;
>> +	}
>> +	buf->trbe_limit = compute_trbe_buffer_limit(handle);
>> +	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
>> +	if (buf->trbe_limit == buf->trbe_base) {
>> +		trbe_stop_and_truncate_event(handle);
>> +		return;
>> +	}
>> +	*this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;
>> +	trbe_enable_hw(buf);
>> +}
>> +
>> +static bool is_perf_trbe(struct perf_output_handle *handle)
>> +{
>> +	struct trbe_buf *buf = etm_perf_sink_config(handle);
>> +	struct trbe_cpudata *cpudata = buf->cpudata;
>> +	struct trbe_drvdata *drvdata = cpudata->drvdata;
>> +	int cpu = smp_processor_id();
>> +
>> +	WARN_ON(buf->trbe_base != get_trbe_base_pointer());
>> +	WARN_ON(buf->trbe_limit != get_trbe_limit_pointer());
>> +
>> +	if (cpudata->mode != CS_MODE_PERF)
>> +		return false;
>> +
>> +	if (cpudata->cpu != cpu)
>> +		return false;
>> +
>> +	if (!cpumask_test_cpu(cpu, &drvdata->supported_cpus))
>> +		return false;
>> +
>> +	return true;
>> +}
>> +
>> +static enum trbe_fault_action trbe_get_fault_act(struct perf_output_handle *handle)
> 
> @handle isn't used for anything.

Okay, will drop.

> 
>> +{
>> +	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
>> +	int ec = get_trbe_ec(trbsr);
>> +	int bsc = get_trbe_bsc(trbsr);
>> +
>> +	WARN_ON(is_trbe_running(trbsr));
>> +	if (is_trbe_trg(trbsr) || is_trbe_abort(trbsr))
>> +		return TRBE_FAULT_ACT_FATAL;
>> +
>> +	if ((ec == TRBE_EC_STAGE1_ABORT) || (ec == TRBE_EC_STAGE2_ABORT))
>> +		return TRBE_FAULT_ACT_FATAL;
>> +
>> +	if (is_trbe_wrap(trbsr) && (ec == TRBE_EC_OTHERS) && (bsc == TRBE_BSC_FILLED)) {
>> +		if (get_trbe_write_pointer() == get_trbe_base_pointer())
>> +			return TRBE_FAULT_ACT_WRAP;
>> +	}
>> +	return TRBE_FAULT_ACT_SPURIOUS;
>> +}
>> +
>> +static irqreturn_t arm_trbe_irq_handler(int irq, void *dev)
>> +{
>> +	struct perf_output_handle **handle_ptr = dev;
>> +	struct perf_output_handle *handle = *handle_ptr;
>> +	enum trbe_fault_action act;
>> +
>> +	WARN_ON(!is_trbe_irq(read_sysreg_s(SYS_TRBSR_EL1)));
>> +	clr_trbe_irq();
>> +
>> +	/*
>> +	 * Ensure the trace is visible to the CPUs and
>> +	 * any external aborts have been resolved.
>> +	 */
>> +	trbe_drain_buffer();
>> +	isb();
>> +
>> +	if (!perf_get_aux(handle))
>> +		return IRQ_NONE;
>> +
>> +	if (!is_perf_trbe(handle))
>> +		return IRQ_NONE;
>> +
>> +	irq_work_run();
> 
> I trust Will that this is the right thing to do.
> 
> I will stop here for this revision.  I will dive more in the mechanic of the
> TRBE on the next revision.

Okay, will collate all the changes till now and respin sooner.

- Anshuman

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 05/14] coresight: ete: Add support for ETE tracing
  2021-02-02 18:56   ` Mathieu Poirier
  2021-02-02 22:50     ` Suzuki K Poulose
@ 2021-02-15 13:21     ` Mike Leach
  2021-02-15 14:08       ` Mike Leach
  1 sibling, 1 reply; 90+ messages in thread
From: Mike Leach @ 2021-02-15 13:21 UTC (permalink / raw)
  To: Mathieu Poirier
  Cc: Anshuman Khandual, linux-arm-kernel, Coresight ML,
	Suzuki K. Poulose, Linu Cherian, Linux Kernel Mailing List

HI,

On Tue, 2 Feb 2021 at 18:56, Mathieu Poirier <mathieu.poirier@linaro.org> wrote:
>
> On Wed, Jan 27, 2021 at 02:25:29PM +0530, Anshuman Khandual wrote:
> > From: Suzuki K Poulose <suzuki.poulose@arm.com>
> >
> > Add ETE as one of the supported device types we support
> > with ETM4x driver. The devices are named following the
> > existing convention as ete<N>.
> >
> > ETE mandates that the trace resource status register is programmed
> > before the tracing is turned on. For the moment simply write to
> > it indicating TraceActive.
> >
> > Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Cc: Mike Leach <mike.leach@linaro.org>
> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> > ---
> >  drivers/hwtracing/coresight/Kconfig                | 10 ++--
> >  drivers/hwtracing/coresight/coresight-etm4x-core.c | 56 +++++++++++++++++-----
> >  .../hwtracing/coresight/coresight-etm4x-sysfs.c    | 19 ++++++--
> >  drivers/hwtracing/coresight/coresight-etm4x.h      | 16 ++++++-
> >  4 files changed, 79 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> > index 7b44ba2..f154ae7 100644
> > --- a/drivers/hwtracing/coresight/Kconfig
> > +++ b/drivers/hwtracing/coresight/Kconfig
> > @@ -97,15 +97,15 @@ config CORESIGHT_SOURCE_ETM3X
> >         module will be called coresight-etm3x.
> >
> >  config CORESIGHT_SOURCE_ETM4X
> > -     tristate "CoreSight Embedded Trace Macrocell 4.x driver"
> > +     tristate "CoreSight ETMv4.x / ETE driver"
> >       depends on ARM64
> >       select CORESIGHT_LINKS_AND_SINKS
> >       select PID_IN_CONTEXTIDR
> >       help
> > -       This driver provides support for the ETM4.x tracer module, tracing the
> > -       instructions that a processor is executing. This is primarily useful
> > -       for instruction level tracing. Depending on the implemented version
> > -       data tracing may also be available.
> > +       This driver provides support for the CoreSight Embedded Trace Macrocell
> > +       version 4.x and the Embedded Trace Extensions (ETE). Both are CPU tracer
> > +       modules, tracing the instructions that a processor is executing. This is
> > +       primarily useful for instruction level tracing.
> >
> >         To compile this driver as a module, choose M here: the
> >         module will be called coresight-etm4x.
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > index 9e92d2a..b40e3c2 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > @@ -431,6 +431,13 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> >               etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
> >       }
> >
> > +     /*
> > +      * ETE mandates that the TRCRSR is written to before
> > +      * enabling it.
> > +      */
> > +     if (etm4x_is_ete(drvdata))
> > +             etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
> > +
> >       /* Enable the trace unit */
> >       etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
> >
> > @@ -864,13 +871,24 @@ static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
> >        * ETMs implementing sysreg access must implement TRCDEVARCH.
> >        */
> >       devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
> > -     if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH)
> > +     switch (devarch & ETM_DEVARCH_ID_MASK) {
> > +     case ETM_DEVARCH_ETMv4x_ARCH:
> > +             *csa = (struct csdev_access) {
> > +                     .io_mem = false,
> > +                     .read   = etm4x_sysreg_read,
> > +                     .write  = etm4x_sysreg_write,
> > +             };
> > +             break;
> > +     case ETM_DEVARCH_ETE_ARCH:
> > +             *csa = (struct csdev_access) {
> > +                     .io_mem = false,
> > +                     .read   = ete_sysreg_read,
> > +                     .write  = ete_sysreg_write,
> > +             };
> > +             break;
> > +     default:
> >               return false;
> > -     *csa = (struct csdev_access) {
> > -             .io_mem = false,
> > -             .read   = etm4x_sysreg_read,
> > -             .write  = etm4x_sysreg_write,
> > -     };
> > +     }
> >
> >       drvdata->arch = etm_devarch_to_arch(devarch);
> >       return true;
> > @@ -1808,6 +1826,8 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
> >       struct etmv4_drvdata *drvdata;
> >       struct coresight_desc desc = { 0 };
> >       struct etm4_init_arg init_arg = { 0 };
> > +     u8 major, minor;
> > +     char *type_name;
> >
> >       drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> >       if (!drvdata)
> > @@ -1834,10 +1854,6 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
> >       if (drvdata->cpu < 0)
> >               return drvdata->cpu;
> >
> > -     desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
> > -     if (!desc.name)
> > -             return -ENOMEM;
> > -
> >       init_arg.drvdata = drvdata;
> >       init_arg.csa = &desc.access;
> >       init_arg.pid = etm_pid;
> > @@ -1853,6 +1869,20 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
> >       if (!desc.access.io_mem ||
> >           fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
> >               drvdata->skip_power_up = true;
>
> Add a space here...
>
> > +     major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
> > +     minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
>
> And here too.  Othersiwe it makes a big blob in the middle of the function.
>
> > +     if (etm4x_is_ete(drvdata)) {
> > +             type_name = "ete";
> > +             /* ETE v1 has major version == 5. Adjust this for logging.*/
> > +             major -= 4;
>
> I don't have the documentation for the ETE but I would not adjust @major.  I
> would simply leave it to what the HW gives us since regardless of the name, the
> major revision of the IP block is 5.
>

For consistency this adjustment should be retained. All the prior
drivers reported the protocol version related to this.
For ETM3.x this value was 0x2 - logging printed "ETMv3.x", for PTM
this value was 0x3 - logging printed "PTM 1.x".
Only for ETMv4 is this value the same as the protocol version.

Mike


> > +     } else {
> > +             type_name = "etm";
> > +     }
> > +
> > +     desc.name = devm_kasprintf(dev, GFP_KERNEL,
> > +                                "%s%d", type_name, drvdata->cpu);
> > +     if (!desc.name)
> > +             return -ENOMEM;
> >
> >       etm4_init_trace_id(drvdata);
> >       etm4_set_default(&drvdata->config);
> > @@ -1881,9 +1911,8 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
> >
> >       etmdrvdata[drvdata->cpu] = drvdata;
> >
> > -     dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n",
> > -              drvdata->cpu, ETM_ARCH_MAJOR_VERSION(drvdata->arch),
> > -              ETM_ARCH_MINOR_VERSION(drvdata->arch));
> > +     dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
> > +              drvdata->cpu, type_name, major, minor);
> >
> >       if (boot_enable) {
> >               coresight_enable(drvdata->csdev);
> > @@ -2027,6 +2056,7 @@ static struct amba_driver etm4x_amba_driver = {
> >
> >  static const struct of_device_id etm4_sysreg_match[] = {
> >       { .compatible   = "arm,coresight-etm4x-sysreg" },
> > +     { .compatible   = "arm,embedded-trace-extension" },
> >       {}
> >  };
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index b646d53..1c490bc 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -2374,12 +2374,20 @@ static inline bool
> >  etm4x_register_implemented(struct etmv4_drvdata *drvdata, u32 offset)
> >  {
> >       switch (offset) {
> > -     ETM4x_SYSREG_LIST_CASES
> > +     ETM_COMMON_SYSREG_LIST_CASES
> >               /*
> > -              * Registers accessible via system instructions are always
> > -              * implemented.
> > +              * Common registers to ETE & ETM4x accessible via system
> > +              * instructions are always implemented.
> >                */
> >               return true;
> > +
> > +     ETM4x_ONLY_SYSREG_LIST_CASES
> > +             /*
> > +              * We only support etm4x and ete. So if the device is not
> > +              * ETE, it must be ETMv4x.
> > +              */
> > +             return !etm4x_is_ete(drvdata);
> > +
> >       ETM4x_MMAP_LIST_CASES
> >               /*
> >                * Registers accessible only via memory-mapped registers
> > @@ -2389,8 +2397,13 @@ etm4x_register_implemented(struct etmv4_drvdata *drvdata, u32 offset)
> >                * coresight_register() and the csdev is not initialized
> >                * until that is done. So rely on the drvdata->base to
> >                * detect if we have a memory mapped access.
> > +              * Also ETE doesn't implement memory mapped access, thus
> > +              * it is sufficient to check that we are using mmio.
> >                */
> >               return !!drvdata->base;
> > +
> > +     ETE_ONLY_SYSREG_LIST_CASES
> > +             return etm4x_is_ete(drvdata);
> >       }
> >
> >       return false;
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> > index ca24ac5..8b90de5 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> > @@ -128,6 +128,8 @@
> >  #define TRCCIDR2                     0xFF8
> >  #define TRCCIDR3                     0xFFC
> >
> > +#define TRCRSR_TA                    BIT(12)
> > +
> >  /*
> >   * System instructions to access ETM registers.
> >   * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
> > @@ -390,6 +392,9 @@
> >  #define ETM_COMMON_SYSREG_LIST_CASES         \
> >       ETM_COMMON_SYSREG_LIST(NOP, __unused)
> >
> > +#define ETM4x_ONLY_SYSREG_LIST_CASES         \
> > +     ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
> > +
> >  #define ETM4x_SYSREG_LIST_CASES                      \
> >       ETM_COMMON_SYSREG_LIST_CASES            \
> >       ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
> > @@ -406,7 +411,6 @@
> >       ETE_ONLY_SYSREG_LIST(WRITE, (val))
> >
> >  #define ETE_ONLY_SYSREG_LIST_CASES           \
> > -     ETM_COMMON_SYSREG_LIST_CASES            \
>
> This goes in patch 04.
>
> With the above:
>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>
> >       ETE_ONLY_SYSREG_LIST(NOP, __unused)
> >
> >  #define read_etm4x_sysreg_offset(offset, _64bit)                             \
> > @@ -589,11 +593,14 @@
> >       ((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13))
> >
> >  #define ETM_DEVARCH_ARCHID_ETMv4x            ETM_DEVARCH_MAKE_ARCHID(0x4)
> > +#define ETM_DEVARCH_ARCHID_ETE                       ETM_DEVARCH_MAKE_ARCHID(0x5)
> >
> >  #define ETM_DEVARCH_ID_MASK                                          \
> >       (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT)
> >  #define ETM_DEVARCH_ETMv4x_ARCH                                              \
> >       (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT)
> > +#define ETM_DEVARCH_ETE_ARCH                                         \
> > +     (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT)
> >
> >  #define TRCSTATR_IDLE_BIT            0
> >  #define TRCSTATR_PMSTABLE_BIT                1
> > @@ -683,6 +690,8 @@
> >  #define ETM_ARCH_MINOR_VERSION(arch) ((arch) & 0xfU)
> >
> >  #define ETM_ARCH_V4  ETM_ARCH_VERSION(4, 0)
> > +#define ETM_ARCH_ETE ETM_ARCH_VERSION(5, 0)
> > +
> >  /* Interpretation of resource numbers change at ETM v4.3 architecture */
> >  #define ETM_ARCH_V4_3        ETM_ARCH_VERSION(4, 3)
> >
> > @@ -989,4 +998,9 @@ void etm4_config_trace_mode(struct etmv4_config *config);
> >
> >  u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit);
> >  void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit);
> > +
> > +static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata)
> > +{
> > +     return drvdata->arch >= ETM_ARCH_ETE;
> > +}
> >  #endif
> > --
> > 2.7.4
> >



-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 05/14] coresight: ete: Add support for ETE tracing
  2021-02-15 13:21     ` Mike Leach
@ 2021-02-15 14:08       ` Mike Leach
  0 siblings, 0 replies; 90+ messages in thread
From: Mike Leach @ 2021-02-15 14:08 UTC (permalink / raw)
  To: Mathieu Poirier
  Cc: Anshuman Khandual, linux-arm-kernel, Coresight ML,
	Suzuki K. Poulose, Linu Cherian, Linux Kernel Mailing List

Reviewed-by: Mike Leach <mike.leach@linaro.org>

On Mon, 15 Feb 2021 at 13:21, Mike Leach <mike.leach@linaro.org> wrote:
>
> HI,
>
> On Tue, 2 Feb 2021 at 18:56, Mathieu Poirier <mathieu.poirier@linaro.org> wrote:
> >
> > On Wed, Jan 27, 2021 at 02:25:29PM +0530, Anshuman Khandual wrote:
> > > From: Suzuki K Poulose <suzuki.poulose@arm.com>
> > >
> > > Add ETE as one of the supported device types we support
> > > with ETM4x driver. The devices are named following the
> > > existing convention as ete<N>.
> > >
> > > ETE mandates that the trace resource status register is programmed
> > > before the tracing is turned on. For the moment simply write to
> > > it indicating TraceActive.
> > >
> > > Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> > > Cc: Mike Leach <mike.leach@linaro.org>
> > > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> > > ---
> > >  drivers/hwtracing/coresight/Kconfig                | 10 ++--
> > >  drivers/hwtracing/coresight/coresight-etm4x-core.c | 56 +++++++++++++++++-----
> > >  .../hwtracing/coresight/coresight-etm4x-sysfs.c    | 19 ++++++--
> > >  drivers/hwtracing/coresight/coresight-etm4x.h      | 16 ++++++-
> > >  4 files changed, 79 insertions(+), 22 deletions(-)
> > >
> > > diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> > > index 7b44ba2..f154ae7 100644
> > > --- a/drivers/hwtracing/coresight/Kconfig
> > > +++ b/drivers/hwtracing/coresight/Kconfig
> > > @@ -97,15 +97,15 @@ config CORESIGHT_SOURCE_ETM3X
> > >         module will be called coresight-etm3x.
> > >
> > >  config CORESIGHT_SOURCE_ETM4X
> > > -     tristate "CoreSight Embedded Trace Macrocell 4.x driver"
> > > +     tristate "CoreSight ETMv4.x / ETE driver"
> > >       depends on ARM64
> > >       select CORESIGHT_LINKS_AND_SINKS
> > >       select PID_IN_CONTEXTIDR
> > >       help
> > > -       This driver provides support for the ETM4.x tracer module, tracing the
> > > -       instructions that a processor is executing. This is primarily useful
> > > -       for instruction level tracing. Depending on the implemented version
> > > -       data tracing may also be available.
> > > +       This driver provides support for the CoreSight Embedded Trace Macrocell
> > > +       version 4.x and the Embedded Trace Extensions (ETE). Both are CPU tracer
> > > +       modules, tracing the instructions that a processor is executing. This is
> > > +       primarily useful for instruction level tracing.
> > >
> > >         To compile this driver as a module, choose M here: the
> > >         module will be called coresight-etm4x.
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > index 9e92d2a..b40e3c2 100644
> > > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > @@ -431,6 +431,13 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > >               etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
> > >       }
> > >
> > > +     /*
> > > +      * ETE mandates that the TRCRSR is written to before
> > > +      * enabling it.
> > > +      */
> > > +     if (etm4x_is_ete(drvdata))
> > > +             etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
> > > +
> > >       /* Enable the trace unit */
> > >       etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
> > >
> > > @@ -864,13 +871,24 @@ static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
> > >        * ETMs implementing sysreg access must implement TRCDEVARCH.
> > >        */
> > >       devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
> > > -     if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH)
> > > +     switch (devarch & ETM_DEVARCH_ID_MASK) {
> > > +     case ETM_DEVARCH_ETMv4x_ARCH:
> > > +             *csa = (struct csdev_access) {
> > > +                     .io_mem = false,
> > > +                     .read   = etm4x_sysreg_read,
> > > +                     .write  = etm4x_sysreg_write,
> > > +             };
> > > +             break;
> > > +     case ETM_DEVARCH_ETE_ARCH:
> > > +             *csa = (struct csdev_access) {
> > > +                     .io_mem = false,
> > > +                     .read   = ete_sysreg_read,
> > > +                     .write  = ete_sysreg_write,
> > > +             };
> > > +             break;
> > > +     default:
> > >               return false;
> > > -     *csa = (struct csdev_access) {
> > > -             .io_mem = false,
> > > -             .read   = etm4x_sysreg_read,
> > > -             .write  = etm4x_sysreg_write,
> > > -     };
> > > +     }
> > >
> > >       drvdata->arch = etm_devarch_to_arch(devarch);
> > >       return true;
> > > @@ -1808,6 +1826,8 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
> > >       struct etmv4_drvdata *drvdata;
> > >       struct coresight_desc desc = { 0 };
> > >       struct etm4_init_arg init_arg = { 0 };
> > > +     u8 major, minor;
> > > +     char *type_name;
> > >
> > >       drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> > >       if (!drvdata)
> > > @@ -1834,10 +1854,6 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
> > >       if (drvdata->cpu < 0)
> > >               return drvdata->cpu;
> > >
> > > -     desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
> > > -     if (!desc.name)
> > > -             return -ENOMEM;
> > > -
> > >       init_arg.drvdata = drvdata;
> > >       init_arg.csa = &desc.access;
> > >       init_arg.pid = etm_pid;
> > > @@ -1853,6 +1869,20 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
> > >       if (!desc.access.io_mem ||
> > >           fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
> > >               drvdata->skip_power_up = true;
> >
> > Add a space here...
> >
> > > +     major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
> > > +     minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
> >
> > And here too.  Othersiwe it makes a big blob in the middle of the function.
> >
> > > +     if (etm4x_is_ete(drvdata)) {
> > > +             type_name = "ete";
> > > +             /* ETE v1 has major version == 5. Adjust this for logging.*/
> > > +             major -= 4;
> >
> > I don't have the documentation for the ETE but I would not adjust @major.  I
> > would simply leave it to what the HW gives us since regardless of the name, the
> > major revision of the IP block is 5.
> >
>
> For consistency this adjustment should be retained. All the prior
> drivers reported the protocol version related to this.
> For ETM3.x this value was 0x2 - logging printed "ETMv3.x", for PTM
> this value was 0x3 - logging printed "PTM 1.x".
> Only for ETMv4 is this value the same as the protocol version.
>
> Mike
>
>
> > > +     } else {
> > > +             type_name = "etm";
> > > +     }
> > > +
> > > +     desc.name = devm_kasprintf(dev, GFP_KERNEL,
> > > +                                "%s%d", type_name, drvdata->cpu);
> > > +     if (!desc.name)
> > > +             return -ENOMEM;
> > >
> > >       etm4_init_trace_id(drvdata);
> > >       etm4_set_default(&drvdata->config);
> > > @@ -1881,9 +1911,8 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
> > >
> > >       etmdrvdata[drvdata->cpu] = drvdata;
> > >
> > > -     dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n",
> > > -              drvdata->cpu, ETM_ARCH_MAJOR_VERSION(drvdata->arch),
> > > -              ETM_ARCH_MINOR_VERSION(drvdata->arch));
> > > +     dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
> > > +              drvdata->cpu, type_name, major, minor);
> > >
> > >       if (boot_enable) {
> > >               coresight_enable(drvdata->csdev);
> > > @@ -2027,6 +2056,7 @@ static struct amba_driver etm4x_amba_driver = {
> > >
> > >  static const struct of_device_id etm4_sysreg_match[] = {
> > >       { .compatible   = "arm,coresight-etm4x-sysreg" },
> > > +     { .compatible   = "arm,embedded-trace-extension" },
> > >       {}
> > >  };
> > >
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > > index b646d53..1c490bc 100644
> > > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > > @@ -2374,12 +2374,20 @@ static inline bool
> > >  etm4x_register_implemented(struct etmv4_drvdata *drvdata, u32 offset)
> > >  {
> > >       switch (offset) {
> > > -     ETM4x_SYSREG_LIST_CASES
> > > +     ETM_COMMON_SYSREG_LIST_CASES
> > >               /*
> > > -              * Registers accessible via system instructions are always
> > > -              * implemented.
> > > +              * Common registers to ETE & ETM4x accessible via system
> > > +              * instructions are always implemented.
> > >                */
> > >               return true;
> > > +
> > > +     ETM4x_ONLY_SYSREG_LIST_CASES
> > > +             /*
> > > +              * We only support etm4x and ete. So if the device is not
> > > +              * ETE, it must be ETMv4x.
> > > +              */
> > > +             return !etm4x_is_ete(drvdata);
> > > +
> > >       ETM4x_MMAP_LIST_CASES
> > >               /*
> > >                * Registers accessible only via memory-mapped registers
> > > @@ -2389,8 +2397,13 @@ etm4x_register_implemented(struct etmv4_drvdata *drvdata, u32 offset)
> > >                * coresight_register() and the csdev is not initialized
> > >                * until that is done. So rely on the drvdata->base to
> > >                * detect if we have a memory mapped access.
> > > +              * Also ETE doesn't implement memory mapped access, thus
> > > +              * it is sufficient to check that we are using mmio.
> > >                */
> > >               return !!drvdata->base;
> > > +
> > > +     ETE_ONLY_SYSREG_LIST_CASES
> > > +             return etm4x_is_ete(drvdata);
> > >       }
> > >
> > >       return false;
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> > > index ca24ac5..8b90de5 100644
> > > --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> > > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> > > @@ -128,6 +128,8 @@
> > >  #define TRCCIDR2                     0xFF8
> > >  #define TRCCIDR3                     0xFFC
> > >
> > > +#define TRCRSR_TA                    BIT(12)
> > > +
> > >  /*
> > >   * System instructions to access ETM registers.
> > >   * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
> > > @@ -390,6 +392,9 @@
> > >  #define ETM_COMMON_SYSREG_LIST_CASES         \
> > >       ETM_COMMON_SYSREG_LIST(NOP, __unused)
> > >
> > > +#define ETM4x_ONLY_SYSREG_LIST_CASES         \
> > > +     ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
> > > +
> > >  #define ETM4x_SYSREG_LIST_CASES                      \
> > >       ETM_COMMON_SYSREG_LIST_CASES            \
> > >       ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
> > > @@ -406,7 +411,6 @@
> > >       ETE_ONLY_SYSREG_LIST(WRITE, (val))
> > >
> > >  #define ETE_ONLY_SYSREG_LIST_CASES           \
> > > -     ETM_COMMON_SYSREG_LIST_CASES            \
> >
> > This goes in patch 04.
> >
> > With the above:
> >
> > Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> >
> > >       ETE_ONLY_SYSREG_LIST(NOP, __unused)
> > >
> > >  #define read_etm4x_sysreg_offset(offset, _64bit)                             \
> > > @@ -589,11 +593,14 @@
> > >       ((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13))
> > >
> > >  #define ETM_DEVARCH_ARCHID_ETMv4x            ETM_DEVARCH_MAKE_ARCHID(0x4)
> > > +#define ETM_DEVARCH_ARCHID_ETE                       ETM_DEVARCH_MAKE_ARCHID(0x5)
> > >
> > >  #define ETM_DEVARCH_ID_MASK                                          \
> > >       (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT)
> > >  #define ETM_DEVARCH_ETMv4x_ARCH                                              \
> > >       (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT)
> > > +#define ETM_DEVARCH_ETE_ARCH                                         \
> > > +     (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT)
> > >
> > >  #define TRCSTATR_IDLE_BIT            0
> > >  #define TRCSTATR_PMSTABLE_BIT                1
> > > @@ -683,6 +690,8 @@
> > >  #define ETM_ARCH_MINOR_VERSION(arch) ((arch) & 0xfU)
> > >
> > >  #define ETM_ARCH_V4  ETM_ARCH_VERSION(4, 0)
> > > +#define ETM_ARCH_ETE ETM_ARCH_VERSION(5, 0)
> > > +
> > >  /* Interpretation of resource numbers change at ETM v4.3 architecture */
> > >  #define ETM_ARCH_V4_3        ETM_ARCH_VERSION(4, 3)
> > >
> > > @@ -989,4 +998,9 @@ void etm4_config_trace_mode(struct etmv4_config *config);
> > >
> > >  u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit);
> > >  void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit);
> > > +
> > > +static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata)
> > > +{
> > > +     return drvdata->arch >= ETM_ARCH_ETE;
> > > +}
> > >  #endif
> > > --
> > > 2.7.4
> > >
>
>
>
> --
> Mike Leach
> Principal Engineer, ARM Ltd.
> Manchester Design Centre. UK



-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock
  2021-01-27  8:55 ` [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
  2021-02-02 17:40   ` Mathieu Poirier
  2021-02-02 18:03   ` Mathieu Poirier
@ 2021-02-15 14:08   ` Mike Leach
  2 siblings, 0 replies; 90+ messages in thread
From: Mike Leach @ 2021-02-15 14:08 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, Coresight ML, Mathieu Poirier,
	Suzuki K. Poulose, Linu Cherian, Linux Kernel Mailing List

Reviewed-by: mike.leach <mike.leach@linaro.org>


On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
<anshuman.khandual@arm.com> wrote:
>
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>
> ETE may not implement the OS lock and instead could rely on
> the PE OS Lock for the trace unit access. This is indicated
> by the TRCOLSR.OSM == 0b100. Add support for handling the
> PE OS lock
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-core.c | 50 ++++++++++++++++++----
>  drivers/hwtracing/coresight/coresight-etm4x.h      | 15 +++++++
>  2 files changed, 56 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 473ab74..9edf8be 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -114,30 +114,59 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
>         }
>  }
>
> -static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa)
> +static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
> +                              struct csdev_access *csa)
>  {
> -       /* Writing 0 to TRCOSLAR unlocks the trace registers */
> -       etm4x_relaxed_write32(csa, 0x0, TRCOSLAR);
> -       drvdata->os_unlock = true;
> +       u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
> +
> +       drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
> +}
> +
> +static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
> +                             struct csdev_access *csa, u32 val)
> +{
> +       val = !!val;
> +
> +       switch (drvdata->os_lock_model) {
> +       case ETM_OSLOCK_PRESENT:
> +               etm4x_relaxed_write32(csa, val, TRCOSLAR);
> +               break;
> +       case ETM_OSLOCK_PE:
> +               write_sysreg_s(val, SYS_OSLAR_EL1);
> +               break;
> +       default:
> +               pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
> +                            smp_processor_id(), drvdata->os_lock_model);
> +               fallthrough;
> +       case ETM_OSLOCK_NI:
> +               return;
> +       }
>         isb();
>  }
>
> +static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
> +                                     struct csdev_access *csa)
> +{
> +       WARN_ON(drvdata->cpu != smp_processor_id());
> +
> +       /* Writing 0 to OS Lock unlocks the trace unit registers */
> +       etm_write_os_lock(drvdata, csa, 0x0);
> +       drvdata->os_unlock = true;
> +}
> +
>  static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
>  {
>         if (!WARN_ON(!drvdata->csdev))
>                 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
> -
>  }
>
>  static void etm4_os_lock(struct etmv4_drvdata *drvdata)
>  {
>         if (WARN_ON(!drvdata->csdev))
>                 return;
> -
> -       /* Writing 0x1 to TRCOSLAR locks the trace registers */
> -       etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR);
> +       /* Writing 0x1 to OS Lock locks the trace registers */
> +       etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
>         drvdata->os_unlock = false;
> -       isb();
>  }
>
>  static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
> @@ -906,6 +935,9 @@ static void etm4_init_arch_data(void *info)
>         if (!etm4_init_csdev_access(drvdata, csa))
>                 return;
>
> +       /* Detect the support for OS Lock before we actuall use it */
> +       etm_detect_os_lock(drvdata, csa);
> +
>         /* Make sure all registers are accessible */
>         etm4_os_unlock_csa(drvdata, csa);
>         etm4_cs_unlock(drvdata, csa);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 0af6057..0e86eba 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -506,6 +506,20 @@
>                                          ETM_MODE_EXCL_USER)
>
>  /*
> + * TRCOSLSR.OSLM advertises the OS Lock model.
> + * OSLM[2:0] = TRCOSLSR[4:3,0]
> + *
> + *     0b000 - Trace OS Lock is not implemented.
> + *     0b010 - Trace OS Lock is implemented.
> + *     0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock.
> + */
> +#define ETM_OSLOCK_NI          0b000
> +#define ETM_OSLOCK_PRESENT     0b010
> +#define ETM_OSLOCK_PE          0b100
> +
> +#define ETM_OSLSR_OSLM(oslsr)  ((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1))
> +
> +/*
>   * TRCDEVARCH Bit field definitions
>   * Bits[31:21] - ARCHITECT = Always Arm Ltd.
>   *                * Bits[31:28] = 0x4
> @@ -897,6 +911,7 @@ struct etmv4_drvdata {
>         u8                              s_ex_level;
>         u8                              ns_ex_level;
>         u8                              q_support;
> +       u8                              os_lock_model;
>         bool                            sticky_enable;
>         bool                            boot_enable;
>         bool                            os_unlock;
> --
> 2.7.4
>


--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access
  2021-01-27  8:55 ` [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access Anshuman Khandual
  2021-02-02 17:52   ` Mathieu Poirier
@ 2021-02-15 14:08   ` Mike Leach
  1 sibling, 0 replies; 90+ messages in thread
From: Mike Leach @ 2021-02-15 14:08 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, Coresight ML, Mathieu Poirier,
	Suzuki K. Poulose, Linu Cherian, Linux Kernel Mailing List

Reviewed-by: Mike Leach <mike.leach@linaro.org>


On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
<anshuman.khandual@arm.com> wrote:
>
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>
> Add support for handling the system registers for Embedded Trace
> Extensions (ETE). ETE shares most of the registers with ETMv4 except
> for some and also adds some new registers. Re-arrange the ETMv4x list
> to share the common definitions and add the ETE sysreg support.
>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-core.c | 32 +++++++++++++
>  drivers/hwtracing/coresight/coresight-etm4x.h      | 52 ++++++++++++++++++----
>  2 files changed, 75 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 9edf8be..9e92d2a 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -114,6 +114,38 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
>         }
>  }
>
> +u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
> +{
> +       u64 res = 0;
> +
> +       switch (offset) {
> +       ETE_READ_CASES(res)
> +       default :
> +               WARN_ONCE(1, "ete: trying to read unsupported register @%x\n",
> +                        offset);
> +       }
> +
> +       if (!_relaxed)
> +               __iormb(res);   /* Imitate the !relaxed I/O helpers */
> +
> +       return res;
> +}
> +
> +void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
> +{
> +       if (!_relaxed)
> +               __iowmb();      /* Imitate the !relaxed I/O helpers */
> +       if (!_64bit)
> +               val &= GENMASK(31, 0);
> +
> +       switch (offset) {
> +       ETE_WRITE_CASES(val)
> +       default :
> +               WARN_ONCE(1, "ete: trying to write to unsupported register @%x\n",
> +                       offset);
> +       }
> +}
> +
>  static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
>                                struct csdev_access *csa)
>  {
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 0e86eba..ca24ac5 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -29,6 +29,7 @@
>  #define TRCAUXCTLR                     0x018
>  #define TRCEVENTCTL0R                  0x020
>  #define TRCEVENTCTL1R                  0x024
> +#define TRCRSR                         0x028
>  #define TRCSTALLCTLR                   0x02C
>  #define TRCTSCTLR                      0x030
>  #define TRCSYNCPR                      0x034
> @@ -49,6 +50,7 @@
>  #define TRCSEQRSTEVR                   0x118
>  #define TRCSEQSTR                      0x11C
>  #define TRCEXTINSELR                   0x120
> +#define TRCEXTINSELRn(n)               (0x120 + (n * 4)) /* n = 0-3 */
>  #define TRCCNTRLDVRn(n)                        (0x140 + (n * 4)) /* n = 0-3 */
>  #define TRCCNTCTLRn(n)                 (0x150 + (n * 4)) /* n = 0-3 */
>  #define TRCCNTVRn(n)                   (0x160 + (n * 4)) /* n = 0-3 */
> @@ -160,10 +162,22 @@
>  #define CASE_NOP(__unused, x)                                  \
>         case (x):       /* fall through */
>
> +#define ETE_ONLY_SYSREG_LIST(op, val)          \
> +       CASE_##op((val), TRCRSR)                \
> +       CASE_##op((val), TRCEXTINSELRn(1))      \
> +       CASE_##op((val), TRCEXTINSELRn(2))      \
> +       CASE_##op((val), TRCEXTINSELRn(3))
> +
>  /* List of registers accessible via System instructions */
> -#define ETM_SYSREG_LIST(op, val)               \
> -       CASE_##op((val), TRCPRGCTLR)            \
> +#define ETM4x_ONLY_SYSREG_LIST(op, val)                \
>         CASE_##op((val), TRCPROCSELR)           \
> +       CASE_##op((val), TRCVDCTLR)             \
> +       CASE_##op((val), TRCVDSACCTLR)          \
> +       CASE_##op((val), TRCVDARCCTLR)          \
> +       CASE_##op((val), TRCOSLAR)
> +
> +#define ETM_COMMON_SYSREG_LIST(op, val)                \
> +       CASE_##op((val), TRCPRGCTLR)            \
>         CASE_##op((val), TRCSTATR)              \
>         CASE_##op((val), TRCCONFIGR)            \
>         CASE_##op((val), TRCAUXCTLR)            \
> @@ -180,9 +194,6 @@
>         CASE_##op((val), TRCVIIECTLR)           \
>         CASE_##op((val), TRCVISSCTLR)           \
>         CASE_##op((val), TRCVIPCSSCTLR)         \
> -       CASE_##op((val), TRCVDCTLR)             \
> -       CASE_##op((val), TRCVDSACCTLR)          \
> -       CASE_##op((val), TRCVDARCCTLR)          \
>         CASE_##op((val), TRCSEQEVRn(0))         \
>         CASE_##op((val), TRCSEQEVRn(1))         \
>         CASE_##op((val), TRCSEQEVRn(2))         \
> @@ -277,7 +288,6 @@
>         CASE_##op((val), TRCSSPCICRn(5))        \
>         CASE_##op((val), TRCSSPCICRn(6))        \
>         CASE_##op((val), TRCSSPCICRn(7))        \
> -       CASE_##op((val), TRCOSLAR)              \
>         CASE_##op((val), TRCOSLSR)              \
>         CASE_##op((val), TRCACVRn(0))           \
>         CASE_##op((val), TRCACVRn(1))           \
> @@ -369,12 +379,36 @@
>         CASE_##op((val), TRCPIDR2)              \
>         CASE_##op((val), TRCPIDR3)
>
> -#define ETM4x_READ_SYSREG_CASES(res)   ETM_SYSREG_LIST(READ, (res))
> -#define ETM4x_WRITE_SYSREG_CASES(val)  ETM_SYSREG_LIST(WRITE, (val))
> +#define ETM4x_READ_SYSREG_CASES(res)           \
> +       ETM_COMMON_SYSREG_LIST(READ, (res))     \
> +       ETM4x_ONLY_SYSREG_LIST(READ, (res))
> +
> +#define ETM4x_WRITE_SYSREG_CASES(val)          \
> +       ETM_COMMON_SYSREG_LIST(WRITE, (val))    \
> +       ETM4x_ONLY_SYSREG_LIST(WRITE, (val))
> +
> +#define ETM_COMMON_SYSREG_LIST_CASES           \
> +       ETM_COMMON_SYSREG_LIST(NOP, __unused)
> +
> +#define ETM4x_SYSREG_LIST_CASES                        \
> +       ETM_COMMON_SYSREG_LIST_CASES            \
> +       ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
>
> -#define ETM4x_SYSREG_LIST_CASES                ETM_SYSREG_LIST(NOP, __unused)
>  #define ETM4x_MMAP_LIST_CASES          ETM_MMAP_LIST(NOP, __unused)
>
> +/* ETE only supports system register access */
> +#define ETE_READ_CASES(res)                    \
> +       ETM_COMMON_SYSREG_LIST(READ, (res))     \
> +       ETE_ONLY_SYSREG_LIST(READ, (res))
> +
> +#define ETE_WRITE_CASES(val)                   \
> +       ETM_COMMON_SYSREG_LIST(WRITE, (val))    \
> +       ETE_ONLY_SYSREG_LIST(WRITE, (val))
> +
> +#define ETE_ONLY_SYSREG_LIST_CASES             \
> +       ETM_COMMON_SYSREG_LIST_CASES            \
> +       ETE_ONLY_SYSREG_LIST(NOP, __unused)
> +
>  #define read_etm4x_sysreg_offset(offset, _64bit)                               \
>         ({                                                                      \
>                 u64 __val;                                                      \
> --
> 2.7.4
>


--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks
  2021-01-27  8:55 ` [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual
  2021-01-28  9:16   ` Suzuki K Poulose
@ 2021-02-15 16:27   ` Mike Leach
  2021-02-15 16:56     ` Mathieu Poirier
  1 sibling, 1 reply; 90+ messages in thread
From: Mike Leach @ 2021-02-15 16:27 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, Coresight ML, Mathieu Poirier,
	Suzuki K. Poulose, Linu Cherian, Linux Kernel Mailing List

HI Anshuman

On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
<anshuman.khandual@arm.com> wrote:
>
> Add support for dedicated sinks that are bound to individual CPUs. (e.g,
> TRBE). To allow quicker access to the sink for a given CPU bound source,
> keep a percpu array of the sink devices. Also, add support for building
> a path to the CPU local sink from the ETM.
>

Really need to tighten up the terminology here - I think what you mean
is a PE architecturally defined sink - i.e. one that can be determined
by reading the feature registers on the PE, rather than an ETR which
cannot.
However, the Coresight Base System Architecture specification does
recommend a per cpu design using an ETR per CPU - now I assume that
this case is not catered for in this patch?

> This adds a new percpu sink type CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM.
> This new sink type is exclusively available and can only work with percpu
> source type device CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC.
>

CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC - this does not exist.

>
> This defines a percpu structure that accommodates a single coresight_device
> which can be used to store an initialized instance from a sink driver. As
> these sinks are exclusively linked and dependent on corresponding percpu
> sources devices, they should also be the default sink device during a perf
> session.
>
> Outwards device connections are scanned while establishing paths between a
> source and a sink device. But such connections are not present for certain
> percpu source and sink devices which are exclusively linked and dependent.
> Build the path directly and skip connection scanning for such devices.
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> Changes in V3:
>
> - Updated coresight_find_default_sink()
>
>  drivers/hwtracing/coresight/coresight-core.c | 16 ++++++++++++++--
>  include/linux/coresight.h                    | 12 ++++++++++++
>  2 files changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index 0062c89..4795e28 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -23,6 +23,7 @@
>  #include "coresight-priv.h"
>
>  static DEFINE_MUTEX(coresight_mutex);
> +DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
>

If you do indeed mean the architecturally defined sinks then this
could be 'csdev_pe_arch_sink' - or something similar to indicate the
reliance on the PE architecture, unless per-cpu ETR topologies are
also handled here.

>  /**
>   * struct coresight_node - elements of a path, from source to sink
> @@ -784,6 +785,13 @@ static int _coresight_build_path(struct coresight_device *csdev,
>         if (csdev == sink)
>                 goto out;
>
> +       if (coresight_is_percpu_source(csdev) && coresight_is_percpu_sink(sink) &&
> +           sink == per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev))) {
> +               _coresight_build_path(sink, sink, path);
> +               found = true;
> +               goto out;
> +       }
> +
>         /* Not a sink - recursively explore each port found on this element */
>         for (i = 0; i < csdev->pdata->nr_outport; i++) {
>                 struct coresight_device *child_dev;
> @@ -999,8 +1007,12 @@ coresight_find_default_sink(struct coresight_device *csdev)
>         int depth = 0;
>
>         /* look for a default sink if we have not found for this device */
> -       if (!csdev->def_sink)
> -               csdev->def_sink = coresight_find_sink(csdev, &depth);
> +       if (!csdev->def_sink) {
> +               if (coresight_is_percpu_source(csdev))
> +                       csdev->def_sink = per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev));
> +               if (!csdev->def_sink)
> +                       csdev->def_sink = coresight_find_sink(csdev, &depth);
> +       }
>         return csdev->def_sink;
>  }
>
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index 976ec26..bc3a5ca 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -50,6 +50,7 @@ enum coresight_dev_subtype_sink {
>         CORESIGHT_DEV_SUBTYPE_SINK_PORT,
>         CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
>         CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
> +       CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,

If this is needed then could it not be ..._SINK_SYSMEM_PROC - to be
consistent with ..._SOURCE_PROC?

>  };
>
>  enum coresight_dev_subtype_link {
> @@ -428,6 +429,17 @@ static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 o
>                 csa->write(val, offset, false, true);
>  }
>
> +static inline bool coresight_is_percpu_source(struct coresight_device *csdev)

All cpu sources are per cpu - that is ETMv3, ETMv4, PTM, ETE - this
might be better as simply coresight_is_cpu_source() as all the
aforementioned types will return true.

> +{
> +       return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
> +              csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
> +}
> +
> +static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
> +{
> +       return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
> +              csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
> +}
>  #else  /* !CONFIG_64BIT */
>
>  static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
> --
> 2.7.4
>

Regards

Mike
-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles
  2021-01-27  8:55 ` [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles Anshuman Khandual
  2021-02-03 19:05   ` Mathieu Poirier
@ 2021-02-15 16:27   ` Mike Leach
  1 sibling, 0 replies; 90+ messages in thread
From: Mike Leach @ 2021-02-15 16:27 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-arm-kernel, Coresight ML, Mathieu Poirier,
	Suzuki K. Poulose, Linu Cherian, Linux Kernel Mailing List,
	Leo Yan

On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
<anshuman.khandual@arm.com> wrote:
>
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>
> The context associated with an ETM for a given perf event
> includes :
>   - handle -> the perf output handle for the AUX buffer.
>   - the path for the trace components
>   - the buffer config for the sink.
>
> The path and the buffer config are part of the "aux_priv" data
> (etm_event_data) setup by the setup_aux() callback, and made available
> via perf_get_aux(handle).
>
> Now with a sink supporting IRQ, the sink could "end" an output
> handle when the buffer reaches the programmed limit and would try
> to restart a handle. This could fail if there is not enough
> space left the AUX buffer (e.g, the userspace has not consumed
> the data). This leaves the "handle" disconnected from the "event"
> and also the "perf_get_aux()" cleared. This all happens within
> the sink driver, without the etm_perf driver being aware.
> Now when the event is actually stopped, etm_event_stop()
> will need to access the "event_data". But since the handle
> is not valid anymore, we loose the information to stop the
> "trace" path. So, we need a reliable way to access the etm_event_data
> even when the handle may not be active.
>
> This patch replaces the per_cpu handle array with a per_cpu context
> for the ETM, which tracks the "handle" as well as the "etm_event_data".
> The context notes the etm_event_data at etm_event_start() and clears
> it at etm_event_stop(). This makes sure that we don't access a
> stale "etm_event_data" as we are guaranteed that it is not
> freed by free_aux() as long as the event is active and tracing,
> also provides us with access to the critical information
> needed to wind up a session even in the absence of an active
> output_handle.
>
> This is not an issue for the legacy sinks as none of them supports
> an IRQ and is centrally handled by the etm-perf.
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
> Cc: Leo Yan <leo.yan@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm-perf.c | 45 +++++++++++++++++++++---
>  1 file changed, 40 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
> index eb9e7e9..a3977b0 100644
> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> @@ -24,7 +24,26 @@
>  static struct pmu etm_pmu;
>  static bool etm_perf_up;
>
> -static DEFINE_PER_CPU(struct perf_output_handle, ctx_handle);
> +/*
> + * An ETM context for a running event includes the perf aux handle
> + * and aux_data. For ETM, the aux_data (etm_event_data), consists of
> + * the trace path and the sink configuration. The event data is accessible
> + * via perf_get_aux(handle). However, a sink could "end" a perf output
> + * handle via the IRQ handler. And if the "sink" encounters a failure
> + * to "begin" another session (e.g due to lack of space in the buffer),
> + * the handle will be cleared. Thus, the event_data may not be accessible
> + * from the handle when we get to the etm_event_stop(), which is required
> + * for stopping the trace path. The event_data is guaranteed to stay alive
> + * until "free_aux()", which cannot happen as long as the event is active on
> + * the ETM. Thus the event_data for the session must be part of the ETM context
> + * to make sure we can disable the trace path.
> + */
> +struct etm_ctxt {
> +       struct perf_output_handle handle;
> +       struct etm_event_data *event_data;
> +};
> +
> +static DEFINE_PER_CPU(struct etm_ctxt, etm_ctxt);
>  static DEFINE_PER_CPU(struct coresight_device *, csdev_src);
>
>  /* ETMv3.5/PTM's ETMCR is 'config' */
> @@ -332,7 +351,8 @@ static void etm_event_start(struct perf_event *event, int flags)
>  {
>         int cpu = smp_processor_id();
>         struct etm_event_data *event_data;
> -       struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle);
> +       struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
> +       struct perf_output_handle *handle = &ctxt->handle;
>         struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
>         struct list_head *path;
>
> @@ -374,6 +394,8 @@ static void etm_event_start(struct perf_event *event, int flags)
>         if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF))
>                 goto fail_disable_path;
>
> +       /* Save the event_data for this ETM */
> +       ctxt->event_data = event_data;
>  out:
>         return;
>
> @@ -392,13 +414,20 @@ static void etm_event_stop(struct perf_event *event, int mode)
>         int cpu = smp_processor_id();
>         unsigned long size;
>         struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
> -       struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle);
> -       struct etm_event_data *event_data = perf_get_aux(handle);
> +       struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
> +       struct perf_output_handle *handle = &ctxt->handle;
> +       struct etm_event_data *event_data = ctxt->event_data;
>         struct list_head *path;
>
> +       /* Clear the event_data as this ETM is stopping the trace. */
> +       ctxt->event_data = NULL;
>         if (event->hw.state == PERF_HES_STOPPED)
>                 return;
>
> +       /* We must have a valid event_data for a running event */
> +       if (WARN_ON(!event_data))
> +               return;
> +
>         if (!csdev)
>                 return;
>
> @@ -416,7 +445,13 @@ static void etm_event_stop(struct perf_event *event, int mode)
>         /* tell the core */
>         event->hw.state = PERF_HES_STOPPED;
>
> -       if (mode & PERF_EF_UPDATE) {
> +       /*
> +        * If the handle is not bound to an event anymore
> +        * (e.g, the sink driver was unable to restart the
> +        * handle due to lack of buffer space), we don't
> +        * have to do anything here.
> +        */
> +       if (handle->event && (mode & PERF_EF_UPDATE)) {
>                 if (WARN_ON_ONCE(handle->event != event))
>                         return;
>
> --
> 2.7.4
>
Reviewed-by: Mike Leach <mike.leach@linaro.org>


--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks
  2021-02-15 16:27   ` Mike Leach
@ 2021-02-15 16:56     ` Mathieu Poirier
  2021-02-15 17:58       ` Mike Leach
  0 siblings, 1 reply; 90+ messages in thread
From: Mathieu Poirier @ 2021-02-15 16:56 UTC (permalink / raw)
  To: Mike Leach
  Cc: Anshuman Khandual, linux-arm-kernel, Coresight ML,
	Suzuki K. Poulose, Linu Cherian, Linux Kernel Mailing List

On Mon, Feb 15, 2021 at 04:27:26PM +0000, Mike Leach wrote:
> HI Anshuman
> 
> On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
> <anshuman.khandual@arm.com> wrote:
> >
> > Add support for dedicated sinks that are bound to individual CPUs. (e.g,
> > TRBE). To allow quicker access to the sink for a given CPU bound source,
> > keep a percpu array of the sink devices. Also, add support for building
> > a path to the CPU local sink from the ETM.
> >
> 
> Really need to tighten up the terminology here - I think what you mean
> is a PE architecturally defined sink - i.e. one that can be determined
> by reading the feature registers on the PE, rather than an ETR which
> cannot.
> However, the Coresight Base System Architecture specification does
> recommend a per cpu design using an ETR per CPU - now I assume that
> this case is not catered for in this patch?
> 
> > This adds a new percpu sink type CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM.
> > This new sink type is exclusively available and can only work with percpu
> > source type device CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC.
> >
> 
> CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC - this does not exist.
> 
> >
> > This defines a percpu structure that accommodates a single coresight_device
> > which can be used to store an initialized instance from a sink driver. As
> > these sinks are exclusively linked and dependent on corresponding percpu
> > sources devices, they should also be the default sink device during a perf
> > session.
> >
> > Outwards device connections are scanned while establishing paths between a
> > source and a sink device. But such connections are not present for certain
> > percpu source and sink devices which are exclusively linked and dependent.
> > Build the path directly and skip connection scanning for such devices.
> >
> > Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Cc: Mike Leach <mike.leach@linaro.org>
> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> > ---
> > Changes in V3:
> >
> > - Updated coresight_find_default_sink()
> >
> >  drivers/hwtracing/coresight/coresight-core.c | 16 ++++++++++++++--
> >  include/linux/coresight.h                    | 12 ++++++++++++
> >  2 files changed, 26 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> > index 0062c89..4795e28 100644
> > --- a/drivers/hwtracing/coresight/coresight-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-core.c
> > @@ -23,6 +23,7 @@
> >  #include "coresight-priv.h"
> >
> >  static DEFINE_MUTEX(coresight_mutex);
> > +DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
> >
> 
> If you do indeed mean the architecturally defined sinks then this
> could be 'csdev_pe_arch_sink' - or something similar to indicate the
> reliance on the PE architecture, unless per-cpu ETR topologies are
> also handled here.

I would like to treat systems with one ETR per CPU the same way we do for TRBEs.
That way we have two distinct way of working, i.e topologies where the sink is
shared and 1:1 topologies.  As such moving forward with "csdev_pe_arch_sink"
could become misleading when 1:1 ETR topologies are supported.

Mathieu

> 
> >  /**
> >   * struct coresight_node - elements of a path, from source to sink
> > @@ -784,6 +785,13 @@ static int _coresight_build_path(struct coresight_device *csdev,
> >         if (csdev == sink)
> >                 goto out;
> >
> > +       if (coresight_is_percpu_source(csdev) && coresight_is_percpu_sink(sink) &&
> > +           sink == per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev))) {
> > +               _coresight_build_path(sink, sink, path);
> > +               found = true;
> > +               goto out;
> > +       }
> > +
> >         /* Not a sink - recursively explore each port found on this element */
> >         for (i = 0; i < csdev->pdata->nr_outport; i++) {
> >                 struct coresight_device *child_dev;
> > @@ -999,8 +1007,12 @@ coresight_find_default_sink(struct coresight_device *csdev)
> >         int depth = 0;
> >
> >         /* look for a default sink if we have not found for this device */
> > -       if (!csdev->def_sink)
> > -               csdev->def_sink = coresight_find_sink(csdev, &depth);
> > +       if (!csdev->def_sink) {
> > +               if (coresight_is_percpu_source(csdev))
> > +                       csdev->def_sink = per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev));
> > +               if (!csdev->def_sink)
> > +                       csdev->def_sink = coresight_find_sink(csdev, &depth);
> > +       }
> >         return csdev->def_sink;
> >  }
> >
> > diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> > index 976ec26..bc3a5ca 100644
> > --- a/include/linux/coresight.h
> > +++ b/include/linux/coresight.h
> > @@ -50,6 +50,7 @@ enum coresight_dev_subtype_sink {
> >         CORESIGHT_DEV_SUBTYPE_SINK_PORT,
> >         CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
> >         CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
> > +       CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
> 
> If this is needed then could it not be ..._SINK_SYSMEM_PROC - to be
> consistent with ..._SOURCE_PROC?
> 
> >  };
> >
> >  enum coresight_dev_subtype_link {
> > @@ -428,6 +429,17 @@ static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 o
> >                 csa->write(val, offset, false, true);
> >  }
> >
> > +static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
> 
> All cpu sources are per cpu - that is ETMv3, ETMv4, PTM, ETE - this
> might be better as simply coresight_is_cpu_source() as all the
> aforementioned types will return true.
> 
> > +{
> > +       return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
> > +              csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
> > +}
> > +
> > +static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
> > +{
> > +       return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
> > +              csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
> > +}
> >  #else  /* !CONFIG_64BIT */
> >
> >  static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
> > --
> > 2.7.4
> >
> 
> Regards
> 
> Mike
> -- 
> Mike Leach
> Principal Engineer, ARM Ltd.
> Manchester Design Centre. UK

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks
  2021-02-15 16:56     ` Mathieu Poirier
@ 2021-02-15 17:58       ` Mike Leach
  2021-02-16 20:30         ` Mathieu Poirier
  0 siblings, 1 reply; 90+ messages in thread
From: Mike Leach @ 2021-02-15 17:58 UTC (permalink / raw)
  To: Mathieu Poirier
  Cc: Anshuman Khandual, linux-arm-kernel, Coresight ML,
	Suzuki K. Poulose, Linu Cherian, Linux Kernel Mailing List

Hi Mathieu,

On Mon, 15 Feb 2021 at 16:56, Mathieu Poirier
<mathieu.poirier@linaro.org> wrote:
>
> On Mon, Feb 15, 2021 at 04:27:26PM +0000, Mike Leach wrote:
> > HI Anshuman
> >
> > On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
> > <anshuman.khandual@arm.com> wrote:
> > >
> > > Add support for dedicated sinks that are bound to individual CPUs. (e.g,
> > > TRBE). To allow quicker access to the sink for a given CPU bound source,
> > > keep a percpu array of the sink devices. Also, add support for building
> > > a path to the CPU local sink from the ETM.
> > >
> >
> > Really need to tighten up the terminology here - I think what you mean
> > is a PE architecturally defined sink - i.e. one that can be determined
> > by reading the feature registers on the PE, rather than an ETR which
> > cannot.
> > However, the Coresight Base System Architecture specification does
> > recommend a per cpu design using an ETR per CPU - now I assume that
> > this case is not catered for in this patch?
> >
> > > This adds a new percpu sink type CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM.
> > > This new sink type is exclusively available and can only work with percpu
> > > source type device CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC.
> > >
> >
> > CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC - this does not exist.
> >
> > >
> > > This defines a percpu structure that accommodates a single coresight_device
> > > which can be used to store an initialized instance from a sink driver. As
> > > these sinks are exclusively linked and dependent on corresponding percpu
> > > sources devices, they should also be the default sink device during a perf
> > > session.
> > >
> > > Outwards device connections are scanned while establishing paths between a
> > > source and a sink device. But such connections are not present for certain
> > > percpu source and sink devices which are exclusively linked and dependent.
> > > Build the path directly and skip connection scanning for such devices.
> > >
> > > Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> > > Cc: Mike Leach <mike.leach@linaro.org>
> > > Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> > > ---
> > > Changes in V3:
> > >
> > > - Updated coresight_find_default_sink()
> > >
> > >  drivers/hwtracing/coresight/coresight-core.c | 16 ++++++++++++++--
> > >  include/linux/coresight.h                    | 12 ++++++++++++
> > >  2 files changed, 26 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> > > index 0062c89..4795e28 100644
> > > --- a/drivers/hwtracing/coresight/coresight-core.c
> > > +++ b/drivers/hwtracing/coresight/coresight-core.c
> > > @@ -23,6 +23,7 @@
> > >  #include "coresight-priv.h"
> > >
> > >  static DEFINE_MUTEX(coresight_mutex);
> > > +DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
> > >
> >
> > If you do indeed mean the architecturally defined sinks then this
> > could be 'csdev_pe_arch_sink' - or something similar to indicate the
> > reliance on the PE architecture, unless per-cpu ETR topologies are
> > also handled here.
>
> I would like to treat systems with one ETR per CPU the same way we do for TRBEs.
> That way we have two distinct way of working, i.e topologies where the sink is
> shared and 1:1 topologies.  As such moving forward with "csdev_pe_arch_sink"
> could become misleading when 1:1 ETR topologies are supported.
>
> Mathieu
>

I believe that In terms of connecting source -> sink for 1:1 ETM:ETR,
then the existing code will already work via the normal build path and
ports declarations. Suzukis changes in coresight-etm-perf to allow
multiple sinks of the same type to be active for ETE:TRBE will also
work for ETx:ETR. (at least in terms of path building - there may
still be other issues that come into play about buffers etc).

The TRBE .dts doesn''t have any ports and is as such outside this
framework. This patch appears to be making it detectable when
connecting source -> sink where we have ETE:TRBE on a given CPU - as
in the subsequent patches, the TRBE driver registers in the per cpu
sink array.

So these changes are not really related to 1:1 specifically, but the
detectability of PE architected sinks. There is a need for the per cpu
array for TRBE as there is no other way of finding them - but not for
ETR - which should work just fine without changes I think.

Regards

Mike


> >
> > >  /**
> > >   * struct coresight_node - elements of a path, from source to sink
> > > @@ -784,6 +785,13 @@ static int _coresight_build_path(struct coresight_device *csdev,
> > >         if (csdev == sink)
> > >                 goto out;
> > >
> > > +       if (coresight_is_percpu_source(csdev) && coresight_is_percpu_sink(sink) &&
> > > +           sink == per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev))) {
> > > +               _coresight_build_path(sink, sink, path);
> > > +               found = true;
> > > +               goto out;
> > > +       }
> > > +
> > >         /* Not a sink - recursively explore each port found on this element */
> > >         for (i = 0; i < csdev->pdata->nr_outport; i++) {
> > >                 struct coresight_device *child_dev;
> > > @@ -999,8 +1007,12 @@ coresight_find_default_sink(struct coresight_device *csdev)
> > >         int depth = 0;
> > >
> > >         /* look for a default sink if we have not found for this device */
> > > -       if (!csdev->def_sink)
> > > -               csdev->def_sink = coresight_find_sink(csdev, &depth);
> > > +       if (!csdev->def_sink) {
> > > +               if (coresight_is_percpu_source(csdev))
> > > +                       csdev->def_sink = per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev));
> > > +               if (!csdev->def_sink)
> > > +                       csdev->def_sink = coresight_find_sink(csdev, &depth);
> > > +       }
> > >         return csdev->def_sink;
> > >  }
> > >
> > > diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> > > index 976ec26..bc3a5ca 100644
> > > --- a/include/linux/coresight.h
> > > +++ b/include/linux/coresight.h
> > > @@ -50,6 +50,7 @@ enum coresight_dev_subtype_sink {
> > >         CORESIGHT_DEV_SUBTYPE_SINK_PORT,
> > >         CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
> > >         CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
> > > +       CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
> >
> > If this is needed then could it not be ..._SINK_SYSMEM_PROC - to be
> > consistent with ..._SOURCE_PROC?
> >
> > >  };
> > >
> > >  enum coresight_dev_subtype_link {
> > > @@ -428,6 +429,17 @@ static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 o
> > >                 csa->write(val, offset, false, true);
> > >  }
> > >
> > > +static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
> >
> > All cpu sources are per cpu - that is ETMv3, ETMv4, PTM, ETE - this
> > might be better as simply coresight_is_cpu_source() as all the
> > aforementioned types will return true.
> >
> > > +{
> > > +       return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
> > > +              csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
> > > +}
> > > +
> > > +static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
> > > +{
> > > +       return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
> > > +              csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM;
> > > +}
> > >  #else  /* !CONFIG_64BIT */
> > >
> > >  static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
> > > --
> > > 2.7.4
> > >
> >
> > Regards
> >
> > Mike
> > --
> > Mike Leach
> > Principal Engineer, ARM Ltd.
> > Manchester Design Centre. UK



--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 09/14] arm64: Add TRBE definitions
  2021-01-28 17:18   ` Catalin Marinas
@ 2021-02-15 18:06     ` Mike Leach
  0 siblings, 0 replies; 90+ messages in thread
From: Mike Leach @ 2021-02-15 18:06 UTC (permalink / raw)
  To: Catalin Marinas
  Cc: Anshuman Khandual, linux-arm-kernel, Coresight ML,
	Mathieu Poirier, Suzuki K. Poulose, Linux Kernel Mailing List,
	Linu Cherian

On Thu, 28 Jan 2021 at 17:18, Catalin Marinas <catalin.marinas@arm.com> wrote:
>
> On Wed, Jan 27, 2021 at 02:25:33PM +0530, Anshuman Khandual wrote:
> > This adds TRBE related registers and corresponding feature macros.
> >
> > Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Cc: Mike Leach <mike.leach@linaro.org>
> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>

Reviewed-by: Mike Leach <mike.leach@linaro.org>



--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-02-15  9:46     ` Anshuman Khandual
@ 2021-02-16  9:00       ` Mike Leach
  2021-02-16  9:44         ` Anshuman Khandual
  2021-02-18  7:50         ` Suzuki K Poulose
  0 siblings, 2 replies; 90+ messages in thread
From: Mike Leach @ 2021-02-16  9:00 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: Mathieu Poirier, linux-arm-kernel, Coresight ML,
	Suzuki K. Poulose, Linu Cherian, Linux Kernel Mailing List

Hi Anshuman,

There have been plenty of detailed comments so I will restrict mine to
a few general issues:-

1) Currently there appears to be no sysfs support (I cannot see the
MODE_SYSFS constants running alongside the MODE_PERF ones present in
the other sink drivers). This is present on all other coresight
devices, and must be provided for this device. It is useful for
testing, and there are users out there who will have scripts to use
it. It is not essential it makes it into this set, but should be a
follow up set.

2) Using FILL mode for TRBE means that the trace will by definition be
lossy. Fill mode will halt collection without cleanly stopping and
flushing the source. This will result in the sink missing the last of
the data from the source as it stops. Even if taking the exception
moves into a prohibited region there is still the possibility the last
trace operations will not be seen. Further it is possible that the
last few bytes of trace will be an incomplete packet, and indeed the
start of the next buffer could contain incomplete packets too.

This operation differs from the other sinks which will only halt after
the sources have stopped and the path has been flushed. This ensures
that the latest trace is complete. The weakness with the older sinks
is the lack of interrupt meaning buffers were frequently wrapped so
that only the latest trace is available.

By using TRBE WRAP mode, with a watermark as described in the TRBE
spec, using the interrupts it is possible to approach lossless trace
in a way that is not possible with earlier ETR/ETB. This is something
that has been requested by partners since trace became available in
linux systems. (There is still a possibility of loss due to filling
the buffer completely and overflowing the watermark, but that can be
flagged).

While FILL mode trace is a good start, and suitable for some scenarios
- WRAP mode needs implementing as well.

3) Padding: To be clear, it is not safe for the decoder to run off the
end of one buffer, into the padding area and continue decoding, or
continue through the padding into the next buffer. However I believe
the buffer start / stop points are demarked by the aux_output_start /
aux_output_end calls?

With upcoming perf decode updates this should enable the decoder to
correctly be started and stopped on the buffer boundaries. The padding
is there primarily to ensure that the decoder does not synchronize
with the data stream until a genuine sync point is found.

4) TRBE needs to be a loadable module like the rest of coresight.

Regards

Mike

On Mon, 15 Feb 2021 at 09:46, Anshuman Khandual
<anshuman.khandual@arm.com> wrote:
>
>
> On 2/13/21 1:56 AM, Mathieu Poirier wrote:
> > On Wed, Jan 27, 2021 at 02:25:35PM +0530, Anshuman Khandual wrote:
> >> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
> >> accessible via the system registers. The TRBE supports different addressing
> >> modes including CPU virtual address and buffer modes including the circular
> >> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
> >> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
> >> access to the trace buffer could be prohibited by a higher exception level
> >> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
> >> private interrupt (PPI) on address translation errors and when the buffer
> >> is full. Overall implementation here is inspired from the Arm SPE driver.
> >>
> >> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> >> Cc: Mike Leach <mike.leach@linaro.org>
> >> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> >> ---
> >> Changes in V3:
> >>
> >> - Added new DT bindings document TRBE.yaml
> >> - Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3
> >> - Dropped isb() from trbe_reset_local()
> >> - Dropped gap between (void *) and buf->trbe_base
> >> - Changed 'int' to 'unsigned int' in is_trbe_available()
> >> - Dropped unused function set_trbe_running(), set_trbe_virtual_mode(),
> >>   set_trbe_enabled() and set_trbe_limit_pointer()
> >> - Changed get_trbe_flag_update(), is_trbe_programmable() and
> >>   get_trbe_address_align() to accept TRBIDR value
> >> - Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), is_trbe_trg(),
> >>   is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value
> >> - Dropped snapshot mode condition in arm_trbe_alloc_buffer()
> >> - Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled
> >> - Compute trbe_limit before trbe_write to get the updated handle
> >> - Added trbe_stop_and_truncate_event()
> >> - Dropped trbe_handle_fatal()
> >>
> >>  Documentation/trace/coresight/coresight-trbe.rst |   39 +
> >>  arch/arm64/include/asm/sysreg.h                  |    1 +
> >>  drivers/hwtracing/coresight/Kconfig              |   11 +
> >>  drivers/hwtracing/coresight/Makefile             |    1 +
> >>  drivers/hwtracing/coresight/coresight-trbe.c     | 1023 ++++++++++++++++++++++
> >>  drivers/hwtracing/coresight/coresight-trbe.h     |  160 ++++
> >>  6 files changed, 1235 insertions(+)
> >>  create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
> >>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
> >>  create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
> >>
> >> diff --git a/Documentation/trace/coresight/coresight-trbe.rst b/Documentation/trace/coresight/coresight-trbe.rst
> >> new file mode 100644
> >> index 0000000..1cbb819
> >> --- /dev/null
> >> +++ b/Documentation/trace/coresight/coresight-trbe.rst
> >> @@ -0,0 +1,39 @@
> >> +.. SPDX-License-Identifier: GPL-2.0
> >> +
> >> +==============================
> >> +Trace Buffer Extension (TRBE).
> >> +==============================
> >> +
> >> +    :Author:   Anshuman Khandual <anshuman.khandual@arm.com>
> >> +    :Date:     November 2020
> >> +
> >> +Hardware Description
> >> +--------------------
> >> +
> >> +Trace Buffer Extension (TRBE) is a percpu hardware which captures in system
> >> +memory, CPU traces generated from a corresponding percpu tracing unit. This
> >> +gets plugged in as a coresight sink device because the corresponding trace
> >> +genarators (ETE), are plugged in as source device.
> >> +
> >> +The TRBE is not compliant to CoreSight architecture specifications, but is
> >> +driven via the CoreSight driver framework to support the ETE (which is
> >> +CoreSight compliant) integration.
> >> +
> >> +Sysfs files and directories
> >> +---------------------------
> >> +
> >> +The TRBE devices appear on the existing coresight bus alongside the other
> >> +coresight devices::
> >> +
> >> +    >$ ls /sys/bus/coresight/devices
> >> +    trbe0  trbe1  trbe2 trbe3
> >> +
> >> +The ``trbe<N>`` named TRBEs are associated with a CPU.::
> >> +
> >> +    >$ ls /sys/bus/coresight/devices/trbe0/
> >> +        align dbm
> >> +
> >> +*Key file items are:-*
> >> +   * ``align``: TRBE write pointer alignment
> >> +   * ``dbm``: TRBE updates memory with access and dirty flags
> >> +
> >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> >> index 85ae4db..9e2e9b7 100644
> >> --- a/arch/arm64/include/asm/sysreg.h
> >> +++ b/arch/arm64/include/asm/sysreg.h
> >> @@ -97,6 +97,7 @@
> >>  #define SET_PSTATE_UAO(x)           __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
> >>  #define SET_PSTATE_SSBS(x)          __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
> >>  #define SET_PSTATE_TCO(x)           __emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
> >> +#define TSB_CSYNC                   __emit_inst(0xd503225f)
> >>
> >>  #define set_pstate_pan(x)           asm volatile(SET_PSTATE_PAN(x))
> >>  #define set_pstate_uao(x)           asm volatile(SET_PSTATE_UAO(x))
> >> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> >> index f154ae7..aa657ab 100644
> >> --- a/drivers/hwtracing/coresight/Kconfig
> >> +++ b/drivers/hwtracing/coresight/Kconfig
> >> @@ -164,6 +164,17 @@ config CORESIGHT_CTI
> >>        To compile this driver as a module, choose M here: the
> >>        module will be called coresight-cti.
> >>
> >> +config CORESIGHT_TRBE
> >> +    bool "Trace Buffer Extension (TRBE) driver"
> >> +    depends on ARM64
> >> +    help
> >> +      This driver provides support for percpu Trace Buffer Extension (TRBE).
> >> +      TRBE always needs to be used along with it's corresponding percpu ETE
> >> +      component. ETE generates trace data which is then captured with TRBE.
> >> +      Unlike traditional sink devices, TRBE is a CPU feature accessible via
> >> +      system registers. But it's explicit dependency with trace unit (ETE)
> >> +      requires it to be plugged in as a coresight sink device.
> >> +
> >>  config CORESIGHT_CTI_INTEGRATION_REGS
> >>      bool "Access CTI CoreSight Integration Registers"
> >>      depends on CORESIGHT_CTI
> >> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
> >> index f20e357..d608165 100644
> >> --- a/drivers/hwtracing/coresight/Makefile
> >> +++ b/drivers/hwtracing/coresight/Makefile
> >> @@ -21,5 +21,6 @@ obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
> >>  obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
> >>  obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
> >>  obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
> >> +obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
> >>  coresight-cti-y := coresight-cti-core.o     coresight-cti-platform.o \
> >>                 coresight-cti-sysfs.o
> >> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> >> new file mode 100644
> >> index 0000000..1464d8b
> >> --- /dev/null
> >> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> >> @@ -0,0 +1,1023 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * This driver enables Trace Buffer Extension (TRBE) as a per-cpu coresight
> >> + * sink device could then pair with an appropriate per-cpu coresight source
> >> + * device (ETE) thus generating required trace data. Trace can be enabled
> >> + * via the perf framework.
> >> + *
> >> + * Copyright (C) 2020 ARM Ltd.
> >> + *
> >> + * Author: Anshuman Khandual <anshuman.khandual@arm.com>
> >> + */
> >> +#define DRVNAME "arm_trbe"
> >> +
> >> +#define pr_fmt(fmt) DRVNAME ": " fmt
> >> +
> >> +#include "coresight-trbe.h"
> >> +
> >> +#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
> >> +
> >> +/*
> >> + * A padding packet that will help the user space tools
> >> + * in skipping relevant sections in the captured trace
> >> + * data which could not be decoded. TRBE doesn't support
> >> + * formatting the trace data, unlike the legacy CoreSight
> >> + * sinks and thus we use ETE trace packets to pad the
> >> + * sections of the buffer.
> >> + */
> >> +#define ETE_IGNORE_PACKET           0x70
> >> +
> >> +/*
> >> + * Minimum amount of meaningful trace will contain:
> >> + * A-Sync, Trace Info, Trace On, Address, Atom.
> >> + * This is about 44bytes of ETE trace. To be on
> >> + * the safer side, we assume 64bytes is the minimum
> >> + * space required for a meaningful session, before
> >> + * we hit a "WRAP" event.
> >> + */
> >> +#define TRBE_TRACE_MIN_BUF_SIZE             64
> >> +
> >> +enum trbe_fault_action {
> >> +    TRBE_FAULT_ACT_WRAP,
> >> +    TRBE_FAULT_ACT_SPURIOUS,
> >> +    TRBE_FAULT_ACT_FATAL,
> >> +};
> >> +
> >> +struct trbe_buf {
> >> +    unsigned long trbe_base;
> >> +    unsigned long trbe_limit;
> >> +    unsigned long trbe_write;
> >> +    int nr_pages;
> >> +    void **pages;
> >> +    bool snapshot;
> >> +    struct trbe_cpudata *cpudata;
> >> +};
> >> +
> >> +struct trbe_cpudata {
> >> +    bool trbe_dbm;
> >> +    u64 trbe_align;
> >> +    int cpu;
> >> +    enum cs_mode mode;
> >> +    struct trbe_buf *buf;
> >> +    struct trbe_drvdata *drvdata;
> >> +};
> >> +
> >> +struct trbe_drvdata {
> >> +    struct trbe_cpudata __percpu *cpudata;
> >> +    struct perf_output_handle __percpu **handle;
> >> +    struct hlist_node hotplug_node;
> >> +    int irq;
> >> +    cpumask_t supported_cpus;
> >> +    enum cpuhp_state trbe_online;
> >> +    struct platform_device *pdev;
> >> +};
> >> +
> >> +static int trbe_alloc_node(struct perf_event *event)
> >> +{
> >> +    if (event->cpu == -1)
> >> +            return NUMA_NO_NODE;
> >> +    return cpu_to_node(event->cpu);
> >> +}
> >> +
> >> +static void trbe_drain_buffer(void)
> >> +{
> >> +    asm(TSB_CSYNC);
> >> +    dsb(nsh);
> >> +}
> >> +
> >> +static void trbe_drain_and_disable_local(void)
> >> +{
> >> +    trbe_drain_buffer();
> >> +    write_sysreg_s(0, SYS_TRBLIMITR_EL1);
> >> +    isb();
> >> +}
> >> +
> >> +static void trbe_reset_local(void)
> >> +{
> >> +    trbe_drain_and_disable_local();
> >> +    write_sysreg_s(0, SYS_TRBPTR_EL1);
> >> +    write_sysreg_s(0, SYS_TRBBASER_EL1);
> >> +    write_sysreg_s(0, SYS_TRBSR_EL1);
> >> +}
> >> +
> >> +static void trbe_stop_and_truncate_event(struct perf_output_handle *handle)
> >> +{
> >> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
> >> +
> >> +    /*
> >> +     * We cannot proceed with the buffer collection and we
> >> +     * do not have any data for the current session. The
> >> +     * etm_perf driver expects to close out the aux_buffer
> >> +     * at event_stop(). So disable the TRBE here and leave
> >> +     * the update_buffer() to return a 0 size.
> >> +     */
> >> +    trbe_drain_and_disable_local();
> >> +    perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> >> +    *this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
> >> +}
> >> +
> >> +/*
> >> + * TRBE Buffer Management
> >> + *
> >> + * The TRBE buffer spans from the base pointer till the limit pointer. When enabled,
> >> + * it starts writing trace data from the write pointer onward till the limit pointer.
> >> + * When the write pointer reaches the address just before the limit pointer, it gets
> >> + * wrapped around again to the base pointer. This is called a TRBE wrap event, which
> >> + * generates a maintenance interrupt when operated in WRAP or FILL mode. This driver
> >> + * uses FILL mode, where the TRBE stops the trace collection at wrap event. The IRQ
> >> + * handler updates the AUX buffer and re-enables the TRBE with updated WRITE and
> >> + * LIMIT pointers.
> >> + *
> >> + *  Wrap around with an IRQ
> >> + *  ------ < ------ < ------- < ----- < -----
> >> + *  |                                       |
> >> + *  ------ > ------ > ------- > ----- > -----
> >> + *
> >> + *  +---------------+-----------------------+
> >> + *  |               |                       |
> >> + *  +---------------+-----------------------+
> >> + *  Base Pointer    Write Pointer           Limit Pointer
> >> + *
> >> + * The base and limit pointers always needs to be PAGE_SIZE aligned. But the write
> >> + * pointer can be aligned to the implementation defined TRBE trace buffer alignment
> >> + * as captured in trbe_cpudata->trbe_align.
> >> + *
> >> + *
> >> + *          head            tail            wakeup
> >> + *  +---------------------------------------+----- ~ ~ ------
> >> + *  |$$$$$$$|################|$$$$$$$$$$$$$$|               |
> >> + *  +---------------------------------------+----- ~ ~ ------
> >> + *  Base Pointer    Write Pointer           Limit Pointer
> >> + *
> >> + * The perf_output_handle indices (head, tail, wakeup) are monotonically increasing
> >> + * values which tracks all the driver writes and user reads from the perf auxiliary
> >> + * buffer. Generally [head..tail] is the area where the driver can write into unless
> >> + * the wakeup is behind the tail. Enabled TRBE buffer span needs to be adjusted and
> >> + * configured depending on the perf_output_handle indices, so that the driver does
> >> + * not override into areas in the perf auxiliary buffer which is being or yet to be
> >> + * consumed from the user space. The enabled TRBE buffer area is a moving subset of
> >> + * the allocated perf auxiliary buffer.
> >> + */
> >> +static void trbe_pad_buf(struct perf_output_handle *handle, int len)
> >> +{
> >> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
> >> +    u64 head = PERF_IDX2OFF(handle->head, buf);
> >> +
> >> +    memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
> >> +    if (!buf->snapshot)
> >> +            perf_aux_output_skip(handle, len);
> >> +}
> >> +
> >> +static unsigned long trbe_snapshot_offset(struct perf_output_handle *handle)
> >> +{
> >> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
> >> +
> >> +    /*
> >> +     * The ETE trace has alignment synchronization packets allowing
> >> +     * the decoder to reset in case of an overflow or corruption.
> >> +     * So we can use the entire buffer for the snapshot mode.
> >> +     */
> >> +    return buf->nr_pages * PAGE_SIZE;
> >> +}
> >> +
> >> +/*
> >> + * TRBE Limit Calculation
> >> + *
> >> + * The following markers are used to illustrate various TRBE buffer situations.
> >> + *
> >> + * $$$$ - Data area, unconsumed captured trace data, not to be overridden
> >> + * #### - Free area, enabled, trace will be written
> >> + * %%%% - Free area, disabled, trace will not be written
> >> + * ==== - Free area, padded with ETE_IGNORE_PACKET, trace will be skipped
> >> + */
> >> +static unsigned long __trbe_normal_offset(struct perf_output_handle *handle)
> >> +{
> >> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
> >> +    struct trbe_cpudata *cpudata = buf->cpudata;
> >> +    const u64 bufsize = buf->nr_pages * PAGE_SIZE;
> >> +    u64 limit = bufsize;
> >> +    u64 head, tail, wakeup;
> >> +
> >> +    head = PERF_IDX2OFF(handle->head, buf);
> >> +
> >> +    /*
> >> +     *              head
> >> +     *      ------->|
> >> +     *      |
> >> +     *      head    TRBE align      tail
> >> +     * +----|-------|---------------|-------+
> >> +     * |$$$$|=======|###############|$$$$$$$|
> >> +     * +----|-------|---------------|-------+
> >> +     * trbe_base                            trbe_base + nr_pages
> >> +     *
> >> +     * Perf aux buffer output head position can be misaligned depending on
> >> +     * various factors including user space reads. In case misaligned, head
> >> +     * needs to be aligned before TRBE can be configured. Pad the alignment
> >> +     * gap with ETE_IGNORE_PACKET bytes that will be ignored by user tools
> >> +     * and skip this section thus advancing the head.
> >> +     */
> >> +    if (!IS_ALIGNED(head, cpudata->trbe_align)) {
> >> +            unsigned long delta = roundup(head, cpudata->trbe_align) - head;
> >> +
> >> +            delta = min(delta, handle->size);
> >> +            trbe_pad_buf(handle, delta);
> >> +            head = PERF_IDX2OFF(handle->head, buf);
> >> +    }
> >> +
> >> +    /*
> >> +     *      head = tail (size = 0)
> >> +     * +----|-------------------------------+
> >> +     * |$$$$|$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ |
> >> +     * +----|-------------------------------+
> >> +     * trbe_base                            trbe_base + nr_pages
> >> +     *
> >> +     * Perf aux buffer does not have any space for the driver to write into.
> >> +     * Just communicate trace truncation event to the user space by marking
> >> +     * it with PERF_AUX_FLAG_TRUNCATED.
> >> +     */
> >> +    if (!handle->size) {
> >> +            perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> >> +            return 0;
> >> +    }
> >> +
> >> +    /* Compute the tail and wakeup indices now that we've aligned head */
> >> +    tail = PERF_IDX2OFF(handle->head + handle->size, buf);
> >> +    wakeup = PERF_IDX2OFF(handle->wakeup, buf);
> >> +
> >> +    /*
> >> +     * Lets calculate the buffer area which TRBE could write into. There
> >> +     * are three possible scenarios here. Limit needs to be aligned with
> >> +     * PAGE_SIZE per the TRBE requirement. Always avoid clobbering the
> >> +     * unconsumed data.
> >> +     *
> >> +     * 1) head < tail
> >> +     *
> >> +     *      head                    tail
> >> +     * +----|-----------------------|-------+
> >> +     * |$$$$|#######################|$$$$$$$|
> >> +     * +----|-----------------------|-------+
> >> +     * trbe_base                    limit   trbe_base + nr_pages
> >> +     *
> >> +     * TRBE could write into [head..tail] area. Unless the tail is right at
> >> +     * the end of the buffer, neither an wrap around nor an IRQ is expected
> >> +     * while being enabled.
> >> +     *
> >> +     * 2) head == tail
> >> +     *
> >> +     *      head = tail (size > 0)
> >> +     * +----|-------------------------------+
> >> +     * |%%%%|###############################|
> >> +     * +----|-------------------------------+
> >> +     * trbe_base                            limit = trbe_base + nr_pages
> >> +     *
> >> +     * TRBE should just write into [head..base + nr_pages] area even though
> >> +     * the entire buffer is empty. Reason being, when the trace reaches the
> >> +     * end of the buffer, it will just wrap around with an IRQ giving an
> >> +     * opportunity to reconfigure the buffer.
> >> +     *
> >> +     * 3) tail < head
> >> +     *
> >> +     *      tail                    head
> >> +     * +----|-----------------------|-------+
> >> +     * |%%%%|$$$$$$$$$$$$$$$$$$$$$$$|#######|
> >> +     * +----|-----------------------|-------+
> >> +     * trbe_base                            limit = trbe_base + nr_pages
> >> +     *
> >> +     * TRBE should just write into [head..base + nr_pages] area even though
> >> +     * the [trbe_base..tail] is also empty. Reason being, when the trace
> >> +     * reaches the end of the buffer, it will just wrap around with an IRQ
> >> +     * giving an opportunity to reconfigure the buffer.
> >> +     */
> >> +    if (head < tail)
> >> +            limit = round_down(tail, PAGE_SIZE);
> >> +
> >> +    /*
> >> +     * Wakeup may be arbitrarily far into the future. If it's not in the
> >> +     * current generation, either we'll wrap before hitting it, or it's
> >> +     * in the past and has been handled already.
> >> +     *
> >> +     * If there's a wakeup before we wrap, arrange to be woken up by the
> >> +     * page boundary following it. Keep the tail boundary if that's lower.
> >> +     *
> >> +     *      head            wakeup  tail
> >> +     * +----|---------------|-------|-------+
> >> +     * |$$$$|###############|%%%%%%%|$$$$$$$|
> >> +     * +----|---------------|-------|-------+
> >> +     * trbe_base            limit           trbe_base + nr_pages
> >> +     */
> >> +    if (handle->wakeup < (handle->head + handle->size) && head <= wakeup)
> >> +            limit = min(limit, round_up(wakeup, PAGE_SIZE));
> >> +
> >> +    /*
> >> +     * There are two situation when this can happen i.e limit is before
> >> +     * the head and hence TRBE cannot be configured.
> >> +     *
> >> +     * 1) head < tail (aligned down with PAGE_SIZE) and also they are both
> >> +     * within the same PAGE size range.
> >> +     *
> >> +     *                      PAGE_SIZE
> >> +     *              |----------------------|
> >> +     *
> >> +     *              limit   head    tail
> >> +     * +------------|------|--------|-------+
> >> +     * |$$$$$$$$$$$$$$$$$$$|========|$$$$$$$|
> >> +     * +------------|------|--------|-------+
> >> +     * trbe_base                            trbe_base + nr_pages
> >> +     *
> >> +     * 2) head < wakeup (aligned up with PAGE_SIZE) < tail and also both
> >> +     * head and wakeup are within same PAGE size range.
> >> +     *
> >> +     *              PAGE_SIZE
> >> +     *      |----------------------|
> >> +     *
> >> +     *      limit   head    wakeup  tail
> >> +     * +----|------|-------|--------|-------+
> >> +     * |$$$$$$$$$$$|=======|========|$$$$$$$|
> >> +     * +----|------|-------|--------|-------+
> >> +     * trbe_base                            trbe_base + nr_pages
> >> +     */
> >> +    if (limit > head)
> >> +            return limit;
> >> +
> >> +    trbe_pad_buf(handle, handle->size);
> >> +    perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
> >> +    return 0;
> >> +}
> >> +
> >> +static unsigned long trbe_normal_offset(struct perf_output_handle *handle)
> >> +{
> >> +    struct trbe_buf *buf = perf_get_aux(handle);
> >> +    u64 limit = __trbe_normal_offset(handle);
> >> +    u64 head = PERF_IDX2OFF(handle->head, buf);
> >> +
> >> +    /*
> >> +     * If the head is too close to the limit and we don't
> >> +     * have space for a meaningful run, we rather pad it
> >> +     * and start fresh.
> >> +     */
> >> +    if (limit && (limit - head < TRBE_TRACE_MIN_BUF_SIZE)) {
> >> +            trbe_pad_buf(handle, limit - head);
> >> +            limit = __trbe_normal_offset(handle);
> >> +    }
> >> +    return limit;
> >> +}
> >> +
> >> +static unsigned long compute_trbe_buffer_limit(struct perf_output_handle *handle)
> >> +{
> >> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
> >> +    unsigned long offset;
> >> +
> >> +    if (buf->snapshot)
> >> +            offset = trbe_snapshot_offset(handle);
> >> +    else
> >> +            offset = trbe_normal_offset(handle);
> >> +    return buf->trbe_base + offset;
> >> +}
> >
> > I won't review the trace buffer management functions in this revision, I will
> > leave that for the next version.
>
> Okay.
>
> >
> >> +
> >> +static void clr_trbe_status(void)
> >> +{
> >> +    u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
> >> +
> >> +    WARN_ON(is_trbe_enabled());
> >> +    trbsr &= ~TRBSR_IRQ;
> >> +    trbsr &= ~TRBSR_TRG;
> >> +    trbsr &= ~TRBSR_WRAP;
> >> +    trbsr &= ~(TRBSR_EC_MASK << TRBSR_EC_SHIFT);
> >> +    trbsr &= ~(TRBSR_BSC_MASK << TRBSR_BSC_SHIFT);
> >> +    trbsr &= ~TRBSR_STOP;
> >> +    write_sysreg_s(trbsr, SYS_TRBSR_EL1);
> >> +}
> >
> > I haven't read the TRBE progammer's manual but looking a the documentation the above
> > looks good.
> >
> >> +
> >> +static void set_trbe_limit_pointer_enabled(unsigned long addr)
> >> +{
> >> +    u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
> >> +
> >> +    WARN_ON(!IS_ALIGNED(addr, (1UL << TRBLIMITR_LIMIT_SHIFT)));
> >> +    WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
> >> +
> >> +    trblimitr &= ~TRBLIMITR_NVM;
> >> +    trblimitr &= ~(TRBLIMITR_FILL_MODE_MASK << TRBLIMITR_FILL_MODE_SHIFT);
> >> +    trblimitr &= ~(TRBLIMITR_TRIG_MODE_MASK << TRBLIMITR_TRIG_MODE_SHIFT);
> >> +    trblimitr &= ~(TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT);
> >> +
> >> +    /*
> >> +     * Fill trace buffer mode is used here while configuring the
> >> +     * TRBE for trace capture. In this particular mode, the trace
> >> +     * collection is stopped and a maintenance interrupt is raised
> >> +     * when the current write pointer wraps. This pause in trace
> >> +     * collection gives the software an opportunity to capture the
> >> +     * trace data in the interrupt handler, before reconfiguring
> >> +     * the TRBE.
> >> +     */
> >> +    trblimitr |= (TRBE_FILL_MODE_FILL & TRBLIMITR_FILL_MODE_MASK) << TRBLIMITR_FILL_MODE_SHIFT;
> >> +
> >> +    /*
> >> +     * Trigger mode is not used here while configuring the TRBE for
> >> +     * the trace capture. Hence just keep this in the ignore mode.
> >> +     */
> >> +    trblimitr |= (TRBE_TRIG_MODE_IGNORE & TRBLIMITR_TRIG_MODE_MASK) << TRBLIMITR_TRIG_MODE_SHIFT;
> >> +    trblimitr |= (addr & PAGE_MASK);
> >> +
> >> +    trblimitr |= TRBLIMITR_ENABLE;
> >> +    write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
> >> +}
> >
> > Same here
> >
> >> +
> >> +static void trbe_enable_hw(struct trbe_buf *buf)
> >> +{
> >> +    WARN_ON(buf->trbe_write < buf->trbe_base);
> >> +    WARN_ON(buf->trbe_write >= buf->trbe_limit);
> >> +    set_trbe_disabled();
> >> +    isb();
> >> +    clr_trbe_status();
> >> +    set_trbe_base_pointer(buf->trbe_base);
> >> +    set_trbe_write_pointer(buf->trbe_write);
> >> +
> >> +    /*
> >> +     * Synchronize all the register updates
> >> +     * till now before enabling the TRBE.
> >> +     */
> >> +    isb();
> >> +    set_trbe_limit_pointer_enabled(buf->trbe_limit);
> >> +
> >> +    /* Synchronize the TRBE enable event */
> >> +    isb();
> >> +}
> >
> > Ok
> >
> >> +
> >> +static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
> >> +                               struct perf_event *event, void **pages,
> >> +                               int nr_pages, bool snapshot)
> >> +{
> >> +    struct trbe_buf *buf;
> >> +    struct page **pglist;
> >> +    int i;
> >> +
> >> +    /*
> >> +     * TRBE LIMIT and TRBE WRITE pointers must be page aligned. But with
> >> +     * just a single page, there is not much room left while writing into
> >> +     * a partially filled TRBE buffer. Hence restrict the minimum buffer
> >> +     * size as two pages.
> >> +     */
> >> +    if (nr_pages < 2)
> >> +            return NULL;
> >> +
> >> +    buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
> >> +    if (IS_ERR(buf))
> >> +            return ERR_PTR(-ENOMEM);
> >
> > You know what do to.
>
> Right, will check for NULL instead and return ERR_PTR(-ENOMEM) as
> the function return type is (void *).
>
> >
> >> +
> >> +    pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
> >> +    if (IS_ERR(pglist)) {
> >> +            kfree(buf);
> >> +            return ERR_PTR(-ENOMEM);
> >> +    }
> >
> > Here too.
>
> Yes, changed.
>
> >
> >> +
> >> +    for (i = 0; i < nr_pages; i++)
> >> +            pglist[i] = virt_to_page(pages[i]);
> >> +
> >> +    buf->trbe_base = (unsigned long) vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
> >> +    if (IS_ERR((void *)buf->trbe_base)) {
> >> +            kfree(pglist);
> >> +            kfree(buf);
> >> +            return ERR_PTR(buf->trbe_base);
> >> +    }
> >
> > Here too.
>
> Yes, changed.
>
> >
> >> +    buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
> >> +    buf->trbe_write = buf->trbe_base;
> >> +    buf->snapshot = snapshot;
> >> +    buf->nr_pages = nr_pages;
> >> +    buf->pages = pages;
> >> +    kfree(pglist);
> >> +    return buf;
> >> +}
> >> +
> >> +void arm_trbe_free_buffer(void *config)
>
> Added the missing 'static' here.
>
> >> +{
> >> +    struct trbe_buf *buf = config;
> >> +
> >> +    vunmap((void *)buf->trbe_base);
> >> +    kfree(buf);
> >> +}
> >
> > Ok
> >
> >> +
> >> +static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
> >> +                                        struct perf_output_handle *handle,
> >> +                                        void *config)
> >> +{
> >> +    struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> >> +    struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> >> +    struct trbe_buf *buf = config;
> >> +    unsigned long size, offset;
> >> +
> >> +    WARN_ON(buf->cpudata != cpudata);
> >> +    WARN_ON(cpudata->cpu != smp_processor_id());
> >> +    WARN_ON(cpudata->drvdata != drvdata);
> >> +    if (cpudata->mode != CS_MODE_PERF)
> >> +            return -EINVAL;
> >> +
> >> +    /*
> >> +     * If the TRBE was disabled due to lack of space in the AUX buffer or a
> >> +     * spurious fault, the driver leaves it disabled, truncating the buffer.
> >> +     * Since the etm_perf driver expects to close out the AUX buffer, the
> >> +     * driver skips it. Thus, just pass in 0 size here to indicate that the
> >> +     * buffer was truncated.
> >> +     */
> >> +    if (!is_trbe_enabled())
> >> +            return 0;
> >> +    /*
> >> +     * perf handle structure needs to be shared with the TRBE IRQ handler for
> >> +     * capturing trace data and restarting the handle. There is a probability
> >> +     * of an undefined reference based crash when etm event is being stopped
> >> +     * while a TRBE IRQ also getting processed. This happens due the release
> >> +     * of perf handle via perf_aux_output_end() in etm_event_stop(). Stopping
> >> +     * the TRBE here will ensure that no IRQ could be generated when the perf
> >> +     * handle gets freed in etm_event_stop().
> >> +     */
> >> +    trbe_drain_and_disable_local();
> >> +    offset = get_trbe_write_pointer() - get_trbe_base_pointer();
> >> +    size = offset - PERF_IDX2OFF(handle->head, buf);
> >> +    if (buf->snapshot)
> >> +            handle->head += size;
> >> +    return size;
> >> +}
> >
> > Ok - I really appreciate the comments.
> >
> >> +
> >> +static int arm_trbe_enable(struct coresight_device *csdev, u32 mode, void *data)
> >> +{
> >> +    struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> >> +    struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> >> +    struct perf_output_handle *handle = data;
> >> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
> >> +
> >> +    WARN_ON(cpudata->cpu != smp_processor_id());
> >> +    WARN_ON(cpudata->drvdata != drvdata);
> >> +    if (mode != CS_MODE_PERF)
> >> +            return -EINVAL;
> >> +
> >> +    *this_cpu_ptr(drvdata->handle) = handle;
> >> +    cpudata->buf = buf;
> >> +    cpudata->mode = mode;
> >> +    buf->cpudata = cpudata;
> >> +    buf->trbe_limit = compute_trbe_buffer_limit(handle);
> >> +    buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> >> +    if (buf->trbe_limit == buf->trbe_base) {
> >> +            trbe_stop_and_truncate_event(handle);
> >> +            return 0;
> >> +    }
> >> +    trbe_enable_hw(buf);
> >> +    return 0;
> >> +}
> >
> > Ok
> >
> >> +
> >> +static int arm_trbe_disable(struct coresight_device *csdev)
> >> +{
> >> +    struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> >> +    struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> >> +    struct trbe_buf *buf = cpudata->buf;
> >> +
> >> +    WARN_ON(buf->cpudata != cpudata);
> >> +    WARN_ON(cpudata->cpu != smp_processor_id());
> >> +    WARN_ON(cpudata->drvdata != drvdata);
> >> +    if (cpudata->mode != CS_MODE_PERF)
> >> +            return -EINVAL;
> >> +
> >> +    trbe_drain_and_disable_local();
> >> +    buf->cpudata = NULL;
> >> +    cpudata->buf = NULL;
> >> +    cpudata->mode = CS_MODE_DISABLED;
> >> +    return 0;
> >> +}
> >
> > Ok
> >
> >> +
> >> +static void trbe_handle_spurious(struct perf_output_handle *handle)
> >> +{
> >> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
> >> +
> >> +    buf->trbe_limit = compute_trbe_buffer_limit(handle);
> >> +    buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> >> +    if (buf->trbe_limit == buf->trbe_base) {
> >> +            trbe_drain_and_disable_local();
> >> +            return;
> >> +    }
> >> +    trbe_enable_hw(buf);
> >> +}
> >> +
> >> +static void trbe_handle_overflow(struct perf_output_handle *handle)
> >> +{
> >> +    struct perf_event *event = handle->event;
> >> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
> >> +    unsigned long offset, size;
> >> +    struct etm_event_data *event_data;
> >> +
> >> +    offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
> >> +    size = offset - PERF_IDX2OFF(handle->head, buf);
> >> +    if (buf->snapshot)
> >> +            handle->head = offset;
> >> +    perf_aux_output_end(handle, size);
> >> +
> >> +    event_data = perf_aux_output_begin(handle, event);
> >> +    if (!event_data) {
> >> +            trbe_drain_and_disable_local();
> >> +            *this_cpu_ptr(buf->cpudata->drvdata->handle) = NULL;
> >> +            return;
> >> +    }
> >> +    buf->trbe_limit = compute_trbe_buffer_limit(handle);
> >> +    buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> >> +    if (buf->trbe_limit == buf->trbe_base) {
> >> +            trbe_stop_and_truncate_event(handle);
> >> +            return;
> >> +    }
> >> +    *this_cpu_ptr(buf->cpudata->drvdata->handle) = handle;
> >> +    trbe_enable_hw(buf);
> >> +}
> >> +
> >> +static bool is_perf_trbe(struct perf_output_handle *handle)
> >> +{
> >> +    struct trbe_buf *buf = etm_perf_sink_config(handle);
> >> +    struct trbe_cpudata *cpudata = buf->cpudata;
> >> +    struct trbe_drvdata *drvdata = cpudata->drvdata;
> >> +    int cpu = smp_processor_id();
> >> +
> >> +    WARN_ON(buf->trbe_base != get_trbe_base_pointer());
> >> +    WARN_ON(buf->trbe_limit != get_trbe_limit_pointer());
> >> +
> >> +    if (cpudata->mode != CS_MODE_PERF)
> >> +            return false;
> >> +
> >> +    if (cpudata->cpu != cpu)
> >> +            return false;
> >> +
> >> +    if (!cpumask_test_cpu(cpu, &drvdata->supported_cpus))
> >> +            return false;
> >> +
> >> +    return true;
> >> +}
> >> +
> >> +static enum trbe_fault_action trbe_get_fault_act(struct perf_output_handle *handle)
> >
> > @handle isn't used for anything.
>
> Okay, will drop.
>
> >
> >> +{
> >> +    u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
> >> +    int ec = get_trbe_ec(trbsr);
> >> +    int bsc = get_trbe_bsc(trbsr);
> >> +
> >> +    WARN_ON(is_trbe_running(trbsr));
> >> +    if (is_trbe_trg(trbsr) || is_trbe_abort(trbsr))
> >> +            return TRBE_FAULT_ACT_FATAL;
> >> +
> >> +    if ((ec == TRBE_EC_STAGE1_ABORT) || (ec == TRBE_EC_STAGE2_ABORT))
> >> +            return TRBE_FAULT_ACT_FATAL;
> >> +
> >> +    if (is_trbe_wrap(trbsr) && (ec == TRBE_EC_OTHERS) && (bsc == TRBE_BSC_FILLED)) {
> >> +            if (get_trbe_write_pointer() == get_trbe_base_pointer())
> >> +                    return TRBE_FAULT_ACT_WRAP;
> >> +    }
> >> +    return TRBE_FAULT_ACT_SPURIOUS;
> >> +}
> >> +
> >> +static irqreturn_t arm_trbe_irq_handler(int irq, void *dev)
> >> +{
> >> +    struct perf_output_handle **handle_ptr = dev;
> >> +    struct perf_output_handle *handle = *handle_ptr;
> >> +    enum trbe_fault_action act;
> >> +
> >> +    WARN_ON(!is_trbe_irq(read_sysreg_s(SYS_TRBSR_EL1)));
> >> +    clr_trbe_irq();
> >> +
> >> +    /*
> >> +     * Ensure the trace is visible to the CPUs and
> >> +     * any external aborts have been resolved.
> >> +     */
> >> +    trbe_drain_buffer();
> >> +    isb();
> >> +
> >> +    if (!perf_get_aux(handle))
> >> +            return IRQ_NONE;
> >> +
> >> +    if (!is_perf_trbe(handle))
> >> +            return IRQ_NONE;
> >> +
> >> +    irq_work_run();
> >
> > I trust Will that this is the right thing to do.
> >
> > I will stop here for this revision.  I will dive more in the mechanic of the
> > TRBE on the next revision.
>
> Okay, will collate all the changes till now and respin sooner.
>
> - Anshuman



-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
  2021-02-16  9:00       ` Mike Leach
@ 2021-02-16  9:44         ` Anshuman Khandual
  2021-02-16 12:12           ` Mike Leach
  2021-02-18  7:50         ` Suzuki K Poulose
  1 sibling, 1 reply; 90+ messages in thread
From: Anshuman Khandual @ 2021-02-16  9:44 UTC (permalink / raw)
  To: Mike Leach
  Cc: Mathieu Poirier, linux-arm-kernel, Coresight ML,
	Suzuki K. Poulose, Linu Cherian, Linux Kernel Mailing List

Hello Mike,

On 2/16/21 2:30 PM, Mike Leach wrote:
> Hi Anshuman,
> 
> There have been plenty of detailed comments so I will restrict mine to
> a few general issues:-
> 
> 1) Currently there appears to be no sysfs support (I cannot see the
> MODE_SYSFS constants running alongside the MODE_PERF ones present in
> the other sink drivers). This is present on all other coresight
> devices, and must be provided for this device. It is useful for
> testing, and there are users out there who will have scripts to use
> it. It is not essential it makes it into this set, but should be a
> follow up set.

Sure, will try and add it in a follow up series.

> 
> 2) Using FILL mode for TRBE means that the trace will by definition be
> lossy. Fill mode will halt collection without cleanly stopping and
> flushing the source. This will result in the sink missing the last of
> the data from the source as it stops. Even if taking the exception
> moves into a prohibited region there is still the possibility the last
> trace operations will not be seen. Further it is possible that the
> last few bytes of trace will be an incomplete packet, and indeed the
> start of the next buffer could contain incomplete packets too.

Just wondering why TRBE and ETE would not sync with each other in order
for the ETE to possibly resend all the lost trace data, when the TRBE
runs out of buffer and wrappers around ? Is this ETE/TRBE behavior same
for all implementations in the FILL mode ? Just wondering.

> 
> This operation differs from the other sinks which will only halt after
> the sources have stopped and the path has been flushed. This ensures
> that the latest trace is complete. The weakness with the older sinks
> is the lack of interrupt meaning buffers were frequently wrapped so
> that only the latest trace is available.

Right.

> 
> By using TRBE WRAP mode, with a watermark as described in the TRBE
> spec, using the interrupts it is possible to approach lossless trace
> in a way that is not possible with earlier ETR/ETB. This is somethin
Using TRBTRG_EL1 as the above mentioned watermark ?

> that has been requested by partners since trace became available in
> linux systems. (There is still a possibility of loss due to filling
> the buffer completely and overflowing the watermark, but that can be
> flagged).
> 
> While FILL mode trace is a good start, and suitable for some scenarios
> - WRAP mode needs implementing as well.

I would like to understand this mechanism more. Besides how the perf
interface suppose to choose between FILL and WRAP mode ? via a new
event attribute ?

> 
> 3) Padding: To be clear, it is not safe for the decoder to run off the
> end of one buffer, into the padding area and continue decoding, or
> continue through the padding into the next buffer. However I believe
> the buffer start / stop points are demarked by the aux_output_start /
> aux_output_end calls?

Yes.

> 
> With upcoming perf decode updates this should enable the decoder to
> correctly be started and stopped on the buffer boundaries. The padding
> is there primarily to ensure that the decoder does not synchronize
> with the data stream until a genuine sync point is found.

Right.

> 
> 4) TRBE needs to be a loadable module like the rest of coresight.

Even though the driver has all the module constructs, the Kconfig was
missing a tristate value, which is being fixed for the next version.

- Anshuman

^ permalink raw reply	[flat|nested] 90+ messages in thread

* Re: [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks
  2021-01-28  9:16   ` Suzuki K Poulose
  2021-02-04 18:34     ` Mathieu Poirier
@ 2021-02-16 10:21     ` Anshuman Khandual