From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
To: sboyd@kernel.org, agross@kernel.org, bjorn.andersson@linaro.org,
david.brown@linaro.org, devicetree@vger.kernel.org,
jassisinghbrar@gmail.com, linux-arm-msm@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-remoteproc@vger.kernel.org, mark.rutland@arm.com,
mturquette@baylibre.com, ohad@wizery.com, robh+dt@kernel.org,
sricharan@codeaurora.org, gokulsri@codeaurora.org
Subject: [PATCH v8 2/9] remoteproc: qcom: Add secure PIL support
Date: Sat, 30 Jan 2021 10:50:06 +0530 [thread overview]
Message-ID: <1611984013-10201-3-git-send-email-gokulsri@codeaurora.org> (raw)
In-Reply-To: <1611984013-10201-1-git-send-email-gokulsri@codeaurora.org>
IPQ8074 uses secure PIL. Hence, adding the support for the same.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 43 ++++++++++++++++++++++++++++++++++---
1 file changed, 40 insertions(+), 3 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
index c0368bb..4e35e5c 100644
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -18,6 +18,7 @@
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/soc/qcom/mdt_loader.h>
+#include <linux/qcom_scm.h>
#include "qcom_common.h"
#include "qcom_pil_info.h"
#include "qcom_q6v5.h"
@@ -86,6 +87,9 @@
#define TCSR_WCSS_CLK_ENABLE 0x14
#define MAX_HALT_REG 3
+
+#define WCNSS_PAS_ID 6
+
enum {
WCSS_IPQ8074,
WCSS_QCS404,
@@ -134,6 +138,7 @@ struct q6v5_wcss {
unsigned int crash_reason_smem;
u32 version;
bool requires_force_stop;
+ bool need_mem_protection;
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_ssr ssr_subdev;
@@ -152,6 +157,7 @@ struct wcss_data {
int ssctl_id;
const struct rproc_ops *ops;
bool requires_force_stop;
+ bool need_mem_protection;
};
static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
@@ -251,6 +257,15 @@ static int q6v5_wcss_start(struct rproc *rproc)
qcom_q6v5_prepare(&wcss->q6v5);
+ if (wcss->need_mem_protection) {
+ ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
+ if (ret) {
+ dev_err(wcss->dev, "wcss_reset failed\n");
+ return ret;
+ }
+ goto wait_for_reset;
+ }
+
/* Release Q6 and WCSS reset */
ret = reset_control_deassert(wcss->wcss_reset);
if (ret) {
@@ -285,6 +300,7 @@ static int q6v5_wcss_start(struct rproc *rproc)
if (ret)
goto wcss_q6_reset;
+wait_for_reset:
ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
if (ret == -ETIMEDOUT)
dev_err(wcss->dev, "start timed out\n");
@@ -717,6 +733,15 @@ static int q6v5_wcss_stop(struct rproc *rproc)
struct q6v5_wcss *wcss = rproc->priv;
int ret;
+ if (wcss->need_mem_protection) {
+ ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
+ if (ret) {
+ dev_err(wcss->dev, "not able to shutdown\n");
+ return ret;
+ }
+ goto pas_done;
+ }
+
/* WCSS powerdown */
if (wcss->requires_force_stop) {
ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
@@ -741,6 +766,7 @@ static int q6v5_wcss_stop(struct rproc *rproc)
return ret;
}
+pas_done:
clk_disable_unprepare(wcss->prng_clk);
qcom_q6v5_unprepare(&wcss->q6v5);
@@ -764,9 +790,15 @@ static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
struct q6v5_wcss *wcss = rproc->priv;
int ret;
- ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
- 0, wcss->mem_region, wcss->mem_phys,
- wcss->mem_size, &wcss->mem_reloc);
+ if (wcss->need_mem_protection)
+ ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
+ WCNSS_PAS_ID, wcss->mem_region,
+ wcss->mem_phys, wcss->mem_size,
+ &wcss->mem_reloc);
+ else
+ ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
+ 0, wcss->mem_region, wcss->mem_phys,
+ wcss->mem_size, &wcss->mem_reloc);
if (ret)
return ret;
@@ -1032,6 +1064,9 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
if (!desc)
return -EINVAL;
+ if (desc->need_mem_protection && !qcom_scm_is_available())
+ return -EPROBE_DEFER;
+
rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
desc->firmware_name, sizeof(*wcss));
if (!rproc) {
@@ -1045,6 +1080,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
wcss->version = desc->version;
wcss->requires_force_stop = desc->requires_force_stop;
+ wcss->need_mem_protection = desc->need_mem_protection;
ret = q6v5_wcss_init_mmio(wcss, pdev);
if (ret)
@@ -1115,6 +1151,7 @@ static const struct wcss_data wcss_ipq8074_res_init = {
.wcss_q6_reset_required = true,
.ops = &q6v5_wcss_ipq8074_ops,
.requires_force_stop = true,
+ .need_mem_protection = true,
};
static const struct wcss_data wcss_qcs404_res_init = {
--
2.7.4
next prev parent reply other threads:[~2021-01-30 5:30 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-30 5:20 [PATCH v8 0/9] remoteproc: qcom: q6v5-wcss: Add support for secure pil Gokul Sriram Palanisamy
2021-01-30 5:20 ` [PATCH v8 1/9] remoteproc: qcom: Add PRNG proxy clock Gokul Sriram Palanisamy
2021-01-30 5:20 ` Gokul Sriram Palanisamy [this message]
2021-03-18 2:05 ` [PATCH v8 2/9] remoteproc: qcom: Add secure PIL support Bjorn Andersson
2021-01-30 5:20 ` [PATCH v8 3/9] remoteproc: qcom: Add support for split q6 + m3 wlan firmware Gokul Sriram Palanisamy
2021-01-30 5:20 ` [PATCH v8 4/9] remoteproc: qcom: Add ssr subdevice identifier Gokul Sriram Palanisamy
2021-01-30 5:20 ` [PATCH v8 5/9] remoteproc: qcom: Update regmap offsets for halt register Gokul Sriram Palanisamy
2021-01-30 5:20 ` [PATCH v8 6/9] dt-bindings: clock: qcom: Add reset for WCSSAON Gokul Sriram Palanisamy
2021-01-30 5:20 ` [PATCH v8 7/9] clk: qcom: Add WCSSAON reset Gokul Sriram Palanisamy
2021-01-30 5:20 ` [PATCH v8 8/9] arm64: dts: Add support for scm on IPQ8074 SoCs Gokul Sriram Palanisamy
2021-01-30 5:20 ` [PATCH v8 9/9] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC Gokul Sriram Palanisamy
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