From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99D17C4332D for ; Mon, 8 Feb 2021 17:59:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 579F764EE9 for ; Mon, 8 Feb 2021 17:59:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235063AbhBHR7W (ORCPT ); Mon, 8 Feb 2021 12:59:22 -0500 Received: from mga14.intel.com ([192.55.52.115]:62780 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233954AbhBHPfK (ORCPT ); Mon, 8 Feb 2021 10:35:10 -0500 IronPort-SDR: WZFArjgOFuLw1mgb/cEaIDwnmBj/miZTKPrSC3s/c368lHXQguGlf7+7Ja4X3nup+PBnM+BlRm itjQgsQ4hM/g== X-IronPort-AV: E=McAfee;i="6000,8403,9889"; a="180951909" X-IronPort-AV: E=Sophos;i="5.81,162,1610438400"; d="scan'208";a="180951909" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2021 07:30:04 -0800 IronPort-SDR: M0glvaKOjAT7iu+uQKwqZ8I9BjUrFnZPGWLoe+mZTiPAXC9gCAg5T4bBtPIvKKIpTQKexk/j/s oe9bzWJULnfg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,162,1610438400"; d="scan'208";a="358820555" Received: from otc-lr-04.jf.intel.com ([10.54.39.41]) by orsmga003.jf.intel.com with ESMTP; 08 Feb 2021 07:30:03 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, acme@kernel.org, mingo@kernel.org, linux-kernel@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, namhyung@kernel.org, jolsa@redhat.com, ak@linux.intel.com, yao.jin@linux.intel.com, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, Kan Liang Subject: [PATCH 06/49] perf/x86: Hybrid PMU support for unconstrained Date: Mon, 8 Feb 2021 07:25:03 -0800 Message-Id: <1612797946-18784-7-git-send-email-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1612797946-18784-1-git-send-email-kan.liang@linux.intel.com> References: <1612797946-18784-1-git-send-email-kan.liang@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kan Liang The unconstrained value depends on the number of GP and fixed counters. Each hybrid PMU should use its own unconstrained. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/events/intel/core.c | 5 ++++- arch/x86/events/perf_event.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 3b8d728..9baa6b6 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3147,7 +3147,10 @@ x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, } } - return &unconstrained; + if (!HAS_VALID_HYBRID_PMU_IN_CPUC(cpuc)) + return &unconstrained; + + return &x86_pmu.hybrid_pmu[cpuc->hybrid_pmu_idx].unconstrained; } static struct event_constraint * diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index bda4bdc..f11dbc4 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -651,6 +651,7 @@ struct x86_hybrid_pmu { int max_pebs_events; int num_counters; int num_counters_fixed; + struct event_constraint unconstrained; }; #define IS_X86_HYBRID cpu_feature_enabled(X86_FEATURE_HYBRID_CPU) -- 2.7.4