linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Stephen Boyd <swboyd@chromium.org>
To: Rajendra Nayak <rnayak@codeaurora.org>,
	agross@kernel.org, bjorn.andersson@linaro.org,
	robh+dt@kernel.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, Maulik Shah <mkshah@codeaurora.org>,
	Rajendra Nayak <rnayak@codeaurora.org>
Subject: Re: [PATCH 05/13] arm64: dts: qcom: sc7280: Add RSC and PDC devices
Date: Mon, 22 Feb 2021 23:41:07 -0800	[thread overview]
Message-ID: <161406606714.1254594.8318028410661523068@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <1613114930-1661-6-git-send-email-rnayak@codeaurora.org>

Quoting Rajendra Nayak (2021-02-11 23:28:42)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 1fe2eba..7848e88 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -7,6 +7,7 @@
>  
>  #include <dt-bindings/clock/qcom,gcc-sc7280.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
>  
>  / {
>         interrupt-parent = <&intc>;
> @@ -30,6 +31,18 @@
>                 };
>         };
>  
> +       reserved_memory: reserved-memory {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               aop_cmd_db_mem: memory@80860000 {
> +                       reg = <0x0 0x80860000 0x0 0x20000>;
> +                       compatible = "qcom,cmd-db";
> +                       no-map;
> +               };
> +       };
> +
>         cpus {
>                 #address-cells = <2>;
>                 #size-cells = <0>;
> @@ -189,6 +202,19 @@
>                         };
>                 };
>  
> +               pdc: interrupt-controller@b220000 {
> +                       compatible = "qcom,sc7280-pdc", "qcom,pdc";
> +                       reg = <0 0xb220000 0 0x30000>;

Can you pad out reg to 8 digits? 0x0b220000

> +                       qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
> +                                         <55 306 4>, <59 312 3>, <62 374 2>,
> +                                         <64 434 2>, <66 438 3>, <69 86 1>,
> +                                         <70 520 54>, <124 609 31>, <155 63 1>,
> +                                         <156 716 12>;
> +                       #interrupt-cells = <2>;
> +                       interrupt-parent = <&intc>;
> +                       interrupt-controller;
> +               };
> +
>                 tlmm: pinctrl@f100000 {
>                         compatible = "qcom,sc7280-pinctrl";
>                         reg = <0 0xf100000 0 0x1000000>;

The same applies to the previous patch. Sorry for missing that.

> @@ -198,6 +224,7 @@
>                         interrupt-controller;
>                         #interrupt-cells = <2>;
>                         gpio-ranges = <&tlmm 0 0 175>;
> +                       wakeup-parent = <&pdc>;
>  
>                         qup_uart5_default: qup-uart5-default {
>                                 pins = "gpio46", "gpio47";
> @@ -282,6 +309,23 @@
>                                 status = "disabled";
>                         };
>                 };
> +
> +               apps_rsc: rsc@18200000 {
> +                       compatible = "qcom,rpmh-rsc";
> +                       reg = <0 0x18200000 0 0x10000>,
> +                             <0 0x18210000 0 0x10000>,
> +                             <0 0x18220000 0 0x10000>;
> +                       reg-names = "drv-0", "drv-1", "drv-2";
> +                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +                       qcom,tcs-offset = <0xd00>;
> +                       qcom,drv-id = <2>;
> +                       qcom,tcs-config = <ACTIVE_TCS  2>,
> +                                         <SLEEP_TCS   3>,
> +                                         <WAKE_TCS    3>,
> +                                         <CONTROL_TCS 1>;
> +               };
>         };

  reply	other threads:[~2021-02-23  7:42 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-12  7:28 [PATCH 00/13] Add binding updates and DT files for SC7280 SoC Rajendra Nayak
2021-02-12  7:28 ` [PATCH 01/13] dt-bindings: arm: qcom: Document SC7280 SoC and board Rajendra Nayak
2021-02-23  7:49   ` Stephen Boyd
2021-03-05 20:08   ` Rob Herring
2021-02-12  7:28 ` [PATCH 02/13] dt-bindings: firmware: scm: Add SC7280 support Rajendra Nayak
2021-02-23  7:50   ` Stephen Boyd
2021-03-05 20:08   ` Rob Herring
2021-02-12  7:28 ` [PATCH 03/13] arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc Rajendra Nayak
2021-02-12 20:00   ` kernel test robot
2021-02-23  7:37   ` Stephen Boyd
2021-02-23 11:42     ` Rajendra Nayak
2021-02-12  7:28 ` [PATCH 04/13] dt-bindings: qcom,pdc: Add compatible for sc7280 Rajendra Nayak
2021-02-23  7:38   ` Stephen Boyd
2021-02-23  7:39   ` Stephen Boyd
2021-03-05  5:46     ` Rajendra Nayak
2021-02-12  7:28 ` [PATCH 05/13] arm64: dts: qcom: sc7280: Add RSC and PDC devices Rajendra Nayak
2021-02-23  7:41   ` Stephen Boyd [this message]
2021-02-12  7:28 ` [PATCH 06/13] arm64: dts: qcom: SC7280: Add rpmhcc clock controller node Rajendra Nayak
2021-02-23  7:43   ` Stephen Boyd
2021-03-01 17:27     ` Taniya Das
2021-03-03  8:21       ` Stephen Boyd
2021-02-12  7:28 ` [PATCH 07/13] dt-bindings: arm-smmu: Add compatible for SC7280 SoC Rajendra Nayak
2021-02-23  7:43   ` Stephen Boyd
2021-02-12  7:28 ` [PATCH 08/13] arm64: dts: qcom: sc7280: Add device node for APPS SMMU Rajendra Nayak
2021-02-12  7:28 ` [PATCH 09/13] arm64: dts: qcom: Add reserved memory for fw Rajendra Nayak
2021-02-23  7:45   ` Stephen Boyd
2021-02-23 11:45     ` Rajendra Nayak
2021-02-12  7:28 ` [PATCH 10/13] dt-bindings: watchdog: Add compatible for SC7280 SoC Rajendra Nayak
2021-02-23  7:45   ` Stephen Boyd
2021-02-12  7:28 ` [PATCH 11/13] arm64: dts: qcom: sc7280: Add APSS watchdog node Rajendra Nayak
2021-02-23  7:46   ` Stephen Boyd
2021-02-12  7:28 ` [PATCH 12/13] arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280 Rajendra Nayak
2021-02-12  7:28 ` [PATCH 13/13] arm64: dts: qcom: sc7280: Add cpuidle states Rajendra Nayak
2021-02-23  7:49   ` Stephen Boyd
2021-02-23 11:50     ` Maulik Shah
2021-03-11  0:13 ` [PATCH 00/13] Add binding updates and DT files for SC7280 SoC Bjorn Andersson
2021-03-11  9:15   ` Rajendra Nayak
2021-03-11 11:35     ` Rajendra Nayak
2021-03-11 16:44     ` Bjorn Andersson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=161406606714.1254594.8318028410661523068@swboyd.mtv.corp.google.com \
    --to=swboyd@chromium.org \
    --cc=agross@kernel.org \
    --cc=bjorn.andersson@linaro.org \
    --cc=devicetree@vger.kernel.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mkshah@codeaurora.org \
    --cc=rnayak@codeaurora.org \
    --cc=robh+dt@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).