[PATCH 0/8] ARM: STM32: add art-pi(stm32h750xbh6) board support

[PATCH 0/8] ARM: STM32: add art-pi(stm32h750xbh6) board support

[dillon.minfei]

From: dillon min <dillon.minfei@gmail.com>

This patchset intend to add art-pi board support, this board developed
by rt-thread(https://www.rt-thread.org/).

Board resources:

8MiB QSPI flash
16MiB SPI flash
32MiB SDRAM
AP6212 wifi,bt,fm comb

sw context:
- as stm32h750 just has 128k bytes internal flash, so running a fw on
  internal flash to download u-boot/kernel to qspi flash, boot
  u-boot/kernel from qspi flash. this fw is based on rt-thread.
- kernel can be xip on qspi flash or load to sdram
- root filesystem is jffs2(created by buildroot), stored on spi flash

to support the boad, add following changes.
- fix r0-r3, r12 register restore failed after svc call, 
- add dts binding
- update yaml doc

dillon min (8):
  ARM: ARMv7-M: Fix register restore corrupt after svc call
  Documentation: arm: stm32: Add stm32h750 value line
  dt-bindings: arm: stm32: Add compatible strings for ART-PI board
  dt-bindings: pinctrl: stm32: Add stm32h750 pinctrl
  ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h75x
  ARM: dts: stm32: add stm32h750-pinctrl.dtsi
  ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6
  ARM: stm32: add initial support for stm32h750

 Documentation/arm/index.rst                        |   1 +
 Documentation/arm/stm32/stm32h750-overview.rst     |  33 ++
 .../devicetree/bindings/arm/stm32/stm32.yaml       |   4 +
 .../bindings/pinctrl/st,stm32-pinctrl.yaml         |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/stm32h7-pinctrl.dtsi             | 392 +++++++++++++++++++++
 arch/arm/boot/dts/stm32h743-pinctrl.dtsi           | 307 +---------------
 arch/arm/boot/dts/stm32h743.dtsi                   |  30 ++
 arch/arm/boot/dts/stm32h750-pinctrl.dtsi           |  11 +
 arch/arm/boot/dts/stm32h750.dtsi                   |   5 +
 arch/arm/boot/dts/stm32h750i-art-pi.dts            | 227 ++++++++++++
 arch/arm/mach-stm32/board-dt.c                     |   1 +
 arch/arm/mm/proc-v7m.S                             |   5 +-
 13 files changed, 716 insertions(+), 302 deletions(-)
 create mode 100644 Documentation/arm/stm32/stm32h750-overview.rst
 create mode 100644 arch/arm/boot/dts/stm32h7-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/stm32h750-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/stm32h750.dtsi
 create mode 100644 arch/arm/boot/dts/stm32h750i-art-pi.dts

-- 
2.7.4

[PATCH 1/8] ARM: ARMv7-M: Fix register restore corrupt after svc call

[dillon.minfei]

From: dillon min <dillon.minfei@gmail.com>

For some case, kernel not boot by u-boot(single thread),
but by rtos , as most rtos use pendsv to do context switch.

So, we need add an lr check after svc call, to find out should
use psp or msp. else register restore after svc call might be
corrupted.

Fixes: b70cd406d7fe ("ARM: 8671/1: V7M: Preserve registers across switch from Thread to Handler mode")
Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 arch/arm/mm/proc-v7m.S | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
index 84459c1d31b8..c93d2757312d 100644
--- a/arch/arm/mm/proc-v7m.S
+++ b/arch/arm/mm/proc-v7m.S
@@ -137,7 +137,10 @@ __v7m_setup_cont:
 1:	cpsid	i
 	/* Calculate exc_ret */
 	orr	r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK
-	ldmia	sp, {r0-r3, r12}
+	tst	lr, #EXC_RET_STACK_MASK
+	mrsne	r4, psp
+	moveq	r4, sp
+	ldmia	r4!, {r0-r3, r12}
 	str	r5, [r12, #11 * 4]	@ restore the original SVC vector entry
 	mov	lr, r6			@ restore LR
 
-- 
2.7.4

[PATCH 2/8] Documentation: arm: stm32: Add stm32h750 value line

[dillon.minfei]

From: dillon min <dillon.minfei@gmail.com>

detail information can be found at:
https://www.st.com/en/microcontrollers-microprocessors/stm32h750-value-line.html

Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 Documentation/arm/index.rst                    |  1 +
 Documentation/arm/stm32/stm32h750-overview.rst | 33 ++++++++++++++++++++++++++
 2 files changed, 34 insertions(+)
 create mode 100644 Documentation/arm/stm32/stm32h750-overview.rst

diff --git a/Documentation/arm/index.rst b/Documentation/arm/index.rst
index b4bea32472b6..d4f34ae9e6f4 100644
--- a/Documentation/arm/index.rst
+++ b/Documentation/arm/index.rst
@@ -52,6 +52,7 @@ SoC-specific documents
    stm32/stm32f746-overview
    stm32/overview
    stm32/stm32h743-overview
+   stm32/stm32h750-overview
    stm32/stm32f769-overview
    stm32/stm32f429-overview
    stm32/stm32mp157-overview
diff --git a/Documentation/arm/stm32/stm32h750-overview.rst b/Documentation/arm/stm32/stm32h750-overview.rst
new file mode 100644
index 000000000000..c8ce59ec3bd1
--- /dev/null
+++ b/Documentation/arm/stm32/stm32h750-overview.rst
@@ -0,0 +1,33 @@
+==================
+STM32H750 Overview
+==================
+
+Introduction
+------------
+
+The STM32H750 is a Cortex-M7 MCU aimed at various applications.
+It features:
+
+- Cortex-M7 core running up to @480MHz
+- 128K internal flash, 1MBytes internal RAM
+- FMC controller to connect SDRAM, NOR and NAND memories
+- Dual mode QSPI
+- SD/MMC/SDIO support
+- Ethernet controller
+- USB OTFG FS & HS controllers
+- I2C, SPI, CAN busses support
+- Several 16 & 32 bits general purpose timers
+- Serial Audio interface
+- LCD controller
+- HDMI-CEC
+- SPDIFRX
+- DFSDM
+
+Resources
+---------
+
+Datasheet and reference manual are publicly available on ST website (STM32H750_).
+
+.. _STM32H750: https://www.st.com/en/microcontrollers-microprocessors/stm32h750-value-line.html
+
+:Authors: Dillon Min <dillon.minfei@gmail.com>
-- 
2.7.4

[PATCH 3/8] dt-bindings: arm: stm32: Add compatible strings for ART-PI board

[dillon.minfei]

From: dillon min <dillon.minfei@gmail.com>

Art-pi based on stm32h750xbh6, with following resources:

-8MiB QSPI flash
-16MiB SPI flash
-32MiB SDRAM
-AP6212 wifi, bt, fm

detail information can be found at:
https://art-pi.gitee.io/website/

Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index e7525a3395e5..306e7551ad39 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -53,6 +53,10 @@ properties:
           - const: st,stm32h743
       - items:
           - enum:
+              - st,stm32h750i-art-pi
+          - const: st,stm32h750
+      - items:
+          - enum:
               - shiratech,stm32mp157a-iot-box # IoT Box
               - shiratech,stm32mp157a-stinger96 # Stinger96
               - st,stm32mp157c-ed1
-- 
2.7.4

[PATCH 4/8] dt-bindings: pinctrl: stm32: Add stm32h750 pinctrl

[dillon.minfei]

From: dillon min <dillon.minfei@gmail.com>

Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
index 72877544ca78..59f33cbe8f48 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
@@ -24,6 +24,7 @@ properties:
       - st,stm32f746-pinctrl
       - st,stm32f769-pinctrl
       - st,stm32h743-pinctrl
+      - st,stm32h750-pinctrl
       - st,stm32mp157-pinctrl
       - st,stm32mp157-z-pinctrl
 
-- 
2.7.4

[PATCH 5/8] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h75x

[dillon.minfei]

From: dillon min <dillon.minfei@gmail.com>

To support stm32h750 and stm32h743, we need a base stm32h7-pinctrl.dtsi
as stm32h743 & h750 has almost the same interface. so, just rename
stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi

Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 arch/arm/boot/dts/stm32h7-pinctrl.dtsi   | 392 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 307 +-----------------------
 2 files changed, 398 insertions(+), 301 deletions(-)
 create mode 100644 arch/arm/boot/dts/stm32h7-pinctrl.dtsi

diff --git a/arch/arm/boot/dts/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi
new file mode 100644
index 000000000000..7d4b5d683ccc
--- /dev/null
+++ b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi
@@ -0,0 +1,392 @@
+/*
+ * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x58020000 0x3000>;
+			interrupt-parent = <&exti>;
+			st,syscfg = <&syscfg 0x8>;
+			pins-are-numbered;
+
+			gpioa: gpio@58020000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x0 0x400>;
+				clocks = <&rcc GPIOA_CK>;
+				st,bank-name = "GPIOA";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiob: gpio@58020400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x400 0x400>;
+				clocks = <&rcc GPIOB_CK>;
+				st,bank-name = "GPIOB";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpioc: gpio@58020800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x800 0x400>;
+				clocks = <&rcc GPIOC_CK>;
+				st,bank-name = "GPIOC";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiod: gpio@58020c00 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0xc00 0x400>;
+				clocks = <&rcc GPIOD_CK>;
+				st,bank-name = "GPIOD";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpioe: gpio@58021000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x1000 0x400>;
+				clocks = <&rcc GPIOE_CK>;
+				st,bank-name = "GPIOE";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiof: gpio@58021400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x1400 0x400>;
+				clocks = <&rcc GPIOF_CK>;
+				st,bank-name = "GPIOF";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiog: gpio@58021800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x1800 0x400>;
+				clocks = <&rcc GPIOG_CK>;
+				st,bank-name = "GPIOG";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpioh: gpio@58021c00 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x1c00 0x400>;
+				clocks = <&rcc GPIOH_CK>;
+				st,bank-name = "GPIOH";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpioi: gpio@58022000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x2000 0x400>;
+				clocks = <&rcc GPIOI_CK>;
+				st,bank-name = "GPIOI";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpioj: gpio@58022400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x2400 0x400>;
+				clocks = <&rcc GPIOJ_CK>;
+				st,bank-name = "GPIOJ";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpiok: gpio@58022800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x2800 0x400>;
+				clocks = <&rcc GPIOK_CK>;
+				st,bank-name = "GPIOK";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			i2c1_pins_a: i2c1-0 {
+				pins {
+					pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
+						 <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
+					bias-disable;
+					drive-open-drain;
+					slew-rate = <0>;
+				};
+			};
+
+			ethernet_rmii: rmii-0 {
+				pins {
+					pinmux = <STM32_PINMUX('G', 11, AF11)>,
+						 <STM32_PINMUX('G', 13, AF11)>,
+						 <STM32_PINMUX('G', 12, AF11)>,
+						 <STM32_PINMUX('C', 4, AF11)>,
+						 <STM32_PINMUX('C', 5, AF11)>,
+						 <STM32_PINMUX('A', 7, AF11)>,
+						 <STM32_PINMUX('C', 1, AF11)>,
+						 <STM32_PINMUX('A', 2, AF11)>,
+						 <STM32_PINMUX('A', 1, AF11)>;
+					slew-rate = <2>;
+				};
+			};
+
+			sdmmc1_b4_pins_a: sdmmc1-b4-0 {
+				pins {
+					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+						 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
+						 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+					slew-rate = <3>;
+					drive-push-pull;
+					bias-disable;
+				};
+			};
+
+			sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+						 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+					slew-rate = <3>;
+					drive-push-pull;
+					bias-disable;
+				};
+				pins2{
+					pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+					slew-rate = <3>;
+					drive-open-drain;
+					bias-disable;
+				};
+			};
+
+			sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
+				pins {
+					pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+						 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+						 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+						 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+						 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+						 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+				};
+			};
+
+			sdmmc2_b4_pins_a: sdmmc2-b4-0 {
+				pins {
+					pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */
+						 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
+						 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
+						 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
+						 <STM32_PINMUX('D', 6, AF11)>, /* SDMMC1_CK */
+						 <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
+					slew-rate = <3>;
+					drive-push-pull;
+					bias-disable;
+				};
+			};
+
+			sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+						 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
+						 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
+						 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
+						 <STM32_PINMUX('D', 6, AF11)>; /* SDMMC1_CK */
+					slew-rate = <3>;
+					drive-push-pull;
+					bias-disable;
+				};
+				pins2{
+					pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
+					slew-rate = <3>;
+					drive-open-drain;
+					bias-disable;
+				};
+			};
+
+			sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
+				pins {
+					pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC1_D0 */
+						 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC1_D1 */
+						 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC1_D2 */
+						 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC1_D3 */
+						 <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC1_CK */
+						 <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC1_CMD */
+				};
+			};
+
+			sdmmc1_dir_pins_a: sdmmc1-dir-0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
+						 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
+						 <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
+					slew-rate = <3>;
+					drive-push-pull;
+					bias-pull-up;
+				};
+				pins2{
+					pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
+					bias-pull-up;
+				};
+			};
+
+			sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
+				pins {
+					pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
+						 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
+						 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
+						 <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
+				};
+			};
+
+			usart1_pins: usart1-0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <0>;
+				};
+				pins2 {
+					pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
+					bias-disable;
+				};
+			};
+
+			usart2_pins: usart2-0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <0>;
+				};
+				pins2 {
+					pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
+					bias-disable;
+				};
+			};
+
+			usart3_pins: usart3-0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <0>;
+				};
+				pins2 {
+					pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
+					bias-disable;
+				};
+			};
+
+			uart4_pins: uart4-0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <0>;
+				};
+				pins2 {
+					pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */
+					bias-disable;
+				};
+			};
+
+			usbotg_hs_pins_a: usbotg-hs-0 {
+				pins {
+					pinmux = <STM32_PINMUX('H', 4, AF10)>,	/* ULPI_NXT */
+							 <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
+							 <STM32_PINMUX('C', 0, AF10)>,	/* ULPI_STP> */
+							 <STM32_PINMUX('A', 5, AF10)>,	/* ULPI_CK> */
+							 <STM32_PINMUX('A', 3, AF10)>,	/* ULPI_D0> */
+							 <STM32_PINMUX('B', 0, AF10)>,	/* ULPI_D1> */
+							 <STM32_PINMUX('B', 1, AF10)>,	/* ULPI_D2> */
+							 <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
+							 <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
+							 <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
+							 <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
+							 <STM32_PINMUX('B', 5, AF10)>;	/* ULPI_D7> */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			spi1_pins: spi1-0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('A', 5, AF5)>,
+						/* SPI1_CLK */
+						 <STM32_PINMUX('B', 5, AF5)>;
+						/* SPI1_MOSI */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+				pins2 {
+					pinmux = <STM32_PINMUX('G', 9, AF5)>;
+						/* SPI1_MISO */
+					bias-disable;
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
index fa5dcb6a5fdd..6b1e115307b9 100644
--- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -1,306 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 /*
- * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
  */
 
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+#include "stm32h7-pinctrl.dtsi"
 
-/ {
-	soc {
-		pin-controller {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "st,stm32h743-pinctrl";
-			ranges = <0 0x58020000 0x3000>;
-			interrupt-parent = <&exti>;
-			st,syscfg = <&syscfg 0x8>;
-			pins-are-numbered;
-
-			gpioa: gpio@58020000 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				reg = <0x0 0x400>;
-				clocks = <&rcc GPIOA_CK>;
-				st,bank-name = "GPIOA";
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-
-			gpiob: gpio@58020400 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				reg = <0x400 0x400>;
-				clocks = <&rcc GPIOB_CK>;
-				st,bank-name = "GPIOB";
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-
-			gpioc: gpio@58020800 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				reg = <0x800 0x400>;
-				clocks = <&rcc GPIOC_CK>;
-				st,bank-name = "GPIOC";
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-
-			gpiod: gpio@58020c00 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				reg = <0xc00 0x400>;
-				clocks = <&rcc GPIOD_CK>;
-				st,bank-name = "GPIOD";
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-
-			gpioe: gpio@58021000 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				reg = <0x1000 0x400>;
-				clocks = <&rcc GPIOE_CK>;
-				st,bank-name = "GPIOE";
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-
-			gpiof: gpio@58021400 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				reg = <0x1400 0x400>;
-				clocks = <&rcc GPIOF_CK>;
-				st,bank-name = "GPIOF";
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-
-			gpiog: gpio@58021800 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				reg = <0x1800 0x400>;
-				clocks = <&rcc GPIOG_CK>;
-				st,bank-name = "GPIOG";
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-
-			gpioh: gpio@58021c00 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				reg = <0x1c00 0x400>;
-				clocks = <&rcc GPIOH_CK>;
-				st,bank-name = "GPIOH";
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-
-			gpioi: gpio@58022000 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				reg = <0x2000 0x400>;
-				clocks = <&rcc GPIOI_CK>;
-				st,bank-name = "GPIOI";
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-
-			gpioj: gpio@58022400 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				reg = <0x2400 0x400>;
-				clocks = <&rcc GPIOJ_CK>;
-				st,bank-name = "GPIOJ";
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-
-			gpiok: gpio@58022800 {
-				gpio-controller;
-				#gpio-cells = <2>;
-				reg = <0x2800 0x400>;
-				clocks = <&rcc GPIOK_CK>;
-				st,bank-name = "GPIOK";
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-
-			i2c1_pins_a: i2c1-0 {
-				pins {
-					pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
-						 <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
-					bias-disable;
-					drive-open-drain;
-					slew-rate = <0>;
-				};
-			};
-
-			ethernet_rmii: rmii-0 {
-				pins {
-					pinmux = <STM32_PINMUX('G', 11, AF11)>,
-						 <STM32_PINMUX('G', 13, AF11)>,
-						 <STM32_PINMUX('G', 12, AF11)>,
-						 <STM32_PINMUX('C', 4, AF11)>,
-						 <STM32_PINMUX('C', 5, AF11)>,
-						 <STM32_PINMUX('A', 7, AF11)>,
-						 <STM32_PINMUX('C', 1, AF11)>,
-						 <STM32_PINMUX('A', 2, AF11)>,
-						 <STM32_PINMUX('A', 1, AF11)>;
-					slew-rate = <2>;
-				};
-			};
-
-			sdmmc1_b4_pins_a: sdmmc1-b4-0 {
-				pins {
-					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
-						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
-						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
-						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
-						 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
-						 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
-					slew-rate = <3>;
-					drive-push-pull;
-					bias-disable;
-				};
-			};
-
-			sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
-				pins1 {
-					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
-						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
-						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
-						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
-						 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
-					slew-rate = <3>;
-					drive-push-pull;
-					bias-disable;
-				};
-				pins2{
-					pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
-					slew-rate = <3>;
-					drive-open-drain;
-					bias-disable;
-				};
-			};
-
-			sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
-				pins {
-					pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
-						 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
-						 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
-						 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
-						 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
-						 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
-				};
-			};
-
-			sdmmc1_dir_pins_a: sdmmc1-dir-0 {
-				pins1 {
-					pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
-						 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
-						 <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
-					slew-rate = <3>;
-					drive-push-pull;
-					bias-pull-up;
-				};
-				pins2{
-					pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
-					bias-pull-up;
-				};
-			};
-
-			sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
-				pins {
-					pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
-						 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
-						 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
-						 <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
-				};
-			};
-
-			usart1_pins: usart1-0 {
-				pins1 {
-					pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
-					bias-disable;
-					drive-push-pull;
-					slew-rate = <0>;
-				};
-				pins2 {
-					pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
-					bias-disable;
-				};
-			};
-
-			usart2_pins: usart2-0 {
-				pins1 {
-					pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
-					bias-disable;
-					drive-push-pull;
-					slew-rate = <0>;
-				};
-				pins2 {
-					pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
-					bias-disable;
-				};
-			};
-
-			usbotg_hs_pins_a: usbotg-hs-0 {
-				pins {
-					pinmux = <STM32_PINMUX('H', 4, AF10)>,	/* ULPI_NXT */
-							 <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
-							 <STM32_PINMUX('C', 0, AF10)>,	/* ULPI_STP> */
-							 <STM32_PINMUX('A', 5, AF10)>,	/* ULPI_CK> */
-							 <STM32_PINMUX('A', 3, AF10)>,	/* ULPI_D0> */
-							 <STM32_PINMUX('B', 0, AF10)>,	/* ULPI_D1> */
-							 <STM32_PINMUX('B', 1, AF10)>,	/* ULPI_D2> */
-							 <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
-							 <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
-							 <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
-							 <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
-							 <STM32_PINMUX('B', 5, AF10)>;	/* ULPI_D7> */
-					bias-disable;
-					drive-push-pull;
-					slew-rate = <2>;
-				};
-			};
-		};
-	};
+&pinctrl{
+	compatible = "st,stm32h743-pinctrl";
 };
-- 
2.7.4

[PATCH 6/8] ARM: dts: stm32: add stm32h750-pinctrl.dtsi

[dillon.minfei]

From: dillon min <dillon.minfei@gmail.com>

Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 arch/arm/boot/dts/stm32h750-pinctrl.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32h750-pinctrl.dtsi

diff --git a/arch/arm/boot/dts/stm32h750-pinctrl.dtsi b/arch/arm/boot/dts/stm32h750-pinctrl.dtsi
new file mode 100644
index 000000000000..24e99970167c
--- /dev/null
+++ b/arch/arm/boot/dts/stm32h750-pinctrl.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
+ * Author: Dillon Min  <dillon.minfei@gmail.com> for STMicroelectronics.
+ */
+
+#include "stm32h7-pinctrl.dtsi"
+
+&pinctrl{
+	compatible = "st,stm32h750-pinctrl";
+};
-- 
2.7.4

[PATCH 7/8] ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6

[dillon.minfei]

From: dillon min <dillon.minfei@gmail.com>

This patchset has following changes:

- add stm32h750i-art-pi.dtb
- add dts binding usart3 for bt, uart4 for console
- add dts binding sdmmc2 for wifi
- add stm32h750-art-pi.dts to support art-pi board

board component:
- 8MiB qspi flash
- 16MiB spi flash
- 32MiB sdram
- ap6212 wifi&bt&fm

the detail board information can be found at:
https://art-pi.gitee.io/website/

Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 arch/arm/boot/dts/Makefile              |   1 +
 arch/arm/boot/dts/stm32h743.dtsi        |  30 +++++
 arch/arm/boot/dts/stm32h750.dtsi        |   5 +
 arch/arm/boot/dts/stm32h750i-art-pi.dts | 224 ++++++++++++++++++++++++++++++++
 4 files changed, 260 insertions(+)
 create mode 100644 arch/arm/boot/dts/stm32h750.dtsi
 create mode 100644 arch/arm/boot/dts/stm32h750i-art-pi.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8e5d4ab4e75e..a19c5ab9df84 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1071,6 +1071,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
 	stm32746g-eval.dtb \
 	stm32h743i-eval.dtb \
 	stm32h743i-disco.dtb \
+	stm32h750i-art-pi.dtb \
 	stm32mp153c-dhcom-drc02.dtb \
 	stm32mp157a-avenger96.dtb \
 	stm32mp157a-dhcor-avenger96.dtb \
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 4ebffb0a45a3..981d44051007 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -135,6 +135,22 @@
 			clocks = <&rcc USART2_CK>;
 		};
 
+		usart3: serial@40004800 {
+			compatible = "st,stm32h7-uart";
+			reg = <0x40004800 0x400>;
+			interrupts = <39>;
+			status = "disabled";
+			clocks = <&rcc USART3_CK>;
+		};
+
+		uart4: serial@40004c00 {
+			compatible = "st,stm32h7-uart";
+			reg = <0x40004c00 0x400>;
+			interrupts = <52>;
+			status = "disabled";
+			clocks = <&rcc UART4_CK>;
+		};
+
 		i2c1: i2c@40005400 {
 			compatible = "st,stm32f7-i2c";
 			#address-cells = <1>;
@@ -368,6 +384,20 @@
 			max-frequency = <120000000>;
 		};
 
+		sdmmc2: mmc@48022400 {
+			compatible = "arm,pl18x", "arm,primecell";
+			arm,primecell-periphid = <0x10153180>;
+			reg = <0x48022400 0x400>;
+			interrupts = <124>;
+			interrupt-names	= "cmd_irq";
+			clocks = <&rcc SDMMC2_CK>;
+			clock-names = "apb_pclk";
+			resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			max-frequency = <120000000>;
+		};
+
 		exti: interrupt-controller@58000000 {
 			compatible = "st,stm32h7-exti";
 			interrupt-controller;
diff --git a/arch/arm/boot/dts/stm32h750.dtsi b/arch/arm/boot/dts/stm32h750.dtsi
new file mode 100644
index 000000000000..dd9166223c2f
--- /dev/null
+++ b/arch/arm/boot/dts/stm32h750.dtsi
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */
+
+#include "stm32h743.dtsi"
+
diff --git a/arch/arm/boot/dts/stm32h750i-art-pi.dts b/arch/arm/boot/dts/stm32h750i-art-pi.dts
new file mode 100644
index 000000000000..84cf70d7800c
--- /dev/null
+++ b/arch/arm/boot/dts/stm32h750i-art-pi.dts
@@ -0,0 +1,224 @@
+/*
+ * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32h750.dtsi"
+#include "stm32h750-pinctrl.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "RT-Thread STM32H750i-ART-PI board";
+	compatible = "st,stm32h750i-art-pi", "st,stm32h750";
+
+	chosen {
+		bootargs = "root=/dev/ram";
+		stdout-path = "serial0:2000000n8";
+	};
+
+	memory@c0000000 {
+		device_type = "memory";
+		reg = <0xc0000000 0x2000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			no-map;
+			size = <0x100000>;
+			linux,dma-default;
+		};
+	};
+
+	aliases {
+		serial0 = &uart4;
+		serial1 = &usart3;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led-red {
+			gpios = <&gpioi 8 0>;
+		};
+		led-green {
+			gpios = <&gpioc 15 0>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	v3v3: regulator-v3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "v3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	wlan_pwr: regulator-wlan {
+		compatible = "regulator-fixed";
+
+		regulator-name = "wl-reg";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&clk_hse {
+	clock-frequency = <25000000>;
+};
+
+&mac {
+	status = "disabled";
+	pinctrl-0	= <&ethernet_rmii>;
+	pinctrl-names	= "default";
+	phy-mode	= "rmii";
+	phy-handle	= <&phy0>;
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		phy0: ethernet-phy@0 {
+			reg = <0>;
+		};
+	};
+};
+
+&sdmmc1 {
+	pinctrl-names = "default", "opendrain", "sleep";
+	pinctrl-0 = <&sdmmc1_b4_pins_a>;
+	pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+	broken-cd;
+	st,neg-edge;
+	bus-width = <4>;
+	vmmc-supply = <&v3v3>;
+	status = "okay";
+};
+
+&usart2 {
+	pinctrl-0 = <&usart2_pins>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
+&uart4 {
+	pinctrl-0 = <&uart4_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&dma1 {
+	status = "okay";
+};
+
+&dma2 {
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+	pinctrl-0 = <&spi1_pins>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
+	dmas = <&dmamux1 37 0x400 0x05>,
+	       <&dmamux1 38 0x400 0x05>;
+	dma-names = "rx", "tx";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <80000000>;
+
+		partition@0 {
+			label = "root filesystem";
+			reg = <0 0x1000000>;
+		};
+	};
+};
+
+&sdmmc2 {
+	pinctrl-names = "default", "opendrain", "sleep";
+	pinctrl-0 = <&sdmmc2_b4_pins_a>;
+	pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
+	pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
+	broken-cd;
+	non-removable;
+	st,neg-edge;
+	bus-width = <4>;
+	vmmc-supply = <&wlan_pwr>;
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	brcmf: bcrmf@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+	};
+};
+
+&usart3 {
+	/delete-property/st,hw-flow-ctrl;
+	cts-gpios = <&gpiod 11 GPIO_ACTIVE_LOW>;
+	rts-gpios = <&gpiod 12 GPIO_ACTIVE_LOW>;
+	dmas = <&dmamux1 45 0x400 0x05>,
+	       <&dmamux1 46 0x400 0x05>;
+	dma-names = "rx", "tx";
+	status = "okay";
+
+	bluetooth {
+		host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>;
+		device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>;
+		compatible = "brcm,bcm43438-bt";
+		max-speed = <115200>;
+	};
+};
-- 
2.7.4

[PATCH 8/8] ARM: stm32: add initial support for stm32h750

[dillon.minfei]

From: dillon min <dillon.minfei@gmail.com>

Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 arch/arm/mach-stm32/board-dt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c
index 011d57b488c2..a766310d8dca 100644
--- a/arch/arm/mach-stm32/board-dt.c
+++ b/arch/arm/mach-stm32/board-dt.c
@@ -17,6 +17,7 @@ static const char *const stm32_compat[] __initconst = {
 	"st,stm32f746",
 	"st,stm32f769",
 	"st,stm32h743",
+	"st,stm32h750",
 	"st,stm32mp157",
 	NULL
 };
-- 
2.7.4

Re: [PATCH 1/8] ARM: ARMv7-M: Fix register restore corrupt after svc call

[Vladimir Murzin]

On 3/3/21 8:05 AM, dillon.minfei@gmail.com wrote:
> From: dillon min <dillon.minfei@gmail.com>
> 
> For some case, kernel not boot by u-boot(single thread),
> but by rtos , as most rtos use pendsv to do context switch.


Hmm, does it mean that it starts kernel from process context?

I'd assume that it is not only kernel who expects MSP. So, what
if RTOS you mentioned want to boot other RTOS (even itself)? What
if you have no access to the source code for those RTOS(es) to
patch MSP/PSP switch?

I'd very much prefer to keep stack switching logic outside kernel,
say, in some shim which RTOS/bootloader can maintain.

Cheers
Vladimir

> 
> So, we need add an lr check after svc call, to find out should
> use psp or msp. else register restore after svc call might be
> corrupted.
> 
> Fixes: b70cd406d7fe ("ARM: 8671/1: V7M: Preserve registers across switch from Thread to Handler mode")
> Signed-off-by: dillon min <dillon.minfei@gmail.com>
> ---
>  arch/arm/mm/proc-v7m.S | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
> index 84459c1d31b8..c93d2757312d 100644
> --- a/arch/arm/mm/proc-v7m.S
> +++ b/arch/arm/mm/proc-v7m.S
> @@ -137,7 +137,10 @@ __v7m_setup_cont:
>  1:	cpsid	i
>  	/* Calculate exc_ret */
>  	orr	r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK
> -	ldmia	sp, {r0-r3, r12}
> +	tst	lr, #EXC_RET_STACK_MASK
> +	mrsne	r4, psp
> +	moveq	r4, sp
> +	ldmia	r4!, {r0-r3, r12}
>  	str	r5, [r12, #11 * 4]	@ restore the original SVC vector entry
>  	mov	lr, r6			@ restore LR
>  
> 

Re: [PATCH 1/8] ARM: ARMv7-M: Fix register restore corrupt after svc call

[dillon min]

Hi Vladimir,

Thanks for the review.

On Wed, Mar 3, 2021 at 5:52 PM Vladimir Murzin <vladimir.murzin@arm.com> wrote:
>
> On 3/3/21 8:05 AM, dillon.minfei@gmail.com wrote:
> > From: dillon min <dillon.minfei@gmail.com>
> >
> > For some case, kernel not boot by u-boot(single thread),
> > but by rtos , as most rtos use pendsv to do context switch.
>
>
> Hmm, does it mean that it starts kernel from process context?
   Yes, kernel might be started from process context, since u-boot not
switch context, so kernel always startup under msp.
>
> I'd assume that it is not only kernel who expects MSP. So, what
> if RTOS you mentioned want to boot other RTOS (even itself)? What
> if you have no access to the source code for those RTOS(es) to
> patch MSP/PSP switch?

My case is a little complicated.
stm32h7 only have 128Kbytes internal flash, can't store u-boot.bin (>200K),
so, set a bootloader (rt-thread rtos) to internal flash, load
linux/u-boot from serial port via ymodem
store to qspi flash(8Mbytes), then jump to u-boot.

qspi flash layout:
0 - 512K:    u-boot
512K- 8M : kernel(xip)

load process : rt-thread -> u-boot -> linux

before add psp/msp check after svc call, register restore corrupt.
add a printhex8 around svc call, found the sp stack is 0x24040000c0ffcff8
it should be 0xc0ffcdf8c0ffcff8. 0x24040000 is the sp stack address
assigned by u-boot
i've no idea how it's become to u-boot's sp.

I have the rtos code, and will try to fix it on the rtos side.

Can you give more explanation about why linux relies on MSP ? thanks

>
> I'd very much prefer to keep stack switching logic outside kernel,
> say, in some shim which RTOS/bootloader can maintain.
>
> Cheers
> Vladimir
>
> >
> > So, we need add an lr check after svc call, to find out should
> > use psp or msp. else register restore after svc call might be
> > corrupted.
> >
> > Fixes: b70cd406d7fe ("ARM: 8671/1: V7M: Preserve registers across switch from Thread to Handler mode")
> > Signed-off-by: dillon min <dillon.minfei@gmail.com>
> > ---
> >  arch/arm/mm/proc-v7m.S | 5 ++++-
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
> > index 84459c1d31b8..c93d2757312d 100644
> > --- a/arch/arm/mm/proc-v7m.S
> > +++ b/arch/arm/mm/proc-v7m.S
> > @@ -137,7 +137,10 @@ __v7m_setup_cont:
> >  1:   cpsid   i
> >       /* Calculate exc_ret */
> >       orr     r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK
> > -     ldmia   sp, {r0-r3, r12}
> > +     tst     lr, #EXC_RET_STACK_MASK
> > +     mrsne   r4, psp
> > +     moveq   r4, sp
> > +     ldmia   r4!, {r0-r3, r12}
> >       str     r5, [r12, #11 * 4]      @ restore the original SVC vector entry
> >       mov     lr, r6                  @ restore LR
> >
> >
>

Re: [PATCH 1/8] ARM: ARMv7-M: Fix register restore corrupt after svc call

[Vladimir Murzin]

On 3/3/21 1:35 PM, dillon min wrote:
> Hi Vladimir,
> 
> Thanks for the review.
> 
> On Wed, Mar 3, 2021 at 5:52 PM Vladimir Murzin <vladimir.murzin@arm.com> wrote:
>>
>> On 3/3/21 8:05 AM, dillon.minfei@gmail.com wrote:
>>> From: dillon min <dillon.minfei@gmail.com>
>>>
>>> For some case, kernel not boot by u-boot(single thread),
>>> but by rtos , as most rtos use pendsv to do context switch.
>>
>>
>> Hmm, does it mean that it starts kernel from process context?
>    Yes, kernel might be started from process context, since u-boot not
> switch context, so kernel always startup under msp.
>>
>> I'd assume that it is not only kernel who expects MSP. So, what
>> if RTOS you mentioned want to boot other RTOS (even itself)? What
>> if you have no access to the source code for those RTOS(es) to
>> patch MSP/PSP switch?
> 
> My case is a little complicated.
> stm32h7 only have 128Kbytes internal flash, can't store u-boot.bin (>200K),
> so, set a bootloader (rt-thread rtos) to internal flash, load
> linux/u-boot from serial port via ymodem
> store to qspi flash(8Mbytes), then jump to u-boot.
> 
> qspi flash layout:
> 0 - 512K:    u-boot
> 512K- 8M : kernel(xip)
> 
> load process : rt-thread -> u-boot -> linux
> 
> before add psp/msp check after svc call, register restore corrupt.
> add a printhex8 around svc call, found the sp stack is 0x24040000c0ffcff8
> it should be 0xc0ffcdf8c0ffcff8. 0x24040000 is the sp stack address
> assigned by u-boot
> i've no idea how it's become to u-boot's sp.
> 
> I have the rtos code, and will try to fix it on the rtos side.

That would be great!

> 
> Can you give more explanation about why linux relies on MSP ? thanks

MSP is what set from boot, thus it is natural assumption that boot code
would preserve that illusion.

I'd guess that kernel is in line in such assumption across different
(RT)OS capable to run on M-class cores (please, note that some variants
might not have two stack pointers)

Cheers
Vladimir

> 
>>
>> I'd very much prefer to keep stack switching logic outside kernel,
>> say, in some shim which RTOS/bootloader can maintain.
>>
>> Cheers
>> Vladimir
>>
>>>
>>> So, we need add an lr check after svc call, to find out should
>>> use psp or msp. else register restore after svc call might be
>>> corrupted.
>>>
>>> Fixes: b70cd406d7fe ("ARM: 8671/1: V7M: Preserve registers across switch from Thread to Handler mode")
>>> Signed-off-by: dillon min <dillon.minfei@gmail.com>
>>> ---
>>>  arch/arm/mm/proc-v7m.S | 5 ++++-
>>>  1 file changed, 4 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
>>> index 84459c1d31b8..c93d2757312d 100644
>>> --- a/arch/arm/mm/proc-v7m.S
>>> +++ b/arch/arm/mm/proc-v7m.S
>>> @@ -137,7 +137,10 @@ __v7m_setup_cont:
>>>  1:   cpsid   i
>>>       /* Calculate exc_ret */
>>>       orr     r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK
>>> -     ldmia   sp, {r0-r3, r12}
>>> +     tst     lr, #EXC_RET_STACK_MASK
>>> +     mrsne   r4, psp
>>> +     moveq   r4, sp
>>> +     ldmia   r4!, {r0-r3, r12}
>>>       str     r5, [r12, #11 * 4]      @ restore the original SVC vector entry
>>>       mov     lr, r6                  @ restore LR
>>>
>>>
>>
> 

Re: [PATCH 1/8] ARM: ARMv7-M: Fix register restore corrupt after svc call

[dillon min]

On Wed, Mar 3, 2021 at 10:19 PM Vladimir Murzin <vladimir.murzin@arm.com> wrote:
>
> On 3/3/21 1:35 PM, dillon min wrote:
> > Hi Vladimir,
> >
> > Thanks for the review.
> >
> > On Wed, Mar 3, 2021 at 5:52 PM Vladimir Murzin <vladimir.murzin@arm.com> wrote:
> >>
> >> On 3/3/21 8:05 AM, dillon.minfei@gmail.com wrote:
> >>> From: dillon min <dillon.minfei@gmail.com>
> >>>
> >>> For some case, kernel not boot by u-boot(single thread),
> >>> but by rtos , as most rtos use pendsv to do context switch.
> >>
> >>
> >> Hmm, does it mean that it starts kernel from process context?
> >    Yes, kernel might be started from process context, since u-boot not
> > switch context, so kernel always startup under msp.
> >>
> >> I'd assume that it is not only kernel who expects MSP. So, what
> >> if RTOS you mentioned want to boot other RTOS (even itself)? What
> >> if you have no access to the source code for those RTOS(es) to
> >> patch MSP/PSP switch?
> >
> > My case is a little complicated.
> > stm32h7 only have 128Kbytes internal flash, can't store u-boot.bin (>200K),
> > so, set a bootloader (rt-thread rtos) to internal flash, load
> > linux/u-boot from serial port via ymodem
> > store to qspi flash(8Mbytes), then jump to u-boot.
> >
> > qspi flash layout:
> > 0 - 512K:    u-boot
> > 512K- 8M : kernel(xip)
> >
> > load process : rt-thread -> u-boot -> linux
> >
> > before add psp/msp check after svc call, register restore corrupt.
> > add a printhex8 around svc call, found the sp stack is 0x24040000c0ffcff8
> > it should be 0xc0ffcdf8c0ffcff8. 0x24040000 is the sp stack address
> > assigned by u-boot
> > i've no idea how it's become to u-boot's sp.
> >
> > I have the rtos code, and will try to fix it on the rtos side.
>
> That would be great!
>
> >
> > Can you give more explanation about why linux relies on MSP ? thanks
>
> MSP is what set from boot, thus it is natural assumption that boot code
> would preserve that illusion.
>
> I'd guess that kernel is in line in such assumption across different
> (RT)OS capable to run on M-class cores (please, note that some variants
> might not have two stack pointers)
>
Okay， got it. after adding msp/psp switch code in RTOS, now the kernel
can be loaded normally
without any modification.

So, just drop the changes in proc-v7m.S.

Thanks.
> Cheers
> Vladimir
>
> >
> >>
> >> I'd very much prefer to keep stack switching logic outside kernel,
> >> say, in some shim which RTOS/bootloader can maintain.
> >>
> >> Cheers
> >> Vladimir
> >>
> >>>
> >>> So, we need add an lr check after svc call, to find out should
> >>> use psp or msp. else register restore after svc call might be
> >>> corrupted.
> >>>
> >>> Fixes: b70cd406d7fe ("ARM: 8671/1: V7M: Preserve registers across switch from Thread to Handler mode")
> >>> Signed-off-by: dillon min <dillon.minfei@gmail.com>
> >>> ---
> >>>  arch/arm/mm/proc-v7m.S | 5 ++++-
> >>>  1 file changed, 4 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
> >>> index 84459c1d31b8..c93d2757312d 100644
> >>> --- a/arch/arm/mm/proc-v7m.S
> >>> +++ b/arch/arm/mm/proc-v7m.S
> >>> @@ -137,7 +137,10 @@ __v7m_setup_cont:
> >>>  1:   cpsid   i
> >>>       /* Calculate exc_ret */
> >>>       orr     r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK
> >>> -     ldmia   sp, {r0-r3, r12}
> >>> +     tst     lr, #EXC_RET_STACK_MASK
> >>> +     mrsne   r4, psp
> >>> +     moveq   r4, sp
> >>> +     ldmia   r4!, {r0-r3, r12}
> >>>       str     r5, [r12, #11 * 4]      @ restore the original SVC vector entry
> >>>       mov     lr, r6                  @ restore LR
> >>>
> >>>
> >>
> >
>

Re: [PATCH 1/8] ARM: ARMv7-M: Fix register restore corrupt after svc call

[Vladimir Murzin]

On 3/4/21 5:42 AM, dillon min wrote:
> Okay， got it. after adding msp/psp switch code in RTOS, now the kernel
> can be loaded normally
> without any modification.

Yay!

> 
> So, just drop the changes in proc-v7m.S.

Glad to see they are not strictly necessary :)

Thanks
Vladimir

Re: [PATCH 3/8] dt-bindings: arm: stm32: Add compatible strings for ART-PI board

[Rob Herring]

On Wed, 03 Mar 2021 16:05:12 +0800, dillon.minfei@gmail.com wrote:
> From: dillon min <dillon.minfei@gmail.com>
> 
> Art-pi based on stm32h750xbh6, with following resources:
> 
> -8MiB QSPI flash
> -16MiB SPI flash
> -32MiB SDRAM
> -AP6212 wifi, bt, fm
> 
> detail information can be found at:
> https://art-pi.gitee.io/website/
> 
> Signed-off-by: dillon min <dillon.minfei@gmail.com>
> ---
>  Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 4/8] dt-bindings: pinctrl: stm32: Add stm32h750 pinctrl

[Rob Herring]

On Wed, 03 Mar 2021 16:05:13 +0800, dillon.minfei@gmail.com wrote:
> From: dillon min <dillon.minfei@gmail.com>
> 
> Signed-off-by: dillon min <dillon.minfei@gmail.com>
> ---
>  Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 0/8] ARM: STM32: add art-pi(stm32h750xbh6) board support

[dillon min]

for the device tree part , still waiting review. just a gentle ping.
if Mr Alexandre torgue can take a look, would be great.

thanks,

On Wed, Mar 3, 2021 at 4:05 PM <dillon.minfei@gmail.com> wrote:
>
> From: dillon min <dillon.minfei@gmail.com>
>
> This patchset intend to add art-pi board support, this board developed
> by rt-thread(https://www.rt-thread.org/).
>
> Board resources:
>
> 8MiB QSPI flash
> 16MiB SPI flash
> 32MiB SDRAM
> AP6212 wifi,bt,fm comb
>
> sw context:
> - as stm32h750 just has 128k bytes internal flash, so running a fw on
>   internal flash to download u-boot/kernel to qspi flash, boot
>   u-boot/kernel from qspi flash. this fw is based on rt-thread.
> - kernel can be xip on qspi flash or load to sdram
> - root filesystem is jffs2(created by buildroot), stored on spi flash
>
> to support the boad, add following changes.
> - fix r0-r3, r12 register restore failed after svc call,
> - add dts binding
> - update yaml doc
>
> dillon min (8):
>   ARM: ARMv7-M: Fix register restore corrupt after svc call
>   Documentation: arm: stm32: Add stm32h750 value line
>   dt-bindings: arm: stm32: Add compatible strings for ART-PI board
>   dt-bindings: pinctrl: stm32: Add stm32h750 pinctrl
>   ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h75x
>   ARM: dts: stm32: add stm32h750-pinctrl.dtsi
>   ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6
>   ARM: stm32: add initial support for stm32h750
>
>  Documentation/arm/index.rst                        |   1 +
>  Documentation/arm/stm32/stm32h750-overview.rst     |  33 ++
>  .../devicetree/bindings/arm/stm32/stm32.yaml       |   4 +
>  .../bindings/pinctrl/st,stm32-pinctrl.yaml         |   1 +
>  arch/arm/boot/dts/Makefile                         |   1 +
>  arch/arm/boot/dts/stm32h7-pinctrl.dtsi             | 392 +++++++++++++++++++++
>  arch/arm/boot/dts/stm32h743-pinctrl.dtsi           | 307 +---------------
>  arch/arm/boot/dts/stm32h743.dtsi                   |  30 ++
>  arch/arm/boot/dts/stm32h750-pinctrl.dtsi           |  11 +
>  arch/arm/boot/dts/stm32h750.dtsi                   |   5 +
>  arch/arm/boot/dts/stm32h750i-art-pi.dts            | 227 ++++++++++++
>  arch/arm/mach-stm32/board-dt.c                     |   1 +
>  arch/arm/mm/proc-v7m.S                             |   5 +-
>  13 files changed, 716 insertions(+), 302 deletions(-)
>  create mode 100644 Documentation/arm/stm32/stm32h750-overview.rst
>  create mode 100644 arch/arm/boot/dts/stm32h7-pinctrl.dtsi
>  create mode 100644 arch/arm/boot/dts/stm32h750-pinctrl.dtsi
>  create mode 100644 arch/arm/boot/dts/stm32h750.dtsi
>  create mode 100644 arch/arm/boot/dts/stm32h750i-art-pi.dts
>
> --
> 2.7.4
>

RE: [PATCH 0/8] ARM: STM32: add art-pi(stm32h750xbh6) board support

[Alexandre TORGUE]

Hi Dillon

> -----Original Message-----
> From: dillon min <dillon.minfei@gmail.com>
> Sent: mercredi 10 mars 2021 12:48
> To: Rob Herring <robh+dt@kernel.org>; Maxime Coquelin
> <mcoquelin.stm32@gmail.com>; Alexandre TORGUE
> <alexandre.torgue@st.com>; open list:OPEN FIRMWARE AND FLATTENED
> DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; linux-stm32@st-md-
> mailman.stormreply.com; Linux ARM <linux-arm-
> kernel@lists.infradead.org>; Linux Kernel Mailing List <linux-
> kernel@vger.kernel.org>; linux@armlinux.org.uk; Vladimir Murzin
> <vladimir.murzin@arm.com>; afzal.mohd.ma@gmail.com
> Subject: Re: [PATCH 0/8] ARM: STM32: add art-pi(stm32h750xbh6) board
> support
> 
> for the device tree part , still waiting review. just a gentle ping.
> if Mr Alexandre torgue can take a look, would be great.
> 

Sorry for the delay. For next versions can you send it to
Alexandre.torgue@foss.st.com please.

Thanks
Alex

> thanks,
> 
> On Wed, Mar 3, 2021 at 4:05 PM <dillon.minfei@gmail.com> wrote:
> >
> > From: dillon min <dillon.minfei@gmail.com>
> >
> > This patchset intend to add art-pi board support, this board developed
> > by rt-thread(https://www.rt-thread.org/).
> >
> > Board resources:
> >
> > 8MiB QSPI flash
> > 16MiB SPI flash
> > 32MiB SDRAM
> > AP6212 wifi,bt,fm comb
> >
> > sw context:
> > - as stm32h750 just has 128k bytes internal flash, so running a fw on
> >   internal flash to download u-boot/kernel to qspi flash, boot
> >   u-boot/kernel from qspi flash. this fw is based on rt-thread.
> > - kernel can be xip on qspi flash or load to sdram
> > - root filesystem is jffs2(created by buildroot), stored on spi flash
> >
> > to support the boad, add following changes.
> > - fix r0-r3, r12 register restore failed after svc call,
> > - add dts binding
> > - update yaml doc
> >
> > dillon min (8):
> >   ARM: ARMv7-M: Fix register restore corrupt after svc call
> >   Documentation: arm: stm32: Add stm32h750 value line
> >   dt-bindings: arm: stm32: Add compatible strings for ART-PI board
> >   dt-bindings: pinctrl: stm32: Add stm32h750 pinctrl
> >   ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h75x
> >   ARM: dts: stm32: add stm32h750-pinctrl.dtsi
> >   ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6
> >   ARM: stm32: add initial support for stm32h750
> >
> >  Documentation/arm/index.rst                        |   1 +
> >  Documentation/arm/stm32/stm32h750-overview.rst     |  33 ++
> >  .../devicetree/bindings/arm/stm32/stm32.yaml       |   4 +
> >  .../bindings/pinctrl/st,stm32-pinctrl.yaml         |   1 +
> >  arch/arm/boot/dts/Makefile                         |   1 +
> >  arch/arm/boot/dts/stm32h7-pinctrl.dtsi             | 392
> +++++++++++++++++++++
> >  arch/arm/boot/dts/stm32h743-pinctrl.dtsi           | 307 +---------------
> >  arch/arm/boot/dts/stm32h743.dtsi                   |  30 ++
> >  arch/arm/boot/dts/stm32h750-pinctrl.dtsi           |  11 +
> >  arch/arm/boot/dts/stm32h750.dtsi                   |   5 +
> >  arch/arm/boot/dts/stm32h750i-art-pi.dts            | 227 ++++++++++++
> >  arch/arm/mach-stm32/board-dt.c                     |   1 +
> >  arch/arm/mm/proc-v7m.S                             |   5 +-
> >  13 files changed, 716 insertions(+), 302 deletions(-)  create mode
> > 100644 Documentation/arm/stm32/stm32h750-overview.rst
> >  create mode 100644 arch/arm/boot/dts/stm32h7-pinctrl.dtsi
> >  create mode 100644 arch/arm/boot/dts/stm32h750-pinctrl.dtsi
> >  create mode 100644 arch/arm/boot/dts/stm32h750.dtsi  create mode
> > 100644 arch/arm/boot/dts/stm32h750i-art-pi.dts
> >
> > --
> > 2.7.4
> >

Re: [PATCH 5/8] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h75x

[Alexandre TORGUE]

Hi Dillon

On 3/3/21 9:05 AM, dillon.minfei@gmail.com wrote:
> From: dillon min <dillon.minfei@gmail.com>
> 
> To support stm32h750 and stm32h743, we need a base stm32h7-pinctrl.dtsi
> as stm32h743 & h750 has almost the same interface. so, just rename
> stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi
> 

You do not "just" rename but you keel also the old version. I don't 
agree with this approach. You have first to rename 
stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi (keeping copyright as 
they are please) and modify existing H7 boards which currently use 
stm32h743-pinctrl.dtsi.
Then you create a second patch adding your pingroups.

Now regarding "st,stm32h750-pinctrl", I see a patch dealing with this 
new binding but no update on driver side. Do I miss something ? what are 
differences between h743 and h750 regarding pinctrl ?

Regards
Alex

> Signed-off-by: dillon min <dillon.minfei@gmail.com>
> ---
>   arch/arm/boot/dts/stm32h7-pinctrl.dtsi   | 392 +++++++++++++++++++++++++++++++
>   arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 307 +-----------------------
>   2 files changed, 398 insertions(+), 301 deletions(-)
>   create mode 100644 arch/arm/boot/dts/stm32h7-pinctrl.dtsi
> 
> diff --git a/arch/arm/boot/dts/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi
> new file mode 100644
> index 000000000000..7d4b5d683ccc
> --- /dev/null
> +++ b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi
> @@ -0,0 +1,392 @@
> +/*
> + * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/pinctrl/stm32-pinfunc.h>
> +
> +/ {
> +	soc {
> +		pinctrl: pin-controller {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0x58020000 0x3000>;
> +			interrupt-parent = <&exti>;
> +			st,syscfg = <&syscfg 0x8>;
> +			pins-are-numbered;
> +
> +			gpioa: gpio@58020000 {
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				reg = <0x0 0x400>;
> +				clocks = <&rcc GPIOA_CK>;
> +				st,bank-name = "GPIOA";
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpiob: gpio@58020400 {
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				reg = <0x400 0x400>;
> +				clocks = <&rcc GPIOB_CK>;
> +				st,bank-name = "GPIOB";
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpioc: gpio@58020800 {
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				reg = <0x800 0x400>;
> +				clocks = <&rcc GPIOC_CK>;
> +				st,bank-name = "GPIOC";
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpiod: gpio@58020c00 {
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				reg = <0xc00 0x400>;
> +				clocks = <&rcc GPIOD_CK>;
> +				st,bank-name = "GPIOD";
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpioe: gpio@58021000 {
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				reg = <0x1000 0x400>;
> +				clocks = <&rcc GPIOE_CK>;
> +				st,bank-name = "GPIOE";
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpiof: gpio@58021400 {
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				reg = <0x1400 0x400>;
> +				clocks = <&rcc GPIOF_CK>;
> +				st,bank-name = "GPIOF";
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpiog: gpio@58021800 {
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				reg = <0x1800 0x400>;
> +				clocks = <&rcc GPIOG_CK>;
> +				st,bank-name = "GPIOG";
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpioh: gpio@58021c00 {
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				reg = <0x1c00 0x400>;
> +				clocks = <&rcc GPIOH_CK>;
> +				st,bank-name = "GPIOH";
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpioi: gpio@58022000 {
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				reg = <0x2000 0x400>;
> +				clocks = <&rcc GPIOI_CK>;
> +				st,bank-name = "GPIOI";
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpioj: gpio@58022400 {
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				reg = <0x2400 0x400>;
> +				clocks = <&rcc GPIOJ_CK>;
> +				st,bank-name = "GPIOJ";
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpiok: gpio@58022800 {
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				reg = <0x2800 0x400>;
> +				clocks = <&rcc GPIOK_CK>;
> +				st,bank-name = "GPIOK";
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			i2c1_pins_a: i2c1-0 {
> +				pins {
> +					pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
> +						 <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
> +					bias-disable;
> +					drive-open-drain;
> +					slew-rate = <0>;
> +				};
> +			};
> +
> +			ethernet_rmii: rmii-0 {
> +				pins {
> +					pinmux = <STM32_PINMUX('G', 11, AF11)>,
> +						 <STM32_PINMUX('G', 13, AF11)>,
> +						 <STM32_PINMUX('G', 12, AF11)>,
> +						 <STM32_PINMUX('C', 4, AF11)>,
> +						 <STM32_PINMUX('C', 5, AF11)>,
> +						 <STM32_PINMUX('A', 7, AF11)>,
> +						 <STM32_PINMUX('C', 1, AF11)>,
> +						 <STM32_PINMUX('A', 2, AF11)>,
> +						 <STM32_PINMUX('A', 1, AF11)>;
> +					slew-rate = <2>;
> +				};
> +			};
> +
> +			sdmmc1_b4_pins_a: sdmmc1-b4-0 {
> +				pins {
> +					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
> +						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
> +						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
> +						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
> +						 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
> +						 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
> +					slew-rate = <3>;
> +					drive-push-pull;
> +					bias-disable;
> +				};
> +			};
> +
> +			sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
> +				pins1 {
> +					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
> +						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
> +						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
> +						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
> +						 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
> +					slew-rate = <3>;
> +					drive-push-pull;
> +					bias-disable;
> +				};
> +				pins2{
> +					pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
> +					slew-rate = <3>;
> +					drive-open-drain;
> +					bias-disable;
> +				};
> +			};
> +
> +			sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
> +				pins {
> +					pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
> +						 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
> +						 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
> +						 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
> +						 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
> +						 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
> +				};
> +			};
> +
> +			sdmmc2_b4_pins_a: sdmmc2-b4-0 {
> +				pins {
> +					pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */
> +						 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
> +						 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
> +						 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
> +						 <STM32_PINMUX('D', 6, AF11)>, /* SDMMC1_CK */
> +						 <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
> +					slew-rate = <3>;
> +					drive-push-pull;
> +					bias-disable;
> +				};
> +			};
> +
> +			sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
> +				pins1 {
> +					pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
> +						 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
> +						 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
> +						 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
> +						 <STM32_PINMUX('D', 6, AF11)>; /* SDMMC1_CK */
> +					slew-rate = <3>;
> +					drive-push-pull;
> +					bias-disable;
> +				};
> +				pins2{
> +					pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
> +					slew-rate = <3>;
> +					drive-open-drain;
> +					bias-disable;
> +				};
> +			};
> +
> +			sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
> +				pins {
> +					pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC1_D0 */
> +						 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC1_D1 */
> +						 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC1_D2 */
> +						 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC1_D3 */
> +						 <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC1_CK */
> +						 <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC1_CMD */
> +				};
> +			};
> +
> +			sdmmc1_dir_pins_a: sdmmc1-dir-0 {
> +				pins1 {
> +					pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
> +						 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
> +						 <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
> +					slew-rate = <3>;
> +					drive-push-pull;
> +					bias-pull-up;
> +				};
> +				pins2{
> +					pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
> +					bias-pull-up;
> +				};
> +			};
> +
> +			sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
> +				pins {
> +					pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
> +						 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
> +						 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
> +						 <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
> +				};
> +			};
> +
> +			usart1_pins: usart1-0 {
> +				pins1 {
> +					pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
> +					bias-disable;
> +					drive-push-pull;
> +					slew-rate = <0>;
> +				};
> +				pins2 {
> +					pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
> +					bias-disable;
> +				};
> +			};
> +
> +			usart2_pins: usart2-0 {
> +				pins1 {
> +					pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
> +					bias-disable;
> +					drive-push-pull;
> +					slew-rate = <0>;
> +				};
> +				pins2 {
> +					pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
> +					bias-disable;
> +				};
> +			};
> +
> +			usart3_pins: usart3-0 {
> +				pins1 {
> +					pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
> +					bias-disable;
> +					drive-push-pull;
> +					slew-rate = <0>;
> +				};
> +				pins2 {
> +					pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
> +					bias-disable;
> +				};
> +			};
> +
> +			uart4_pins: uart4-0 {
> +				pins1 {
> +					pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */
> +					bias-disable;
> +					drive-push-pull;
> +					slew-rate = <0>;
> +				};
> +				pins2 {
> +					pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */
> +					bias-disable;
> +				};
> +			};
> +
> +			usbotg_hs_pins_a: usbotg-hs-0 {
> +				pins {
> +					pinmux = <STM32_PINMUX('H', 4, AF10)>,	/* ULPI_NXT */
> +							 <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
> +							 <STM32_PINMUX('C', 0, AF10)>,	/* ULPI_STP> */
> +							 <STM32_PINMUX('A', 5, AF10)>,	/* ULPI_CK> */
> +							 <STM32_PINMUX('A', 3, AF10)>,	/* ULPI_D0> */
> +							 <STM32_PINMUX('B', 0, AF10)>,	/* ULPI_D1> */
> +							 <STM32_PINMUX('B', 1, AF10)>,	/* ULPI_D2> */
> +							 <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
> +							 <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
> +							 <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
> +							 <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
> +							 <STM32_PINMUX('B', 5, AF10)>;	/* ULPI_D7> */
> +					bias-disable;
> +					drive-push-pull;
> +					slew-rate = <2>;
> +				};
> +			};
> +
> +			spi1_pins: spi1-0 {
> +				pins1 {
> +					pinmux = <STM32_PINMUX('A', 5, AF5)>,
> +						/* SPI1_CLK */
> +						 <STM32_PINMUX('B', 5, AF5)>;
> +						/* SPI1_MOSI */
> +					bias-disable;
> +					drive-push-pull;
> +					slew-rate = <2>;
> +				};
> +				pins2 {
> +					pinmux = <STM32_PINMUX('G', 9, AF5)>;
> +						/* SPI1_MISO */
> +					bias-disable;
> +				};
> +			};
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
> index fa5dcb6a5fdd..6b1e115307b9 100644
> --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
> @@ -1,306 +1,11 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>   /*
> - * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
> - *
> - * This file is dual-licensed: you can use it either under the terms
> - * of the GPL or the X11 license, at your option. Note that this dual
> - * licensing only applies to this file, and not this project as a
> - * whole.
> - *
> - *  a) This file is free software; you can redistribute it and/or
> - *     modify it under the terms of the GNU General Public License as
> - *     published by the Free Software Foundation; either version 2 of the
> - *     License, or (at your option) any later version.
> - *
> - *     This file is distributed in the hope that it will be useful,
> - *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> - *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - *     GNU General Public License for more details.
> - *
> - * Or, alternatively,
> - *
> - *  b) Permission is hereby granted, free of charge, to any person
> - *     obtaining a copy of this software and associated documentation
> - *     files (the "Software"), to deal in the Software without
> - *     restriction, including without limitation the rights to use,
> - *     copy, modify, merge, publish, distribute, sublicense, and/or
> - *     sell copies of the Software, and to permit persons to whom the
> - *     Software is furnished to do so, subject to the following
> - *     conditions:
> - *
> - *     The above copyright notice and this permission notice shall be
> - *     included in all copies or substantial portions of the Software.
> - *
> - *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> - *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> - *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> - *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> - *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> - *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> - *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - *     OTHER DEALINGS IN THE SOFTWARE.
> + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
> + * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
>    */
>   
> -#include <dt-bindings/pinctrl/stm32-pinfunc.h>
> +#include "stm32h7-pinctrl.dtsi"
>   
> -/ {
> -	soc {
> -		pin-controller {
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			compatible = "st,stm32h743-pinctrl";
> -			ranges = <0 0x58020000 0x3000>;
> -			interrupt-parent = <&exti>;
> -			st,syscfg = <&syscfg 0x8>;
> -			pins-are-numbered;
> -
> -			gpioa: gpio@58020000 {
> -				gpio-controller;
> -				#gpio-cells = <2>;
> -				reg = <0x0 0x400>;
> -				clocks = <&rcc GPIOA_CK>;
> -				st,bank-name = "GPIOA";
> -				interrupt-controller;
> -				#interrupt-cells = <2>;
> -			};
> -
> -			gpiob: gpio@58020400 {
> -				gpio-controller;
> -				#gpio-cells = <2>;
> -				reg = <0x400 0x400>;
> -				clocks = <&rcc GPIOB_CK>;
> -				st,bank-name = "GPIOB";
> -				interrupt-controller;
> -				#interrupt-cells = <2>;
> -			};
> -
> -			gpioc: gpio@58020800 {
> -				gpio-controller;
> -				#gpio-cells = <2>;
> -				reg = <0x800 0x400>;
> -				clocks = <&rcc GPIOC_CK>;
> -				st,bank-name = "GPIOC";
> -				interrupt-controller;
> -				#interrupt-cells = <2>;
> -			};
> -
> -			gpiod: gpio@58020c00 {
> -				gpio-controller;
> -				#gpio-cells = <2>;
> -				reg = <0xc00 0x400>;
> -				clocks = <&rcc GPIOD_CK>;
> -				st,bank-name = "GPIOD";
> -				interrupt-controller;
> -				#interrupt-cells = <2>;
> -			};
> -
> -			gpioe: gpio@58021000 {
> -				gpio-controller;
> -				#gpio-cells = <2>;
> -				reg = <0x1000 0x400>;
> -				clocks = <&rcc GPIOE_CK>;
> -				st,bank-name = "GPIOE";
> -				interrupt-controller;
> -				#interrupt-cells = <2>;
> -			};
> -
> -			gpiof: gpio@58021400 {
> -				gpio-controller;
> -				#gpio-cells = <2>;
> -				reg = <0x1400 0x400>;
> -				clocks = <&rcc GPIOF_CK>;
> -				st,bank-name = "GPIOF";
> -				interrupt-controller;
> -				#interrupt-cells = <2>;
> -			};
> -
> -			gpiog: gpio@58021800 {
> -				gpio-controller;
> -				#gpio-cells = <2>;
> -				reg = <0x1800 0x400>;
> -				clocks = <&rcc GPIOG_CK>;
> -				st,bank-name = "GPIOG";
> -				interrupt-controller;
> -				#interrupt-cells = <2>;
> -			};
> -
> -			gpioh: gpio@58021c00 {
> -				gpio-controller;
> -				#gpio-cells = <2>;
> -				reg = <0x1c00 0x400>;
> -				clocks = <&rcc GPIOH_CK>;
> -				st,bank-name = "GPIOH";
> -				interrupt-controller;
> -				#interrupt-cells = <2>;
> -			};
> -
> -			gpioi: gpio@58022000 {
> -				gpio-controller;
> -				#gpio-cells = <2>;
> -				reg = <0x2000 0x400>;
> -				clocks = <&rcc GPIOI_CK>;
> -				st,bank-name = "GPIOI";
> -				interrupt-controller;
> -				#interrupt-cells = <2>;
> -			};
> -
> -			gpioj: gpio@58022400 {
> -				gpio-controller;
> -				#gpio-cells = <2>;
> -				reg = <0x2400 0x400>;
> -				clocks = <&rcc GPIOJ_CK>;
> -				st,bank-name = "GPIOJ";
> -				interrupt-controller;
> -				#interrupt-cells = <2>;
> -			};
> -
> -			gpiok: gpio@58022800 {
> -				gpio-controller;
> -				#gpio-cells = <2>;
> -				reg = <0x2800 0x400>;
> -				clocks = <&rcc GPIOK_CK>;
> -				st,bank-name = "GPIOK";
> -				interrupt-controller;
> -				#interrupt-cells = <2>;
> -			};
> -
> -			i2c1_pins_a: i2c1-0 {
> -				pins {
> -					pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
> -						 <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
> -					bias-disable;
> -					drive-open-drain;
> -					slew-rate = <0>;
> -				};
> -			};
> -
> -			ethernet_rmii: rmii-0 {
> -				pins {
> -					pinmux = <STM32_PINMUX('G', 11, AF11)>,
> -						 <STM32_PINMUX('G', 13, AF11)>,
> -						 <STM32_PINMUX('G', 12, AF11)>,
> -						 <STM32_PINMUX('C', 4, AF11)>,
> -						 <STM32_PINMUX('C', 5, AF11)>,
> -						 <STM32_PINMUX('A', 7, AF11)>,
> -						 <STM32_PINMUX('C', 1, AF11)>,
> -						 <STM32_PINMUX('A', 2, AF11)>,
> -						 <STM32_PINMUX('A', 1, AF11)>;
> -					slew-rate = <2>;
> -				};
> -			};
> -
> -			sdmmc1_b4_pins_a: sdmmc1-b4-0 {
> -				pins {
> -					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
> -						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
> -						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
> -						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
> -						 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
> -						 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
> -					slew-rate = <3>;
> -					drive-push-pull;
> -					bias-disable;
> -				};
> -			};
> -
> -			sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
> -				pins1 {
> -					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
> -						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
> -						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
> -						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
> -						 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
> -					slew-rate = <3>;
> -					drive-push-pull;
> -					bias-disable;
> -				};
> -				pins2{
> -					pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
> -					slew-rate = <3>;
> -					drive-open-drain;
> -					bias-disable;
> -				};
> -			};
> -
> -			sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
> -				pins {
> -					pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
> -						 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
> -						 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
> -						 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
> -						 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
> -						 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
> -				};
> -			};
> -
> -			sdmmc1_dir_pins_a: sdmmc1-dir-0 {
> -				pins1 {
> -					pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
> -						 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
> -						 <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
> -					slew-rate = <3>;
> -					drive-push-pull;
> -					bias-pull-up;
> -				};
> -				pins2{
> -					pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
> -					bias-pull-up;
> -				};
> -			};
> -
> -			sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
> -				pins {
> -					pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
> -						 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
> -						 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
> -						 <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
> -				};
> -			};
> -
> -			usart1_pins: usart1-0 {
> -				pins1 {
> -					pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
> -					bias-disable;
> -					drive-push-pull;
> -					slew-rate = <0>;
> -				};
> -				pins2 {
> -					pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
> -					bias-disable;
> -				};
> -			};
> -
> -			usart2_pins: usart2-0 {
> -				pins1 {
> -					pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
> -					bias-disable;
> -					drive-push-pull;
> -					slew-rate = <0>;
> -				};
> -				pins2 {
> -					pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
> -					bias-disable;
> -				};
> -			};
> -
> -			usbotg_hs_pins_a: usbotg-hs-0 {
> -				pins {
> -					pinmux = <STM32_PINMUX('H', 4, AF10)>,	/* ULPI_NXT */
> -							 <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
> -							 <STM32_PINMUX('C', 0, AF10)>,	/* ULPI_STP> */
> -							 <STM32_PINMUX('A', 5, AF10)>,	/* ULPI_CK> */
> -							 <STM32_PINMUX('A', 3, AF10)>,	/* ULPI_D0> */
> -							 <STM32_PINMUX('B', 0, AF10)>,	/* ULPI_D1> */
> -							 <STM32_PINMUX('B', 1, AF10)>,	/* ULPI_D2> */
> -							 <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
> -							 <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
> -							 <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
> -							 <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
> -							 <STM32_PINMUX('B', 5, AF10)>;	/* ULPI_D7> */
> -					bias-disable;
> -					drive-push-pull;
> -					slew-rate = <2>;
> -				};
> -			};
> -		};
> -	};
> +&pinctrl{
> +	compatible = "st,stm32h743-pinctrl";
>   };
> 

Re: [PATCH 7/8] ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6

[Alexandre TORGUE]

On 3/3/21 9:05 AM, dillon.minfei@gmail.com wrote:
> From: dillon min <dillon.minfei@gmail.com>
> 
> This patchset has following changes:
> 
> - add stm32h750i-art-pi.dtb
> - add dts binding usart3 for bt, uart4 for console
> - add dts binding sdmmc2 for wifi
> - add stm32h750-art-pi.dts to support art-pi board
> 
> board component:
> - 8MiB qspi flash
> - 16MiB spi flash
> - 32MiB sdram
> - ap6212 wifi&bt&fm
> 
> the detail board information can be found at:
> https://art-pi.gitee.io/website/
> 
> Signed-off-by: dillon min <dillon.minfei@gmail.com>
> ---
>   arch/arm/boot/dts/Makefile              |   1 +
>   arch/arm/boot/dts/stm32h743.dtsi        |  30 +++++
>   arch/arm/boot/dts/stm32h750.dtsi        |   5 +
>   arch/arm/boot/dts/stm32h750i-art-pi.dts | 224 ++++++++++++++++++++++++++++++++
>   4 files changed, 260 insertions(+)
>   create mode 100644 arch/arm/boot/dts/stm32h750.dtsi
>   create mode 100644 arch/arm/boot/dts/stm32h750i-art-pi.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 8e5d4ab4e75e..a19c5ab9df84 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1071,6 +1071,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
>   	stm32746g-eval.dtb \
>   	stm32h743i-eval.dtb \
>   	stm32h743i-disco.dtb \
> +	stm32h750i-art-pi.dtb \
>   	stm32mp153c-dhcom-drc02.dtb \
>   	stm32mp157a-avenger96.dtb \
>   	stm32mp157a-dhcor-avenger96.dtb \
> diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
> index 4ebffb0a45a3..981d44051007 100644
> --- a/arch/arm/boot/dts/stm32h743.dtsi
> +++ b/arch/arm/boot/dts/stm32h743.dtsi
> @@ -135,6 +135,22 @@
>   			clocks = <&rcc USART2_CK>;
>   		};
>   
> +		usart3: serial@40004800 {
> +			compatible = "st,stm32h7-uart";
> +			reg = <0x40004800 0x400>;
> +			interrupts = <39>;
> +			status = "disabled";
> +			clocks = <&rcc USART3_CK>;
> +		};
> +
> +		uart4: serial@40004c00 {
> +			compatible = "st,stm32h7-uart";
> +			reg = <0x40004c00 0x400>;
> +			interrupts = <52>;
> +			status = "disabled";
> +			clocks = <&rcc UART4_CK>;
> +		};
> +

Those peripherals are available on h743 ?

>   		i2c1: i2c@40005400 {
>   			compatible = "st,stm32f7-i2c";
>   			#address-cells = <1>;
> @@ -368,6 +384,20 @@
>   			max-frequency = <120000000>;
>   		};
>   
> +		sdmmc2: mmc@48022400 {
> +			compatible = "arm,pl18x", "arm,primecell";
> +			arm,primecell-periphid = <0x10153180>;
> +			reg = <0x48022400 0x400>;
> +			interrupts = <124>;
> +			interrupt-names	= "cmd_irq";
> +			clocks = <&rcc SDMMC2_CK>;
> +			clock-names = "apb_pclk";
> +			resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
> +			cap-sd-highspeed;
> +			cap-mmc-highspeed;
> +			max-frequency = <120000000>;
> +		};
> +
>   		exti: interrupt-controller@58000000 {
>   			compatible = "st,stm32h7-exti";
>   			interrupt-controller;
> diff --git a/arch/arm/boot/dts/stm32h750.dtsi b/arch/arm/boot/dts/stm32h750.dtsi
> new file mode 100644
> index 000000000000..dd9166223c2f
> --- /dev/null
> +++ b/arch/arm/boot/dts/stm32h750.dtsi
> @@ -0,0 +1,5 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
> +/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */
> +
> +#include "stm32h743.dtsi"
> +
> diff --git a/arch/arm/boot/dts/stm32h750i-art-pi.dts b/arch/arm/boot/dts/stm32h750i-art-pi.dts
> new file mode 100644
> index 000000000000..84cf70d7800c
> --- /dev/null
> +++ b/arch/arm/boot/dts/stm32h750i-art-pi.dts
> @@ -0,0 +1,224 @@
> +/*
> + * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "stm32h750.dtsi"
> +#include "stm32h750-pinctrl.dtsi"
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +	model = "RT-Thread STM32H750i-ART-PI board";
> +	compatible = "st,stm32h750i-art-pi", "st,stm32h750";
> +
> +	chosen {
> +		bootargs = "root=/dev/ram";
> +		stdout-path = "serial0:2000000n8";
> +	};
> +
> +	memory@c0000000 {
> +		device_type = "memory";
> +		reg = <0xc0000000 0x2000000>;
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		linux,cma {
> +			compatible = "shared-dma-pool";
> +			no-map;
> +			size = <0x100000>;
> +			linux,dma-default;
> +		};
> +	};
> +
> +	aliases {
> +		serial0 = &uart4;
> +		serial1 = &usart3;
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		led-red {
> +			gpios = <&gpioi 8 0>;
> +		};
> +		led-green {
> +			gpios = <&gpioc 15 0>;
> +			linux,default-trigger = "heartbeat";
> +		};
> +	};
> +
> +	v3v3: regulator-v3v3 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "v3v3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-always-on;
> +	};
> +
> +	wlan_pwr: regulator-wlan {
> +		compatible = "regulator-fixed";
> +
> +		regulator-name = "wl-reg";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +
> +		gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +	};
> +};
> +
> +&clk_hse {
> +	clock-frequency = <25000000>;
> +};
> +
> +&mac {
> +	status = "disabled";
> +	pinctrl-0	= <&ethernet_rmii>;
> +	pinctrl-names	= "default";
> +	phy-mode	= "rmii";
> +	phy-handle	= <&phy0>;
> +
> +	mdio0 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "snps,dwmac-mdio";
> +		phy0: ethernet-phy@0 {
> +			reg = <0>;
> +		};
> +	};
> +};
> +
> +&sdmmc1 {
> +	pinctrl-names = "default", "opendrain", "sleep";
> +	pinctrl-0 = <&sdmmc1_b4_pins_a>;
> +	pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
> +	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
> +	broken-cd;
> +	st,neg-edge;
> +	bus-width = <4>;
> +	vmmc-supply = <&v3v3>;
> +	status = "okay";
> +};
> +
> +&usart2 {
> +	pinctrl-0 = <&usart2_pins>;
> +	pinctrl-names = "default";
> +	status = "disabled";
> +};
> +
> +&uart4 {
> +	pinctrl-0 = <&uart4_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&dma1 {
> +	status = "okay";
> +};
> +

Would be better to order by name, but it is your board :)

> +&dma2 {
> +	status = "okay";
> +};
> +
> +&spi1 {
> +	status = "okay";
> +	pinctrl-0 = <&spi1_pins>;
> +	pinctrl-names = "default";
> +	cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
> +	dmas = <&dmamux1 37 0x400 0x05>,
> +	       <&dmamux1 38 0x400 0x05>;
> +	dma-names = "rx", "tx";
> +
> +	flash@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "winbond,w25q128", "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <80000000>;
> +
> +		partition@0 {
> +			label = "root filesystem";
> +			reg = <0 0x1000000>;
> +		};
> +	};
> +};
> +
> +&sdmmc2 {
> +	pinctrl-names = "default", "opendrain", "sleep";
> +	pinctrl-0 = <&sdmmc2_b4_pins_a>;
> +	pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
> +	pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
> +	broken-cd;
> +	non-removable;
> +	st,neg-edge;
> +	bus-width = <4>;
> +	vmmc-supply = <&wlan_pwr>;
> +	status = "okay";
> +
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	brcmf: bcrmf@1 {
> +		reg = <1>;
> +		compatible = "brcm,bcm4329-fmac";
> +	};
> +};
> +
> +&usart3 {
> +	/delete-property/st,hw-flow-ctrl;
> +	cts-gpios = <&gpiod 11 GPIO_ACTIVE_LOW>;
> +	rts-gpios = <&gpiod 12 GPIO_ACTIVE_LOW>;
> +	dmas = <&dmamux1 45 0x400 0x05>,
> +	       <&dmamux1 46 0x400 0x05>;
> +	dma-names = "rx", "tx";
> +	status = "okay";
> +
> +	bluetooth {
> +		host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>;
> +		device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
> +		shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>;
> +		compatible = "brcm,bcm43438-bt";
> +		max-speed = <115200>;
> +	};
> +};
> 

Re: [PATCH 8/8] ARM: stm32: add initial support for stm32h750

[Alexandre TORGUE]

Hi Dillon

On 3/3/21 9:05 AM, dillon.minfei@gmail.com wrote:
> From: dillon min <dillon.minfei@gmail.com>
> 

No empty commit message please

> Signed-off-by: dillon min <dillon.minfei@gmail.com>
> ---
>   arch/arm/mach-stm32/board-dt.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c
> index 011d57b488c2..a766310d8dca 100644
> --- a/arch/arm/mach-stm32/board-dt.c
> +++ b/arch/arm/mach-stm32/board-dt.c
> @@ -17,6 +17,7 @@ static const char *const stm32_compat[] __initconst = {
>   	"st,stm32f746",
>   	"st,stm32f769",
>   	"st,stm32h743",
> +	"st,stm32h750",
>   	"st,stm32mp157",
>   	NULL
>   };
> 

Re: [PATCH 0/8] ARM: STM32: add art-pi(stm32h750xbh6) board support

[dillon min]

Hi Alexandre,

Thanks for quickly responding.

On Thu, Mar 11, 2021 at 6:26 PM Alexandre TORGUE
<alexandre.torgue@st.com> wrote:
>
> Hi Dillon
>
> > -----Original Message-----
> > From: dillon min <dillon.minfei@gmail.com>
> > Sent: mercredi 10 mars 2021 12:48
> > To: Rob Herring <robh+dt@kernel.org>; Maxime Coquelin
> > <mcoquelin.stm32@gmail.com>; Alexandre TORGUE
> > <alexandre.torgue@st.com>; open list:OPEN FIRMWARE AND FLATTENED
> > DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; linux-stm32@st-md-
> > mailman.stormreply.com; Linux ARM <linux-arm-
> > kernel@lists.infradead.org>; Linux Kernel Mailing List <linux-
> > kernel@vger.kernel.org>; linux@armlinux.org.uk; Vladimir Murzin
> > <vladimir.murzin@arm.com>; afzal.mohd.ma@gmail.com
> > Subject: Re: [PATCH 0/8] ARM: STM32: add art-pi(stm32h750xbh6) board
> > support
> >
> > for the device tree part , still waiting review. just a gentle ping.
> > if Mr Alexandre torgue can take a look, would be great.
> >
>
> Sorry for the delay. For next versions can you send it to
> Alexandre.torgue@foss.st.com please
Okay, I will add your new e-mail address to next review mailing list.
>
> Thanks
> Alex
>
> > thanks,
> >
> > On Wed, Mar 3, 2021 at 4:05 PM <dillon.minfei@gmail.com> wrote:
> > >
> > > From: dillon min <dillon.minfei@gmail.com>
> > >
> > > This patchset intend to add art-pi board support, this board developed
> > > by rt-thread(https://www.rt-thread.org/).
> > >
> > > Board resources:
> > >
> > > 8MiB QSPI flash
> > > 16MiB SPI flash
> > > 32MiB SDRAM
> > > AP6212 wifi,bt,fm comb
> > >
> > > sw context:
> > > - as stm32h750 just has 128k bytes internal flash, so running a fw on
> > >   internal flash to download u-boot/kernel to qspi flash, boot
> > >   u-boot/kernel from qspi flash. this fw is based on rt-thread.
> > > - kernel can be xip on qspi flash or load to sdram
> > > - root filesystem is jffs2(created by buildroot), stored on spi flash
> > >
> > > to support the boad, add following changes.
> > > - fix r0-r3, r12 register restore failed after svc call,
> > > - add dts binding
> > > - update yaml doc
> > >
> > > dillon min (8):
> > >   ARM: ARMv7-M: Fix register restore corrupt after svc call
> > >   Documentation: arm: stm32: Add stm32h750 value line
> > >   dt-bindings: arm: stm32: Add compatible strings for ART-PI board
> > >   dt-bindings: pinctrl: stm32: Add stm32h750 pinctrl
> > >   ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h75x
> > >   ARM: dts: stm32: add stm32h750-pinctrl.dtsi
> > >   ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6
> > >   ARM: stm32: add initial support for stm32h750
> > >
> > >  Documentation/arm/index.rst                        |   1 +
> > >  Documentation/arm/stm32/stm32h750-overview.rst     |  33 ++
> > >  .../devicetree/bindings/arm/stm32/stm32.yaml       |   4 +
> > >  .../bindings/pinctrl/st,stm32-pinctrl.yaml         |   1 +
> > >  arch/arm/boot/dts/Makefile                         |   1 +
> > >  arch/arm/boot/dts/stm32h7-pinctrl.dtsi             | 392
> > +++++++++++++++++++++
> > >  arch/arm/boot/dts/stm32h743-pinctrl.dtsi           | 307 +---------------
> > >  arch/arm/boot/dts/stm32h743.dtsi                   |  30 ++
> > >  arch/arm/boot/dts/stm32h750-pinctrl.dtsi           |  11 +
> > >  arch/arm/boot/dts/stm32h750.dtsi                   |   5 +
> > >  arch/arm/boot/dts/stm32h750i-art-pi.dts            | 227 ++++++++++++
> > >  arch/arm/mach-stm32/board-dt.c                     |   1 +
> > >  arch/arm/mm/proc-v7m.S                             |   5 +-
> > >  13 files changed, 716 insertions(+), 302 deletions(-)  create mode
> > > 100644 Documentation/arm/stm32/stm32h750-overview.rst
> > >  create mode 100644 arch/arm/boot/dts/stm32h7-pinctrl.dtsi
> > >  create mode 100644 arch/arm/boot/dts/stm32h750-pinctrl.dtsi
> > >  create mode 100644 arch/arm/boot/dts/stm32h750.dtsi  create mode
> > > 100644 arch/arm/boot/dts/stm32h750i-art-pi.dts
> > >
> > > --
> > > 2.7.4
> > >

Re: [PATCH 5/8] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h75x

[dillon min]

Hi Alexandre

On Thu, Mar 11, 2021 at 6:40 PM Alexandre TORGUE
<alexandre.torgue@foss.st.com> wrote:
>
> Hi Dillon
>
> On 3/3/21 9:05 AM, dillon.minfei@gmail.com wrote:
> > From: dillon min <dillon.minfei@gmail.com>
> >
> > To support stm32h750 and stm32h743, we need a base stm32h7-pinctrl.dtsi
> > as stm32h743 & h750 has almost the same interface. so, just rename
> > stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi
> >
>
> You do not "just" rename but you keel also the old version. I don't
> agree with this approach. You have first to rename
> stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi (keeping copyright as
> they are please) and modify existing H7 boards which currently use
> stm32h743-pinctrl.dtsi.
> Then you create a second patch adding your pingroups.
For stm32h7's new board support , I guess following the stm32f7/stm32f4's style
is a reasonable way to do it, but add a little optimization。
which means :
old structure
stm32h7-pinctrl.dtsi --> stm32h743-pinctrl.dtsi  (referenced by
stm32h743i-disco, -eval)
                                |--> stm32h750-pinctrl.dtsi
(referenced by stm32h750i-art-pi, etc)
add art-pi other board's pin definition in stm32h750-pinctrl.dtsi with
xxx_pins_a, xxx_pins_b
xxx_pins_a used for art-pi, xxx_pins_b used for other boards.

after more boards add in support, there will be more xxx_pin_c, .... defined

as the pin map is according to the hardware schematic diagram io connection.
so, why not move xxx_pin_x to a board specific place. such as
stm32h750i-art-pi.dts

new structure:
1, rename stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi (only
preserve gpioa...k,)
2, move xxx_pins_x from stm32h7-pinctrl.dtsi to
stm32h7xx-disco/eval/art-pi/etc.dts (as they depends on hardware
schematic)

stm32h7-pinctrl.dtsi --> stm32h743i-discon.dts
                                |--> stm32h743i-eval.dts
                                |--> stm32h750i-art-pi.dts
                                |--> stm32h7xxx.dts
would you agree this ?
>
> Now regarding "st,stm32h750-pinctrl", I see a patch dealing with this
> new binding but no update on driver side. Do I miss something ? what are
> differences between h743 and h750 regarding pinctrl ?
Oh, i forget to add pin driver under drivers/pinctrl/stm32/
will add it next time.
>
> Regards
> Alex
>
> > Signed-off-by: dillon min <dillon.minfei@gmail.com>
> > ---
> >   arch/arm/boot/dts/stm32h7-pinctrl.dtsi   | 392 +++++++++++++++++++++++++++++++
> >   arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 307 +-----------------------
> >   2 files changed, 398 insertions(+), 301 deletions(-)
> >   create mode 100644 arch/arm/boot/dts/stm32h7-pinctrl.dtsi
> >
> > diff --git a/arch/arm/boot/dts/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi
> > new file mode 100644
> > index 000000000000..7d4b5d683ccc
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi
> > @@ -0,0 +1,392 @@
> > +/*
> > + * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
> > + *
> > + * This file is dual-licensed: you can use it either under the terms
> > + * of the GPL or the X11 license, at your option. Note that this dual
> > + * licensing only applies to this file, and not this project as a
> > + * whole.
> > + *
> > + *  a) This file is free software; you can redistribute it and/or
> > + *     modify it under the terms of the GNU General Public License as
> > + *     published by the Free Software Foundation; either version 2 of the
> > + *     License, or (at your option) any later version.
> > + *
> > + *     This file is distributed in the hope that it will be useful,
> > + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + *     GNU General Public License for more details.
> > + *
> > + * Or, alternatively,
> > + *
> > + *  b) Permission is hereby granted, free of charge, to any person
> > + *     obtaining a copy of this software and associated documentation
> > + *     files (the "Software"), to deal in the Software without
> > + *     restriction, including without limitation the rights to use,
> > + *     copy, modify, merge, publish, distribute, sublicense, and/or
> > + *     sell copies of the Software, and to permit persons to whom the
> > + *     Software is furnished to do so, subject to the following
> > + *     conditions:
> > + *
> > + *     The above copyright notice and this permission notice shall be
> > + *     included in all copies or substantial portions of the Software.
> > + *
> > + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> > + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> > + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + *     OTHER DEALINGS IN THE SOFTWARE.
> > + */
> > +
> > +#include <dt-bindings/pinctrl/stm32-pinfunc.h>
> > +
> > +/ {
> > +     soc {
> > +             pinctrl: pin-controller {
> > +                     #address-cells = <1>;
> > +                     #size-cells = <1>;
> > +                     ranges = <0 0x58020000 0x3000>;
> > +                     interrupt-parent = <&exti>;
> > +                     st,syscfg = <&syscfg 0x8>;
> > +                     pins-are-numbered;
> > +
> > +                     gpioa: gpio@58020000 {
> > +                             gpio-controller;
> > +                             #gpio-cells = <2>;
> > +                             reg = <0x0 0x400>;
> > +                             clocks = <&rcc GPIOA_CK>;
> > +                             st,bank-name = "GPIOA";
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <2>;
> > +                     };
> > +
> > +                     gpiob: gpio@58020400 {
> > +                             gpio-controller;
> > +                             #gpio-cells = <2>;
> > +                             reg = <0x400 0x400>;
> > +                             clocks = <&rcc GPIOB_CK>;
> > +                             st,bank-name = "GPIOB";
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <2>;
> > +                     };
> > +
> > +                     gpioc: gpio@58020800 {
> > +                             gpio-controller;
> > +                             #gpio-cells = <2>;
> > +                             reg = <0x800 0x400>;
> > +                             clocks = <&rcc GPIOC_CK>;
> > +                             st,bank-name = "GPIOC";
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <2>;
> > +                     };
> > +
> > +                     gpiod: gpio@58020c00 {
> > +                             gpio-controller;
> > +                             #gpio-cells = <2>;
> > +                             reg = <0xc00 0x400>;
> > +                             clocks = <&rcc GPIOD_CK>;
> > +                             st,bank-name = "GPIOD";
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <2>;
> > +                     };
> > +
> > +                     gpioe: gpio@58021000 {
> > +                             gpio-controller;

> > +                             reg = <0x1000 0x400>;
> > +                             clocks = <&rcc GPIOE_CK>;
> > +                             st,bank-name = "GPIOE";
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <2>;
> > +                     };
> > +
> > +                     gpiof: gpio@58021400 {
> > +                             gpio-controller;
> > +                             #gpio-cells = <2>;
> > +                             reg = <0x1400 0x400>;
> > +                             clocks = <&rcc GPIOF_CK>;
> > +                             st,bank-name = "GPIOF";
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <2>;
> > +                     };
> > +
> > +                     gpiog: gpio@58021800 {
> > +                             gpio-controller;
> > +                             #gpio-cells = <2>;
> > +                             reg = <0x1800 0x400>;
> > +                             clocks = <&rcc GPIOG_CK>;
> > +                             st,bank-name = "GPIOG";
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <2>;
> > +                     };
> > +
> > +                     gpioh: gpio@58021c00 {
> > +                             gpio-controller;
> > +                             #gpio-cells = <2>;
> > +                             reg = <0x1c00 0x400>;
> > +                             clocks = <&rcc GPIOH_CK>;
> > +                             st,bank-name = "GPIOH";
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <2>;
> > +                     };
> > +
> > +                     gpioi: gpio@58022000 {
> > +                             gpio-controller;
> > +                             #gpio-cells = <2>;
> > +                             reg = <0x2000 0x400>;
> > +                             clocks = <&rcc GPIOI_CK>;
> > +                             st,bank-name = "GPIOI";
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <2>;
> > +                     };
> > +
> > +                     gpioj: gpio@58022400 {
> > +                             gpio-controller;
> > +                             #gpio-cells = <2>;
> > +                             reg = <0x2400 0x400>;
> > +                             clocks = <&rcc GPIOJ_CK>;
> > +                             st,bank-name = "GPIOJ";
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <2>;
> > +                     };
> > +
> > +                     gpiok: gpio@58022800 {
> > +                             gpio-controller;
> > +                             #gpio-cells = <2>;
> > +                             reg = <0x2800 0x400>;
> > +                             clocks = <&rcc GPIOK_CK>;
> > +                             st,bank-name = "GPIOK";
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <2>;
> > +                     };
> > +
> > +                     i2c1_pins_a: i2c1-0 {
> > +                             pins {
> > +                                     pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
> > +                                              <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
> > +                                     bias-disable;
> > +                                     drive-open-drain;
> > +                                     slew-rate = <0>;
> > +                             };
> > +                     };
> > +
> > +                     ethernet_rmii: rmii-0 {
> > +                             pins {
> > +                                     pinmux = <STM32_PINMUX('G', 11, AF11)>,
> > +                                              <STM32_PINMUX('G', 13, AF11)>,
> > +                                              <STM32_PINMUX('G', 12, AF11)>,
> > +                                              <STM32_PINMUX('C', 4, AF11)>,
> > +                                              <STM32_PINMUX('C', 5, AF11)>,
> > +                                              <STM32_PINMUX('A', 7, AF11)>,
> > +                                              <STM32_PINMUX('C', 1, AF11)>,
> > +                                              <STM32_PINMUX('A', 2, AF11)>,
> > +                                              <STM32_PINMUX('A', 1, AF11)>;
> > +                                     slew-rate = <2>;
> > +                             };
> > +                     };
> > +
> > +                     sdmmc1_b4_pins_a: sdmmc1-b4-0 {
> > +                             pins {
> > +                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
> > +                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
> > +                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
> > +                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
> > +                                              <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
> > +                                              <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
> > +                                     slew-rate = <3>;
> > +                                     drive-push-pull;
> > +                                     bias-disable;
> > +                             };
> > +                     };
> > +
> > +                     sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
> > +                             pins1 {
> > +                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
> > +                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
> > +                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
> > +                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
> > +                                              <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
> > +                                     slew-rate = <3>;
> > +                                     drive-push-pull;
> > +                                     bias-disable;
> > +                             };
> > +                             pins2{
> > +                                     pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
> > +                                     slew-rate = <3>;
> > +                                     drive-open-drain;
> > +                                     bias-disable;
> > +                             };
> > +                     };
> > +
> > +                     sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
> > +                             pins {
> > +                                     pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
> > +                                              <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
> > +                                              <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
> > +                                              <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
> > +                                              <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
> > +                                              <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
> > +                             };
> > +                     };
> > +
> > +                     sdmmc2_b4_pins_a: sdmmc2-b4-0 {
> > +                             pins {
> > +                                     pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */
> > +                                              <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
> > +                                              <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
> > +                                              <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
> > +                                              <STM32_PINMUX('D', 6, AF11)>, /* SDMMC1_CK */
> > +                                              <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
> > +                                     slew-rate = <3>;
> > +                                     drive-push-pull;
> > +                                     bias-disable;
> > +                             };
> > +                     };
> > +
> > +                     sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
> > +                             pins1 {
> > +                                     pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
> > +                                              <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
> > +                                              <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
> > +                                              <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
> > +                                              <STM32_PINMUX('D', 6, AF11)>; /* SDMMC1_CK */
> > +                                     slew-rate = <3>;
> > +                                     drive-push-pull;
> > +                                     bias-disable;
> > +                             };
> > +                             pins2{
> > +                                     pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
> > +                                     slew-rate = <3>;
> > +                                     drive-open-drain;
> > +                                     bias-disable;
> > +                             };
> > +                     };
> > +
> > +                     sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
> > +                             pins {
> > +                                     pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC1_D0 */
> > +                                              <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC1_D1 */
> > +                                              <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC1_D2 */
> > +                                              <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC1_D3 */
> > +                                              <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC1_CK */
> > +                                              <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC1_CMD */
> > +                             };
> > +                     };
> > +
> > +                     sdmmc1_dir_pins_a: sdmmc1-dir-0 {
> > +                             pins1 {
> > +                                     pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
> > +                                              <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
> > +                                              <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
> > +                                     slew-rate = <3>;
> > +                                     drive-push-pull;
> > +                                     bias-pull-up;
> > +                             };
> > +                             pins2{
> > +                                     pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
> > +                                     bias-pull-up;
> > +                             };
> > +                     };
> > +
> > +                     sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
> > +                             pins {
> > +                                     pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
> > +                                              <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
> > +                                              <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
> > +                                              <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
> > +                             };
> > +                     };
> > +
> > +                     usart1_pins: usart1-0 {
> > +                             pins1 {
> > +                                     pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
> > +                                     bias-disable;
> > +                                     drive-push-pull;
> > +                                     slew-rate = <0>;
> > +                             };
> > +                             pins2 {
> > +                                     pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
> > +                                     bias-disable;
> > +                             };
> > +                     };
> > +
> > +                     usart2_pins: usart2-0 {
> > +                             pins1 {
> > +                                     pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
> > +                                     bias-disable;
> > +                                     drive-push-pull;
> > +                                     slew-rate = <0>;
> > +                             };
> > +                             pins2 {
> > +                                     pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
> > +                                     bias-disable;
> > +                             };
> > +                     };
> > +
> > +                     usart3_pins: usart3-0 {
> > +                             pins1 {
> > +                                     pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
> > +                                     bias-disable;
> > +                                     drive-push-pull;
> > +                                     slew-rate = <0>;
> > +                             };
> > +                             pins2 {
> > +                                     pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
> > +                                     bias-disable;
> > +                             };
> > +                     };
> > +
> > +                     uart4_pins: uart4-0 {
> > +                             pins1 {
> > +                                     pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */
> > +                                     bias-disable;
> > +                                     drive-push-pull;
> > +                                     slew-rate = <0>;
> > +                             };
> > +                             pins2 {
> > +                                     pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */
> > +                                     bias-disable;
> > +                             };
> > +                     };
> > +
> > +                     usbotg_hs_pins_a: usbotg-hs-0 {
> > +                             pins {
> > +                                     pinmux = <STM32_PINMUX('H', 4, AF10)>,  /* ULPI_NXT */
> > +                                                      <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
> > +                                                      <STM32_PINMUX('C', 0, AF10)>,  /* ULPI_STP> */
> > +                                                      <STM32_PINMUX('A', 5, AF10)>,  /* ULPI_CK> */
> > +                                                      <STM32_PINMUX('A', 3, AF10)>,  /* ULPI_D0> */
> > +                                                      <STM32_PINMUX('B', 0, AF10)>,  /* ULPI_D1> */
> > +                                                      <STM32_PINMUX('B', 1, AF10)>,  /* ULPI_D2> */
> > +                                                      <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
> > +                                                      <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
> > +                                                      <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
> > +                                                      <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
> > +                                                      <STM32_PINMUX('B', 5, AF10)>;  /* ULPI_D7> */
> > +                                     bias-disable;
> > +                                     drive-push-pull;
> > +                                     slew-rate = <2>;
> > +                             };
> > +                     };
> > +
> > +                     spi1_pins: spi1-0 {
> > +                             pins1 {
> > +                                     pinmux = <STM32_PINMUX('A', 5, AF5)>,
> > +                                             /* SPI1_CLK */
> > +                                              <STM32_PINMUX('B', 5, AF5)>;
> > +                                             /* SPI1_MOSI */
> > +                                     bias-disable;
> > +                                     drive-push-pull;
> > +                                     slew-rate = <2>;
> > +                             };
> > +                             pins2 {
> > +                                     pinmux = <STM32_PINMUX('G', 9, AF5)>;
> > +                                             /* SPI1_MISO */
> > +                                     bias-disable;
> > +                             };
> > +                     };
> > +             };
> > +     };
> > +};
> > diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
> > index fa5dcb6a5fdd..6b1e115307b9 100644
> > --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
> > +++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
> > @@ -1,306 +1,11 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> >   /*
> > - * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
> > - *
> > - * This file is dual-licensed: you can use it either under the terms
> > - * of the GPL or the X11 license, at your option. Note that this dual
> > - * licensing only applies to this file, and not this project as a
> > - * whole.
> > - *
> > - *  a) This file is free software; you can redistribute it and/or
> > - *     modify it under the terms of the GNU General Public License as
> > - *     published by the Free Software Foundation; either version 2 of the
> > - *     License, or (at your option) any later version.
> > - *
> > - *     This file is distributed in the hope that it will be useful,
> > - *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> > - *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > - *     GNU General Public License for more details.
> > - *
> > - * Or, alternatively,
> > - *
> > - *  b) Permission is hereby granted, free of charge, to any person
> > - *     obtaining a copy of this software and associated documentation
> > - *     files (the "Software"), to deal in the Software without
> > - *     restriction, including without limitation the rights to use,
> > - *     copy, modify, merge, publish, distribute, sublicense, and/or
> > - *     sell copies of the Software, and to permit persons to whom the
> > - *     Software is furnished to do so, subject to the following
> > - *     conditions:
> > - *
> > - *     The above copyright notice and this permission notice shall be
> > - *     included in all copies or substantial portions of the Software.
> > - *
> > - *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > - *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> > - *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > - *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> > - *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > - *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > - *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > - *     OTHER DEALINGS IN THE SOFTWARE.
> > + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
> > + * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
> >    */
> >
> > -#include <dt-bindings/pinctrl/stm32-pinfunc.h>
> > +#include "stm32h7-pinctrl.dtsi"
> >
> > -/ {
> > -     soc {
> > -             pin-controller {
> > -                     #address-cells = <1>;
> > -                     #size-cells = <1>;
> > -                     compatible = "st,stm32h743-pinctrl";
> > -                     ranges = <0 0x58020000 0x3000>;
> > -                     interrupt-parent = <&exti>;
> > -                     st,syscfg = <&syscfg 0x8>;
> > -                     pins-are-numbered;
> > -
> > -                     gpioa: gpio@58020000 {
> > -                             gpio-controller;
> > -                             #gpio-cells = <2>;
> > -                             reg = <0x0 0x400>;
> > -                             clocks = <&rcc GPIOA_CK>;
> > -                             st,bank-name = "GPIOA";
> > -                             interrupt-controller;
> > -                             #interrupt-cells = <2>;
> > -                     };
> > -
> > -                     gpiob: gpio@58020400 {
> > -                             gpio-controller;
> > -                             #gpio-cells = <2>;
> > -                             reg = <0x400 0x400>;
> > -                             clocks = <&rcc GPIOB_CK>;
> > -                             st,bank-name = "GPIOB";
> > -                             interrupt-controller;
> > -                             #interrupt-cells = <2>;
> > -                     };
> > -
> > -                     gpioc: gpio@58020800 {
> > -                             gpio-controller;
> > -                             #gpio-cells = <2>;
> > -                             reg = <0x800 0x400>;
> > -                             clocks = <&rcc GPIOC_CK>;
> > -                             st,bank-name = "GPIOC";
> > -                             interrupt-controller;
> > -                             #interrupt-cells = <2>;
> > -                     };
> > -
> > -                     gpiod: gpio@58020c00 {
> > -                             gpio-controller;
> > -                             #gpio-cells = <2>;
> > -                             reg = <0xc00 0x400>;
> > -                             clocks = <&rcc GPIOD_CK>;
> > -                             st,bank-name = "GPIOD";
> > -                             interrupt-controller;
> > -                             #interrupt-cells = <2>;
> > -                     };
> > -
> > -                     gpioe: gpio@58021000 {
> > -                             gpio-controller;
> > -                             #gpio-cells = <2>;
> > -                             reg = <0x1000 0x400>;
> > -                             clocks = <&rcc GPIOE_CK>;
> > -                             st,bank-name = "GPIOE";
> > -                             interrupt-controller;
> > -                             #interrupt-cells = <2>;
> > -                     };
> > -
> > -                     gpiof: gpio@58021400 {
> > -                             gpio-controller;
> > -                             #gpio-cells = <2>;
> > -                             reg = <0x1400 0x400>;
> > -                             clocks = <&rcc GPIOF_CK>;
> > -                             st,bank-name = "GPIOF";
> > -                             interrupt-controller;
> > -                             #interrupt-cells = <2>;
> > -                     };
> > -
> > -                     gpiog: gpio@58021800 {
> > -                             gpio-controller;
> > -                             #gpio-cells = <2>;
> > -                             reg = <0x1800 0x400>;
> > -                             clocks = <&rcc GPIOG_CK>;
> > -                             st,bank-name = "GPIOG";
> > -                             interrupt-controller;
> > -                             #interrupt-cells = <2>;
> > -                     };
> > -
> > -                     gpioh: gpio@58021c00 {
> > -                             gpio-controller;
> > -                             #gpio-cells = <2>;
> > -                             reg = <0x1c00 0x400>;
> > -                             clocks = <&rcc GPIOH_CK>;
> > -                             st,bank-name = "GPIOH";
> > -                             interrupt-controller;
> > -                             #interrupt-cells = <2>;
> > -                     };
> > -
> > -                     gpioi: gpio@58022000 {
> > -                             gpio-controller;
> > -                             #gpio-cells = <2>;
> > -                             reg = <0x2000 0x400>;
> > -                             clocks = <&rcc GPIOI_CK>;
> > -                             st,bank-name = "GPIOI";
> > -                             interrupt-controller;
> > -                             #interrupt-cells = <2>;
> > -                     };
> > -
> > -                     gpioj: gpio@58022400 {
> > -                             gpio-controller;
> > -                             #gpio-cells = <2>;
> > -                             reg = <0x2400 0x400>;
> > -                             clocks = <&rcc GPIOJ_CK>;
> > -                             st,bank-name = "GPIOJ";
> > -                             interrupt-controller;
> > -                             #interrupt-cells = <2>;
> > -                     };
> > -
> > -                     gpiok: gpio@58022800 {
> > -                             gpio-controller;
> > -                             #gpio-cells = <2>;
> > -                             reg = <0x2800 0x400>;
> > -                             clocks = <&rcc GPIOK_CK>;
> > -                             st,bank-name = "GPIOK";
> > -                             interrupt-controller;
> > -                             #interrupt-cells = <2>;
> > -                     };
> > -
> > -                     i2c1_pins_a: i2c1-0 {
> > -                             pins {
> > -                                     pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
> > -                                              <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
> > -                                     bias-disable;
> > -                                     drive-open-drain;
> > -                                     slew-rate = <0>;
> > -                             };
> > -                     };
> > -
> > -                     ethernet_rmii: rmii-0 {
> > -                             pins {
> > -                                     pinmux = <STM32_PINMUX('G', 11, AF11)>,
> > -                                              <STM32_PINMUX('G', 13, AF11)>,
> > -                                              <STM32_PINMUX('G', 12, AF11)>,
> > -                                              <STM32_PINMUX('C', 4, AF11)>,
> > -                                              <STM32_PINMUX('C', 5, AF11)>,
> > -                                              <STM32_PINMUX('A', 7, AF11)>,
> > -                                              <STM32_PINMUX('C', 1, AF11)>,
> > -                                              <STM32_PINMUX('A', 2, AF11)>,
> > -                                              <STM32_PINMUX('A', 1, AF11)>;
> > -                                     slew-rate = <2>;
> > -                             };
> > -                     };
> > -
> > -                     sdmmc1_b4_pins_a: sdmmc1-b4-0 {
> > -                             pins {
> > -                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
> > -                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
> > -                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
> > -                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
> > -                                              <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
> > -                                              <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
> > -                                     slew-rate = <3>;
> > -                                     drive-push-pull;
> > -                                     bias-disable;
> > -                             };
> > -                     };
> > -
> > -                     sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
> > -                             pins1 {
> > -                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
> > -                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
> > -                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
> > -                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
> > -                                              <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
> > -                                     slew-rate = <3>;
> > -                                     drive-push-pull;
> > -                                     bias-disable;
> > -                             };
> > -                             pins2{
> > -                                     pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
> > -                                     slew-rate = <3>;
> > -                                     drive-open-drain;
> > -                                     bias-disable;
> > -                             };
> > -                     };
> > -
> > -                     sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
> > -                             pins {
> > -                                     pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
> > -                                              <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
> > -                                              <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
> > -                                              <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
> > -                                              <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
> > -                                              <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
> > -                             };
> > -                     };
> > -
> > -                     sdmmc1_dir_pins_a: sdmmc1-dir-0 {
> > -                             pins1 {
> > -                                     pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
> > -                                              <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
> > -                                              <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
> > -                                     slew-rate = <3>;
> > -                                     drive-push-pull;
> > -                                     bias-pull-up;
> > -                             };
> > -                             pins2{
> > -                                     pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
> > -                                     bias-pull-up;
> > -                             };
> > -                     };
> > -
> > -                     sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
> > -                             pins {
> > -                                     pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
> > -                                              <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
> > -                                              <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
> > -                                              <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
> > -                             };
> > -                     };
> > -
> > -                     usart1_pins: usart1-0 {
> > -                             pins1 {
> > -                                     pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
> > -                                     bias-disable;
> > -                                     drive-push-pull;
> > -                                     slew-rate = <0>;
> > -                             };
> > -                             pins2 {
> > -                                     pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
> > -                                     bias-disable;
> > -                             };
> > -                     };
> > -
> > -                     usart2_pins: usart2-0 {
> > -                             pins1 {
> > -                                     pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
> > -                                     bias-disable;
> > -                                     drive-push-pull;
> > -                                     slew-rate = <0>;
> > -                             };
> > -                             pins2 {
> > -                                     pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
> > -                                     bias-disable;
> > -                             };
> > -                     };
> > -
> > -                     usbotg_hs_pins_a: usbotg-hs-0 {
> > -                             pins {
> > -                                     pinmux = <STM32_PINMUX('H', 4, AF10)>,  /* ULPI_NXT */
> > -                                                      <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
> > -                                                      <STM32_PINMUX('C', 0, AF10)>,  /* ULPI_STP> */
> > -                                                      <STM32_PINMUX('A', 5, AF10)>,  /* ULPI_CK> */
> > -                                                      <STM32_PINMUX('A', 3, AF10)>,  /* ULPI_D0> */
> > -                                                      <STM32_PINMUX('B', 0, AF10)>,  /* ULPI_D1> */
> > -                                                      <STM32_PINMUX('B', 1, AF10)>,  /* ULPI_D2> */
> > -                                                      <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
> > -                                                      <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
> > -                                                      <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
> > -                                                      <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
> > -                                                      <STM32_PINMUX('B', 5, AF10)>;  /* ULPI_D7> */
> > -                                     bias-disable;
> > -                                     drive-push-pull;
> > -                                     slew-rate = <2>;
> > -                             };
> > -                     };
> > -             };
> > -     };
> > +&pinctrl{
> > +     compatible = "st,stm32h743-pinctrl";
> >   };
> >

Re: [PATCH 7/8] ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6

[dillon min]

Hi Alexandre

On Thu, Mar 11, 2021 at 6:42 PM Alexandre TORGUE
<alexandre.torgue@foss.st.com> wrote:
>
>
>
> On 3/3/21 9:05 AM, dillon.minfei@gmail.com wrote:
> > From: dillon min <dillon.minfei@gmail.com>
> >
> > This patchset has following changes:
> >
> > - add stm32h750i-art-pi.dtb
> > - add dts binding usart3 for bt, uart4 for console
> > - add dts binding sdmmc2 for wifi
> > - add stm32h750-art-pi.dts to support art-pi board
> >
> > board component:
> > - 8MiB qspi flash
> > - 16MiB spi flash
> > - 32MiB sdram
> > - ap6212 wifi&bt&fm
> >
> > the detail board information can be found at:
> > https://art-pi.gitee.io/website/
> >
> > Signed-off-by: dillon min <dillon.minfei@gmail.com>
> > ---
> >   arch/arm/boot/dts/Makefile              |   1 +
> >   arch/arm/boot/dts/stm32h743.dtsi        |  30 +++++
> >   arch/arm/boot/dts/stm32h750.dtsi        |   5 +
> >   arch/arm/boot/dts/stm32h750i-art-pi.dts | 224 ++++++++++++++++++++++++++++++++
> >   4 files changed, 260 insertions(+)
> >   create mode 100644 arch/arm/boot/dts/stm32h750.dtsi
> >   create mode 100644 arch/arm/boot/dts/stm32h750i-art-pi.dts
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 8e5d4ab4e75e..a19c5ab9df84 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -1071,6 +1071,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
> >       stm32746g-eval.dtb \
> >       stm32h743i-eval.dtb \
> >       stm32h743i-disco.dtb \
> > +     stm32h750i-art-pi.dtb \
> >       stm32mp153c-dhcom-drc02.dtb \
> >       stm32mp157a-avenger96.dtb \
> >       stm32mp157a-dhcor-avenger96.dtb \
> > diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
> > index 4ebffb0a45a3..981d44051007 100644
> > --- a/arch/arm/boot/dts/stm32h743.dtsi
> > +++ b/arch/arm/boot/dts/stm32h743.dtsi
> > @@ -135,6 +135,22 @@
> >                       clocks = <&rcc USART2_CK>;
> >               };
> >
> > +             usart3: serial@40004800 {
> > +                     compatible = "st,stm32h7-uart";
> > +                     reg = <0x40004800 0x400>;
> > +                     interrupts = <39>;
> > +                     status = "disabled";
> > +                     clocks = <&rcc USART3_CK>;
> > +             };
> > +
> > +             uart4: serial@40004c00 {
> > +                     compatible = "st,stm32h7-uart";
> > +                     reg = <0x40004c00 0x400>;
> > +                     interrupts = <52>;
> > +                     status = "disabled";
> > +                     clocks = <&rcc UART4_CK>;
> > +             };
> > +
>
> Those peripherals are available on h743 ?
Yes, available for stm32h743, but might not used by stm32h743i-disco board.
the difference between stm32h743xi and stm32h750xb:
 flash size:  2048/128,
ad convter : none/3
crypto-hash: none/aes,hmac,....

>
> >               i2c1: i2c@40005400 {
> >                       compatible = "st,stm32f7-i2c";
> >                       #address-cells = <1>;
> > @@ -368,6 +384,20 @@
> >                       max-frequency = <120000000>;
> >               };
> >
> > +             sdmmc2: mmc@48022400 {
> > +                     compatible = "arm,pl18x", "arm,primecell";
> > +                     arm,primecell-periphid = <0x10153180>;
> > +                     reg = <0x48022400 0x400>;
> > +                     interrupts = <124>;
> > +                     interrupt-names = "cmd_irq";
> > +                     clocks = <&rcc SDMMC2_CK>;
> > +                     clock-names = "apb_pclk";
> > +                     resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
> > +                     cap-sd-highspeed;
> > +                     cap-mmc-highspeed;
> > +                     max-frequency = <120000000>;
> > +             };
> > +
> >               exti: interrupt-controller@58000000 {
> >                       compatible = "st,stm32h7-exti";
> >                       interrupt-controller;
> > diff --git a/arch/arm/boot/dts/stm32h750.dtsi b/arch/arm/boot/dts/stm32h750.dtsi
> > new file mode 100644
> > index 000000000000..dd9166223c2f
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/stm32h750.dtsi
> > @@ -0,0 +1,5 @@
> > +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
> > +/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */
> > +
> > +#include "stm32h743.dtsi"
> > +
> > diff --git a/arch/arm/boot/dts/stm32h750i-art-pi.dts b/arch/arm/boot/dts/stm32h750i-art-pi.dts
> > new file mode 100644
> > index 000000000000..84cf70d7800c
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/stm32h750i-art-pi.dts
> > @@ -0,0 +1,224 @@
> > +/*
> > + * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
> > + *
> > + * This file is dual-licensed: you can use it either under the terms
> > + * of the GPL or the X11 license, at your option. Note that this dual
> > + * licensing only applies to this file, and not this project as a
> > + * whole.
> > + *
> > + *  a) This file is free software; you can redistribute it and/or
> > + *     modify it under the terms of the GNU General Public License as
> > + *     published by the Free Software Foundation; either version 2 of the
> > + *     License, or (at your option) any later version.
> > + *
> > + *     This file is distributed in the hope that it will be useful,
> > + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + *     GNU General Public License for more details.
> > + *
> > + * Or, alternatively,
> > + *
> > + *  b) Permission is hereby granted, free of charge, to any person
> > + *     obtaining a copy of this software and associated documentation
> > + *     files (the "Software"), to deal in the Software without
> > + *     restriction, including without limitation the rights to use,
> > + *     copy, modify, merge, publish, distribute, sublicense, and/or
> > + *     sell copies of the Software, and to permit persons to whom the
> > + *     Software is furnished to do so, subject to the following
> > + *     conditions:
> > + *
> > + *     The above copyright notice and this permission notice shall be
> > + *     included in all copies or substantial portions of the Software.
> > + *
> > + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> > + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> > + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + *     OTHER DEALINGS IN THE SOFTWARE.
> > + */
> > +
> > +/dts-v1/;
> > +#include "stm32h750.dtsi"
> > +#include "stm32h750-pinctrl.dtsi"
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> > +/ {
> > +     model = "RT-Thread STM32H750i-ART-PI board";
> > +     compatible = "st,stm32h750i-art-pi", "st,stm32h750";
> > +
> > +     chosen {
> > +             bootargs = "root=/dev/ram";
> > +             stdout-path = "serial0:2000000n8";
> > +     };
> > +
> > +     memory@c0000000 {
> > +             device_type = "memory";
> > +             reg = <0xc0000000 0x2000000>;
> > +     };
> > +
> > +     reserved-memory {
> > +             #address-cells = <1>;
> > +             #size-cells = <1>;
> > +             ranges;
> > +
> > +             linux,cma {
> > +                     compatible = "shared-dma-pool";
> > +                     no-map;
> > +                     size = <0x100000>;
> > +                     linux,dma-default;
> > +             };
> > +     };
> > +
> > +     aliases {
> > +             serial0 = &uart4;
> > +             serial1 = &usart3;
> > +     };
> > +
> > +     leds {
> > +             compatible = "gpio-leds";
> > +             led-red {
> > +                     gpios = <&gpioi 8 0>;
> > +             };
> > +             led-green {
> > +                     gpios = <&gpioc 15 0>;
> > +                     linux,default-trigger = "heartbeat";
> > +             };
> > +     };
> > +
> > +     v3v3: regulator-v3v3 {
> > +             compatible = "regulator-fixed";
> > +             regulator-name = "v3v3";
> > +             regulator-min-microvolt = <3300000>;
> > +             regulator-max-microvolt = <3300000>;
> > +             regulator-always-on;
> > +     };
> > +
> > +     wlan_pwr: regulator-wlan {
> > +             compatible = "regulator-fixed";
> > +
> > +             regulator-name = "wl-reg";
> > +             regulator-min-microvolt = <3300000>;
> > +             regulator-max-microvolt = <3300000>;
> > +
> > +             gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
> > +             enable-active-high;
> > +     };
> > +};
> > +
> > +&clk_hse {
> > +     clock-frequency = <25000000>;
> > +};
> > +
> > +&mac {
> > +     status = "disabled";
> > +     pinctrl-0       = <&ethernet_rmii>;
> > +     pinctrl-names   = "default";
> > +     phy-mode        = "rmii";
> > +     phy-handle      = <&phy0>;
> > +
> > +     mdio0 {
> > +             #address-cells = <1>;
> > +             #size-cells = <0>;
> > +             compatible = "snps,dwmac-mdio";
> > +             phy0: ethernet-phy@0 {
> > +                     reg = <0>;
> > +             };
> > +     };
> > +};
> > +
> > +&sdmmc1 {
> > +     pinctrl-names = "default", "opendrain", "sleep";
> > +     pinctrl-0 = <&sdmmc1_b4_pins_a>;
> > +     pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
> > +     pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
> > +     broken-cd;
> > +     st,neg-edge;
> > +     bus-width = <4>;
> > +     vmmc-supply = <&v3v3>;
> > +     status = "okay";
> > +};
> > +
> > +&usart2 {
> > +     pinctrl-0 = <&usart2_pins>;
> > +     pinctrl-names = "default";
> > +     status = "disabled";
> > +};
> > +
> > +&uart4 {
> > +     pinctrl-0 = <&uart4_pins>;
> > +     pinctrl-names = "default";
> > +     status = "okay";
> > +};
> > +
> > +&dma1 {
> > +     status = "okay";
> > +};
> > +
>
> Would be better to order by name, but it is your board :)
Okay, i will follow stm32f7/f4's order next submit.
>
> > +&dma2 {
> > +     status = "okay";
> > +};
> > +
> > +&spi1 {
> > +     status = "okay";
> > +     pinctrl-0 = <&spi1_pins>;
> > +     pinctrl-names = "default";
> > +     cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
> > +     dmas = <&dmamux1 37 0x400 0x05>,
> > +            <&dmamux1 38 0x400 0x05>;
> > +     dma-names = "rx", "tx";
> > +
> > +     flash@0 {
> > +             #address-cells = <1>;
> > +             #size-cells = <1>;
> > +             compatible = "winbond,w25q128", "jedec,spi-nor";
> > +             reg = <0>;
> > +             spi-max-frequency = <80000000>;
> > +
> > +             partition@0 {
> > +                     label = "root filesystem";
> > +                     reg = <0 0x1000000>;
> > +             };
> > +     };
> > +};
> > +
> > +&sdmmc2 {
> > +     pinctrl-names = "default", "opendrain", "sleep";
> > +     pinctrl-0 = <&sdmmc2_b4_pins_a>;
> > +     pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
> > +     pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
> > +     broken-cd;
> > +     non-removable;
> > +     st,neg-edge;
> > +     bus-width = <4>;
> > +     vmmc-supply = <&wlan_pwr>;
> > +     status = "okay";
> > +
> > +     #address-cells = <1>;
> > +     #size-cells = <0>;
> > +     brcmf: bcrmf@1 {
> > +             reg = <1>;
> > +             compatible = "brcm,bcm4329-fmac";
> > +     };
> > +};
> > +
> > +&usart3 {
> > +     /delete-property/st,hw-flow-ctrl;
> > +     cts-gpios = <&gpiod 11 GPIO_ACTIVE_LOW>;
> > +     rts-gpios = <&gpiod 12 GPIO_ACTIVE_LOW>;
> > +     dmas = <&dmamux1 45 0x400 0x05>,
> > +            <&dmamux1 46 0x400 0x05>;
> > +     dma-names = "rx", "tx";
> > +     status = "okay";
> > +
> > +     bluetooth {
> > +             host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>;
> > +             device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
> > +             shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>;
> > +             compatible = "brcm,bcm43438-bt";
> > +             max-speed = <115200>;
> > +     };
> > +};
> >

Re: [PATCH 8/8] ARM: stm32: add initial support for stm32h750

[dillon min]

Hi Alexandre

On Thu, Mar 11, 2021 at 6:43 PM Alexandre TORGUE
<alexandre.torgue@foss.st.com> wrote:
>
> Hi Dillon
>
> On 3/3/21 9:05 AM, dillon.minfei@gmail.com wrote:
> > From: dillon min <dillon.minfei@gmail.com>
> >
>
> No empty commit message please
Okay, thanks for remind.
>
> > Signed-off-by: dillon min <dillon.minfei@gmail.com>
> > ---
> >   arch/arm/mach-stm32/board-dt.c | 1 +
> >   1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c
> > index 011d57b488c2..a766310d8dca 100644
> > --- a/arch/arm/mach-stm32/board-dt.c
> > +++ b/arch/arm/mach-stm32/board-dt.c
> > @@ -17,6 +17,7 @@ static const char *const stm32_compat[] __initconst = {
> >       "st,stm32f746",
> >       "st,stm32f769",
> >       "st,stm32h743",
> > +     "st,stm32h750",
> >       "st,stm32mp157",
> >       NULL
> >   };
> >

Re: [Linux-stm32] [PATCH 5/8] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h75x

[Ahmad Fatoum]

Hello Dillon,

On 11.03.21 13:23, dillon min wrote:
> For stm32h7's new board support , I guess following the stm32f7/stm32f4's style
> is a reasonable way to do it, but add a little optimization。
> which means :
> old structure
> stm32h7-pinctrl.dtsi --> stm32h743-pinctrl.dtsi  (referenced by
> stm32h743i-disco, -eval)
>                                 |--> stm32h750-pinctrl.dtsi
> (referenced by stm32h750i-art-pi, etc)
> add art-pi other board's pin definition in stm32h750-pinctrl.dtsi with
> xxx_pins_a, xxx_pins_b
> xxx_pins_a used for art-pi, xxx_pins_b used for other boards.
> 
> after more boards add in support, there will be more xxx_pin_c, .... defined
> 
> as the pin map is according to the hardware schematic diagram io connection.
> so, why not move xxx_pin_x to a board specific place. such as
> stm32h750i-art-pi.dts
> 
> new structure:
> 1, rename stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi (only
> preserve gpioa...k,)
> 2, move xxx_pins_x from stm32h7-pinctrl.dtsi to
> stm32h7xx-disco/eval/art-pi/etc.dts (as they depends on hardware
> schematic)
> 
> stm32h7-pinctrl.dtsi --> stm32h743i-discon.dts
>                                 |--> stm32h743i-eval.dts
>                                 |--> stm32h750i-art-pi.dts
>                                 |--> stm32h7xxx.dts
> would you agree this ?

If the optimization you intend is reducing DTB size, you can flag
all pinctrl groups with /omit-if-no-ref/ to have dtc throw them
away if they are unused.

(But in general, I am in favor of having board-specific configuration
 in the board dts)

Cheers,
Ahmad

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [Linux-stm32] [PATCH 5/8] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h75x

[dillon min]

Hi Ahmad,

Thanks for discussing.

On Thu, Mar 11, 2021 at 8:55 PM Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
>
> Hello Dillon,
>
> On 11.03.21 13:23, dillon min wrote:
> > For stm32h7's new board support , I guess following the stm32f7/stm32f4's style
> > is a reasonable way to do it, but add a little optimization。
> > which means :
> > old structure
> > stm32h7-pinctrl.dtsi --> stm32h743-pinctrl.dtsi  (referenced by
> > stm32h743i-disco, -eval)
> >                                 |--> stm32h750-pinctrl.dtsi
> > (referenced by stm32h750i-art-pi, etc)
> > add art-pi other board's pin definition in stm32h750-pinctrl.dtsi with
> > xxx_pins_a, xxx_pins_b
> > xxx_pins_a used for art-pi, xxx_pins_b used for other boards.
> >
> > after more boards add in support, there will be more xxx_pin_c, .... defined
> >
> > as the pin map is according to the hardware schematic diagram io connection.
> > so, why not move xxx_pin_x to a board specific place. such as
> > stm32h750i-art-pi.dts
> >
> > new structure:
> > 1, rename stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi (only
> > preserve gpioa...k,)
> > 2, move xxx_pins_x from stm32h7-pinctrl.dtsi to
> > stm32h7xx-disco/eval/art-pi/etc.dts (as they depends on hardware
> > schematic)
> >
> > stm32h7-pinctrl.dtsi --> stm32h743i-discon.dts
> >                                 |--> stm32h743i-eval.dts
> >                                 |--> stm32h750i-art-pi.dts
> >                                 |--> stm32h7xxx.dts
> > would you agree this ?
>
> If the optimization you intend is reducing DTB size, you can flag
> all pinctrl groups with /omit-if-no-ref/ to have dtc throw them
> away if they are unused.
Thanks for your advice, actually, DTB size is not my first consideration.
different board pin configuration place to one dtsi files, it's a little hard
to maintain when a lot of boards add in.

>
> (But in general, I am in favor of having board-specific configuration
>  in the board dts)
Yes, same to me.
>
> Cheers,
> Ahmad
>
> --
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH 5/8] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h75x

[Alexandre TORGUE]

Hi Dillon

On 3/11/21 1:23 PM, dillon min wrote:
> Hi Alexandre
> 
> On Thu, Mar 11, 2021 at 6:40 PM Alexandre TORGUE
> <alexandre.torgue@foss.st.com> wrote:
>>
>> Hi Dillon
>>
>> On 3/3/21 9:05 AM, dillon.minfei@gmail.com wrote:
>>> From: dillon min <dillon.minfei@gmail.com>
>>>
>>> To support stm32h750 and stm32h743, we need a base stm32h7-pinctrl.dtsi
>>> as stm32h743 & h750 has almost the same interface. so, just rename
>>> stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi
>>>
>>
>> You do not "just" rename but you keel also the old version. I don't
>> agree with this approach. You have first to rename
>> stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi (keeping copyright as
>> they are please) and modify existing H7 boards which currently use
>> stm32h743-pinctrl.dtsi.
>> Then you create a second patch adding your pingroups.
> For stm32h7's new board support , I guess following the stm32f7/stm32f4's style

Yes sorry, I read it too quickly

> is a reasonable way to do it, but add a little optimization。
> which means :
> old structure
> stm32h7-pinctrl.dtsi --> stm32h743-pinctrl.dtsi  (referenced by
> stm32h743i-disco, -eval)
>                                  |--> stm32h750-pinctrl.dtsi
> (referenced by stm32h750i-art-pi, etc)
> add art-pi other board's pin definition in stm32h750-pinctrl.dtsi with
> xxx_pins_a, xxx_pins_b
> xxx_pins_a used for art-pi, xxx_pins_b used for other boards.
> 
> after more boards add in support, there will be more xxx_pin_c, .... defined
> 
> as the pin map is according to the hardware schematic diagram io connection.
> so, why not move xxx_pin_x to a board specific place. such as
> stm32h750i-art-pi.dts
> 
> new structure:
> 1, rename stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi (only
> preserve gpioa...k,)
> 2, move xxx_pins_x from stm32h7-pinctrl.dtsi to
> stm32h7xx-disco/eval/art-pi/etc.dts (as they depends on hardware
> schematic)
> 
> stm32h7-pinctrl.dtsi --> stm32h743i-discon.dts
>                                  |--> stm32h743i-eval.dts
>                                  |--> stm32h750i-art-pi.dts
>                                  |--> stm32h7xxx.dts
> would you agree this ?

:) it remember me an old discussion we had with Ahmad or Marek. My first 
feeling is "The group definition follow the SoC, and the group choice is 
done on the board". But As said in the past I have to think more about 
this topic and check how it could be reorganize (as it would be nice to 
have the same approach for MPU and MCU boards.) I'll try to post 
something soon. Waiting that this patch looks. As you mainly change the 
name can you keep please header (copyright) as they were initially.

>>
>> Now regarding "st,stm32h750-pinctrl", I see a patch dealing with this
>> new binding but no update on driver side. Do I miss something ? what are
>> differences between h743 and h750 regarding pinctrl ?
> Oh, i forget to add pin driver under drivers/pinctrl/stm32/
> will add it next time.
>>
>> Regards
>> Alex
>>
>>> Signed-off-by: dillon min <dillon.minfei@gmail.com>
>>> ---
>>>    arch/arm/boot/dts/stm32h7-pinctrl.dtsi   | 392 +++++++++++++++++++++++++++++++
>>>    arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 307 +-----------------------
>>>    2 files changed, 398 insertions(+), 301 deletions(-)
>>>    create mode 100644 arch/arm/boot/dts/stm32h7-pinctrl.dtsi
>>>
>>> diff --git a/arch/arm/boot/dts/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi
>>> new file mode 100644
>>> index 000000000000..7d4b5d683ccc
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi
>>> @@ -0,0 +1,392 @@
>>> +/*
>>> + * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
>>> + *
>>> + * This file is dual-licensed: you can use it either under the terms
>>> + * of the GPL or the X11 license, at your option. Note that this dual
>>> + * licensing only applies to this file, and not this project as a
>>> + * whole.
>>> + *
>>> + *  a) This file is free software; you can redistribute it and/or
>>> + *     modify it under the terms of the GNU General Public License as
>>> + *     published by the Free Software Foundation; either version 2 of the
>>> + *     License, or (at your option) any later version.
>>> + *
>>> + *     This file is distributed in the hope that it will be useful,
>>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> + *     GNU General Public License for more details.
>>> + *
>>> + * Or, alternatively,
>>> + *
>>> + *  b) Permission is hereby granted, free of charge, to any person
>>> + *     obtaining a copy of this software and associated documentation
>>> + *     files (the "Software"), to deal in the Software without
>>> + *     restriction, including without limitation the rights to use,
>>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>>> + *     sell copies of the Software, and to permit persons to whom the
>>> + *     Software is furnished to do so, subject to the following
>>> + *     conditions:
>>> + *
>>> + *     The above copyright notice and this permission notice shall be
>>> + *     included in all copies or substantial portions of the Software.
>>> + *
>>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> + *     OTHER DEALINGS IN THE SOFTWARE.
>>> + */
>>> +
>>> +#include <dt-bindings/pinctrl/stm32-pinfunc.h>
>>> +
>>> +/ {
>>> +     soc {
>>> +             pinctrl: pin-controller {
>>> +                     #address-cells = <1>;
>>> +                     #size-cells = <1>;
>>> +                     ranges = <0 0x58020000 0x3000>;
>>> +                     interrupt-parent = <&exti>;
>>> +                     st,syscfg = <&syscfg 0x8>;
>>> +                     pins-are-numbered;
>>> +
>>> +                     gpioa: gpio@58020000 {
>>> +                             gpio-controller;
>>> +                             #gpio-cells = <2>;
>>> +                             reg = <0x0 0x400>;
>>> +                             clocks = <&rcc GPIOA_CK>;
>>> +                             st,bank-name = "GPIOA";
>>> +                             interrupt-controller;
>>> +                             #interrupt-cells = <2>;
>>> +                     };
>>> +
>>> +                     gpiob: gpio@58020400 {
>>> +                             gpio-controller;
>>> +                             #gpio-cells = <2>;
>>> +                             reg = <0x400 0x400>;
>>> +                             clocks = <&rcc GPIOB_CK>;
>>> +                             st,bank-name = "GPIOB";
>>> +                             interrupt-controller;
>>> +                             #interrupt-cells = <2>;
>>> +                     };
>>> +
>>> +                     gpioc: gpio@58020800 {
>>> +                             gpio-controller;
>>> +                             #gpio-cells = <2>;
>>> +                             reg = <0x800 0x400>;
>>> +                             clocks = <&rcc GPIOC_CK>;
>>> +                             st,bank-name = "GPIOC";
>>> +                             interrupt-controller;
>>> +                             #interrupt-cells = <2>;
>>> +                     };
>>> +
>>> +                     gpiod: gpio@58020c00 {
>>> +                             gpio-controller;
>>> +                             #gpio-cells = <2>;
>>> +                             reg = <0xc00 0x400>;
>>> +                             clocks = <&rcc GPIOD_CK>;
>>> +                             st,bank-name = "GPIOD";
>>> +                             interrupt-controller;
>>> +                             #interrupt-cells = <2>;
>>> +                     };
>>> +
>>> +                     gpioe: gpio@58021000 {
>>> +                             gpio-controller;
> 
>>> +                             reg = <0x1000 0x400>;
>>> +                             clocks = <&rcc GPIOE_CK>;
>>> +                             st,bank-name = "GPIOE";
>>> +                             interrupt-controller;
>>> +                             #interrupt-cells = <2>;
>>> +                     };
>>> +
>>> +                     gpiof: gpio@58021400 {
>>> +                             gpio-controller;
>>> +                             #gpio-cells = <2>;
>>> +                             reg = <0x1400 0x400>;
>>> +                             clocks = <&rcc GPIOF_CK>;
>>> +                             st,bank-name = "GPIOF";
>>> +                             interrupt-controller;
>>> +                             #interrupt-cells = <2>;
>>> +                     };
>>> +
>>> +                     gpiog: gpio@58021800 {
>>> +                             gpio-controller;
>>> +                             #gpio-cells = <2>;
>>> +                             reg = <0x1800 0x400>;
>>> +                             clocks = <&rcc GPIOG_CK>;
>>> +                             st,bank-name = "GPIOG";
>>> +                             interrupt-controller;
>>> +                             #interrupt-cells = <2>;
>>> +                     };
>>> +
>>> +                     gpioh: gpio@58021c00 {
>>> +                             gpio-controller;
>>> +                             #gpio-cells = <2>;
>>> +                             reg = <0x1c00 0x400>;
>>> +                             clocks = <&rcc GPIOH_CK>;
>>> +                             st,bank-name = "GPIOH";
>>> +                             interrupt-controller;
>>> +                             #interrupt-cells = <2>;
>>> +                     };
>>> +
>>> +                     gpioi: gpio@58022000 {
>>> +                             gpio-controller;
>>> +                             #gpio-cells = <2>;
>>> +                             reg = <0x2000 0x400>;
>>> +                             clocks = <&rcc GPIOI_CK>;
>>> +                             st,bank-name = "GPIOI";
>>> +                             interrupt-controller;
>>> +                             #interrupt-cells = <2>;
>>> +                     };
>>> +
>>> +                     gpioj: gpio@58022400 {
>>> +                             gpio-controller;
>>> +                             #gpio-cells = <2>;
>>> +                             reg = <0x2400 0x400>;
>>> +                             clocks = <&rcc GPIOJ_CK>;
>>> +                             st,bank-name = "GPIOJ";
>>> +                             interrupt-controller;
>>> +                             #interrupt-cells = <2>;
>>> +                     };
>>> +
>>> +                     gpiok: gpio@58022800 {
>>> +                             gpio-controller;
>>> +                             #gpio-cells = <2>;
>>> +                             reg = <0x2800 0x400>;
>>> +                             clocks = <&rcc GPIOK_CK>;
>>> +                             st,bank-name = "GPIOK";
>>> +                             interrupt-controller;
>>> +                             #interrupt-cells = <2>;
>>> +                     };
>>> +
>>> +                     i2c1_pins_a: i2c1-0 {
>>> +                             pins {
>>> +                                     pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
>>> +                                              <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
>>> +                                     bias-disable;
>>> +                                     drive-open-drain;
>>> +                                     slew-rate = <0>;
>>> +                             };
>>> +                     };
>>> +
>>> +                     ethernet_rmii: rmii-0 {
>>> +                             pins {
>>> +                                     pinmux = <STM32_PINMUX('G', 11, AF11)>,
>>> +                                              <STM32_PINMUX('G', 13, AF11)>,
>>> +                                              <STM32_PINMUX('G', 12, AF11)>,
>>> +                                              <STM32_PINMUX('C', 4, AF11)>,
>>> +                                              <STM32_PINMUX('C', 5, AF11)>,
>>> +                                              <STM32_PINMUX('A', 7, AF11)>,
>>> +                                              <STM32_PINMUX('C', 1, AF11)>,
>>> +                                              <STM32_PINMUX('A', 2, AF11)>,
>>> +                                              <STM32_PINMUX('A', 1, AF11)>;
>>> +                                     slew-rate = <2>;
>>> +                             };
>>> +                     };
>>> +
>>> +                     sdmmc1_b4_pins_a: sdmmc1-b4-0 {
>>> +                             pins {
>>> +                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
>>> +                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
>>> +                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
>>> +                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
>>> +                                              <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
>>> +                                              <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
>>> +                                     slew-rate = <3>;
>>> +                                     drive-push-pull;
>>> +                                     bias-disable;
>>> +                             };
>>> +                     };
>>> +
>>> +                     sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
>>> +                             pins1 {
>>> +                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
>>> +                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
>>> +                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
>>> +                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
>>> +                                              <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
>>> +                                     slew-rate = <3>;
>>> +                                     drive-push-pull;
>>> +                                     bias-disable;
>>> +                             };
>>> +                             pins2{
>>> +                                     pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
>>> +                                     slew-rate = <3>;
>>> +                                     drive-open-drain;
>>> +                                     bias-disable;
>>> +                             };
>>> +                     };
>>> +
>>> +                     sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
>>> +                             pins {
>>> +                                     pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
>>> +                                              <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
>>> +                                              <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
>>> +                                              <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
>>> +                                              <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
>>> +                                              <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
>>> +                             };
>>> +                     };
>>> +
>>> +                     sdmmc2_b4_pins_a: sdmmc2-b4-0 {
>>> +                             pins {
>>> +                                     pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */
>>> +                                              <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
>>> +                                              <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
>>> +                                              <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
>>> +                                              <STM32_PINMUX('D', 6, AF11)>, /* SDMMC1_CK */
>>> +                                              <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
>>> +                                     slew-rate = <3>;
>>> +                                     drive-push-pull;
>>> +                                     bias-disable;
>>> +                             };
>>> +                     };
>>> +
>>> +                     sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
>>> +                             pins1 {
>>> +                                     pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
>>> +                                              <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
>>> +                                              <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
>>> +                                              <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
>>> +                                              <STM32_PINMUX('D', 6, AF11)>; /* SDMMC1_CK */
>>> +                                     slew-rate = <3>;
>>> +                                     drive-push-pull;
>>> +                                     bias-disable;
>>> +                             };
>>> +                             pins2{
>>> +                                     pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
>>> +                                     slew-rate = <3>;
>>> +                                     drive-open-drain;
>>> +                                     bias-disable;
>>> +                             };
>>> +                     };
>>> +
>>> +                     sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
>>> +                             pins {
>>> +                                     pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC1_D0 */
>>> +                                              <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC1_D1 */
>>> +                                              <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC1_D2 */
>>> +                                              <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC1_D3 */
>>> +                                              <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC1_CK */
>>> +                                              <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC1_CMD */
>>> +                             };
>>> +                     };
>>> +
>>> +                     sdmmc1_dir_pins_a: sdmmc1-dir-0 {
>>> +                             pins1 {
>>> +                                     pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
>>> +                                              <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
>>> +                                              <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
>>> +                                     slew-rate = <3>;
>>> +                                     drive-push-pull;
>>> +                                     bias-pull-up;
>>> +                             };
>>> +                             pins2{
>>> +                                     pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
>>> +                                     bias-pull-up;
>>> +                             };
>>> +                     };
>>> +
>>> +                     sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
>>> +                             pins {
>>> +                                     pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
>>> +                                              <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
>>> +                                              <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
>>> +                                              <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
>>> +                             };
>>> +                     };
>>> +
>>> +                     usart1_pins: usart1-0 {
>>> +                             pins1 {
>>> +                                     pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
>>> +                                     bias-disable;
>>> +                                     drive-push-pull;
>>> +                                     slew-rate = <0>;
>>> +                             };
>>> +                             pins2 {
>>> +                                     pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
>>> +                                     bias-disable;
>>> +                             };
>>> +                     };
>>> +
>>> +                     usart2_pins: usart2-0 {
>>> +                             pins1 {
>>> +                                     pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
>>> +                                     bias-disable;
>>> +                                     drive-push-pull;
>>> +                                     slew-rate = <0>;
>>> +                             };
>>> +                             pins2 {
>>> +                                     pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
>>> +                                     bias-disable;
>>> +                             };
>>> +                     };
>>> +
>>> +                     usart3_pins: usart3-0 {
>>> +                             pins1 {
>>> +                                     pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
>>> +                                     bias-disable;
>>> +                                     drive-push-pull;
>>> +                                     slew-rate = <0>;
>>> +                             };
>>> +                             pins2 {
>>> +                                     pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
>>> +                                     bias-disable;
>>> +                             };
>>> +                     };
>>> +
>>> +                     uart4_pins: uart4-0 {
>>> +                             pins1 {
>>> +                                     pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */
>>> +                                     bias-disable;
>>> +                                     drive-push-pull;
>>> +                                     slew-rate = <0>;
>>> +                             };
>>> +                             pins2 {
>>> +                                     pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */
>>> +                                     bias-disable;
>>> +                             };
>>> +                     };
>>> +
>>> +                     usbotg_hs_pins_a: usbotg-hs-0 {
>>> +                             pins {
>>> +                                     pinmux = <STM32_PINMUX('H', 4, AF10)>,  /* ULPI_NXT */
>>> +                                                      <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
>>> +                                                      <STM32_PINMUX('C', 0, AF10)>,  /* ULPI_STP> */
>>> +                                                      <STM32_PINMUX('A', 5, AF10)>,  /* ULPI_CK> */
>>> +                                                      <STM32_PINMUX('A', 3, AF10)>,  /* ULPI_D0> */
>>> +                                                      <STM32_PINMUX('B', 0, AF10)>,  /* ULPI_D1> */
>>> +                                                      <STM32_PINMUX('B', 1, AF10)>,  /* ULPI_D2> */
>>> +                                                      <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
>>> +                                                      <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
>>> +                                                      <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
>>> +                                                      <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
>>> +                                                      <STM32_PINMUX('B', 5, AF10)>;  /* ULPI_D7> */
>>> +                                     bias-disable;
>>> +                                     drive-push-pull;
>>> +                                     slew-rate = <2>;
>>> +                             };
>>> +                     };
>>> +
>>> +                     spi1_pins: spi1-0 {
>>> +                             pins1 {
>>> +                                     pinmux = <STM32_PINMUX('A', 5, AF5)>,
>>> +                                             /* SPI1_CLK */
>>> +                                              <STM32_PINMUX('B', 5, AF5)>;
>>> +                                             /* SPI1_MOSI */
>>> +                                     bias-disable;
>>> +                                     drive-push-pull;
>>> +                                     slew-rate = <2>;
>>> +                             };
>>> +                             pins2 {
>>> +                                     pinmux = <STM32_PINMUX('G', 9, AF5)>;
>>> +                                             /* SPI1_MISO */
>>> +                                     bias-disable;
>>> +                             };
>>> +                     };
>>> +             };
>>> +     };
>>> +};
>>> diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
>>> index fa5dcb6a5fdd..6b1e115307b9 100644
>>> --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
>>> +++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
>>> @@ -1,306 +1,11 @@
>>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>>>    /*
>>> - * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
>>> - *
>>> - * This file is dual-licensed: you can use it either under the terms
>>> - * of the GPL or the X11 license, at your option. Note that this dual
>>> - * licensing only applies to this file, and not this project as a
>>> - * whole.
>>> - *
>>> - *  a) This file is free software; you can redistribute it and/or
>>> - *     modify it under the terms of the GNU General Public License as
>>> - *     published by the Free Software Foundation; either version 2 of the
>>> - *     License, or (at your option) any later version.
>>> - *
>>> - *     This file is distributed in the hope that it will be useful,
>>> - *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> - *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> - *     GNU General Public License for more details.
>>> - *
>>> - * Or, alternatively,
>>> - *
>>> - *  b) Permission is hereby granted, free of charge, to any person
>>> - *     obtaining a copy of this software and associated documentation
>>> - *     files (the "Software"), to deal in the Software without
>>> - *     restriction, including without limitation the rights to use,
>>> - *     copy, modify, merge, publish, distribute, sublicense, and/or
>>> - *     sell copies of the Software, and to permit persons to whom the
>>> - *     Software is furnished to do so, subject to the following
>>> - *     conditions:
>>> - *
>>> - *     The above copyright notice and this permission notice shall be
>>> - *     included in all copies or substantial portions of the Software.
>>> - *
>>> - *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> - *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>> - *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>> - *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>> - *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>> - *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> - *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> - *     OTHER DEALINGS IN THE SOFTWARE.
>>> + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
>>> + * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
>>>     */
>>>
>>> -#include <dt-bindings/pinctrl/stm32-pinfunc.h>
>>> +#include "stm32h7-pinctrl.dtsi"
>>>
>>> -/ {
>>> -     soc {
>>> -             pin-controller {
>>> -                     #address-cells = <1>;
>>> -                     #size-cells = <1>;
>>> -                     compatible = "st,stm32h743-pinctrl";
>>> -                     ranges = <0 0x58020000 0x3000>;
>>> -                     interrupt-parent = <&exti>;
>>> -                     st,syscfg = <&syscfg 0x8>;
>>> -                     pins-are-numbered;
>>> -
>>> -                     gpioa: gpio@58020000 {
>>> -                             gpio-controller;
>>> -                             #gpio-cells = <2>;
>>> -                             reg = <0x0 0x400>;
>>> -                             clocks = <&rcc GPIOA_CK>;
>>> -                             st,bank-name = "GPIOA";
>>> -                             interrupt-controller;
>>> -                             #interrupt-cells = <2>;
>>> -                     };
>>> -
>>> -                     gpiob: gpio@58020400 {
>>> -                             gpio-controller;
>>> -                             #gpio-cells = <2>;
>>> -                             reg = <0x400 0x400>;
>>> -                             clocks = <&rcc GPIOB_CK>;
>>> -                             st,bank-name = "GPIOB";
>>> -                             interrupt-controller;
>>> -                             #interrupt-cells = <2>;
>>> -                     };
>>> -
>>> -                     gpioc: gpio@58020800 {
>>> -                             gpio-controller;
>>> -                             #gpio-cells = <2>;
>>> -                             reg = <0x800 0x400>;
>>> -                             clocks = <&rcc GPIOC_CK>;
>>> -                             st,bank-name = "GPIOC";
>>> -                             interrupt-controller;
>>> -                             #interrupt-cells = <2>;
>>> -                     };
>>> -
>>> -                     gpiod: gpio@58020c00 {
>>> -                             gpio-controller;
>>> -                             #gpio-cells = <2>;
>>> -                             reg = <0xc00 0x400>;
>>> -                             clocks = <&rcc GPIOD_CK>;
>>> -                             st,bank-name = "GPIOD";
>>> -                             interrupt-controller;
>>> -                             #interrupt-cells = <2>;
>>> -                     };
>>> -
>>> -                     gpioe: gpio@58021000 {
>>> -                             gpio-controller;
>>> -                             #gpio-cells = <2>;
>>> -                             reg = <0x1000 0x400>;
>>> -                             clocks = <&rcc GPIOE_CK>;
>>> -                             st,bank-name = "GPIOE";
>>> -                             interrupt-controller;
>>> -                             #interrupt-cells = <2>;
>>> -                     };
>>> -
>>> -                     gpiof: gpio@58021400 {
>>> -                             gpio-controller;
>>> -                             #gpio-cells = <2>;
>>> -                             reg = <0x1400 0x400>;
>>> -                             clocks = <&rcc GPIOF_CK>;
>>> -                             st,bank-name = "GPIOF";
>>> -                             interrupt-controller;
>>> -                             #interrupt-cells = <2>;
>>> -                     };
>>> -
>>> -                     gpiog: gpio@58021800 {
>>> -                             gpio-controller;
>>> -                             #gpio-cells = <2>;
>>> -                             reg = <0x1800 0x400>;
>>> -                             clocks = <&rcc GPIOG_CK>;
>>> -                             st,bank-name = "GPIOG";
>>> -                             interrupt-controller;
>>> -                             #interrupt-cells = <2>;
>>> -                     };
>>> -
>>> -                     gpioh: gpio@58021c00 {
>>> -                             gpio-controller;
>>> -                             #gpio-cells = <2>;
>>> -                             reg = <0x1c00 0x400>;
>>> -                             clocks = <&rcc GPIOH_CK>;
>>> -                             st,bank-name = "GPIOH";
>>> -                             interrupt-controller;
>>> -                             #interrupt-cells = <2>;
>>> -                     };
>>> -
>>> -                     gpioi: gpio@58022000 {
>>> -                             gpio-controller;
>>> -                             #gpio-cells = <2>;
>>> -                             reg = <0x2000 0x400>;
>>> -                             clocks = <&rcc GPIOI_CK>;
>>> -                             st,bank-name = "GPIOI";
>>> -                             interrupt-controller;
>>> -                             #interrupt-cells = <2>;
>>> -                     };
>>> -
>>> -                     gpioj: gpio@58022400 {
>>> -                             gpio-controller;
>>> -                             #gpio-cells = <2>;
>>> -                             reg = <0x2400 0x400>;
>>> -                             clocks = <&rcc GPIOJ_CK>;
>>> -                             st,bank-name = "GPIOJ";
>>> -                             interrupt-controller;
>>> -                             #interrupt-cells = <2>;
>>> -                     };
>>> -
>>> -                     gpiok: gpio@58022800 {
>>> -                             gpio-controller;
>>> -                             #gpio-cells = <2>;
>>> -                             reg = <0x2800 0x400>;
>>> -                             clocks = <&rcc GPIOK_CK>;
>>> -                             st,bank-name = "GPIOK";
>>> -                             interrupt-controller;
>>> -                             #interrupt-cells = <2>;
>>> -                     };
>>> -
>>> -                     i2c1_pins_a: i2c1-0 {
>>> -                             pins {
>>> -                                     pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
>>> -                                              <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
>>> -                                     bias-disable;
>>> -                                     drive-open-drain;
>>> -                                     slew-rate = <0>;
>>> -                             };
>>> -                     };
>>> -
>>> -                     ethernet_rmii: rmii-0 {
>>> -                             pins {
>>> -                                     pinmux = <STM32_PINMUX('G', 11, AF11)>,
>>> -                                              <STM32_PINMUX('G', 13, AF11)>,
>>> -                                              <STM32_PINMUX('G', 12, AF11)>,
>>> -                                              <STM32_PINMUX('C', 4, AF11)>,
>>> -                                              <STM32_PINMUX('C', 5, AF11)>,
>>> -                                              <STM32_PINMUX('A', 7, AF11)>,
>>> -                                              <STM32_PINMUX('C', 1, AF11)>,
>>> -                                              <STM32_PINMUX('A', 2, AF11)>,
>>> -                                              <STM32_PINMUX('A', 1, AF11)>;
>>> -                                     slew-rate = <2>;
>>> -                             };
>>> -                     };
>>> -
>>> -                     sdmmc1_b4_pins_a: sdmmc1-b4-0 {
>>> -                             pins {
>>> -                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
>>> -                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
>>> -                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
>>> -                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
>>> -                                              <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
>>> -                                              <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
>>> -                                     slew-rate = <3>;
>>> -                                     drive-push-pull;
>>> -                                     bias-disable;
>>> -                             };
>>> -                     };
>>> -
>>> -                     sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
>>> -                             pins1 {
>>> -                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
>>> -                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
>>> -                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
>>> -                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
>>> -                                              <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
>>> -                                     slew-rate = <3>;
>>> -                                     drive-push-pull;
>>> -                                     bias-disable;
>>> -                             };
>>> -                             pins2{
>>> -                                     pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
>>> -                                     slew-rate = <3>;
>>> -                                     drive-open-drain;
>>> -                                     bias-disable;
>>> -                             };
>>> -                     };
>>> -
>>> -                     sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
>>> -                             pins {
>>> -                                     pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
>>> -                                              <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
>>> -                                              <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
>>> -                                              <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
>>> -                                              <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
>>> -                                              <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
>>> -                             };
>>> -                     };
>>> -
>>> -                     sdmmc1_dir_pins_a: sdmmc1-dir-0 {
>>> -                             pins1 {
>>> -                                     pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
>>> -                                              <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
>>> -                                              <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
>>> -                                     slew-rate = <3>;
>>> -                                     drive-push-pull;
>>> -                                     bias-pull-up;
>>> -                             };
>>> -                             pins2{
>>> -                                     pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
>>> -                                     bias-pull-up;
>>> -                             };
>>> -                     };
>>> -
>>> -                     sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
>>> -                             pins {
>>> -                                     pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
>>> -                                              <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
>>> -                                              <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
>>> -                                              <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
>>> -                             };
>>> -                     };
>>> -
>>> -                     usart1_pins: usart1-0 {
>>> -                             pins1 {
>>> -                                     pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
>>> -                                     bias-disable;
>>> -                                     drive-push-pull;
>>> -                                     slew-rate = <0>;
>>> -                             };
>>> -                             pins2 {
>>> -                                     pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
>>> -                                     bias-disable;
>>> -                             };
>>> -                     };
>>> -
>>> -                     usart2_pins: usart2-0 {
>>> -                             pins1 {
>>> -                                     pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
>>> -                                     bias-disable;
>>> -                                     drive-push-pull;
>>> -                                     slew-rate = <0>;
>>> -                             };
>>> -                             pins2 {
>>> -                                     pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
>>> -                                     bias-disable;
>>> -                             };
>>> -                     };
>>> -
>>> -                     usbotg_hs_pins_a: usbotg-hs-0 {
>>> -                             pins {
>>> -                                     pinmux = <STM32_PINMUX('H', 4, AF10)>,  /* ULPI_NXT */
>>> -                                                      <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
>>> -                                                      <STM32_PINMUX('C', 0, AF10)>,  /* ULPI_STP> */
>>> -                                                      <STM32_PINMUX('A', 5, AF10)>,  /* ULPI_CK> */
>>> -                                                      <STM32_PINMUX('A', 3, AF10)>,  /* ULPI_D0> */
>>> -                                                      <STM32_PINMUX('B', 0, AF10)>,  /* ULPI_D1> */
>>> -                                                      <STM32_PINMUX('B', 1, AF10)>,  /* ULPI_D2> */
>>> -                                                      <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
>>> -                                                      <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
>>> -                                                      <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
>>> -                                                      <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
>>> -                                                      <STM32_PINMUX('B', 5, AF10)>;  /* ULPI_D7> */
>>> -                                     bias-disable;
>>> -                                     drive-push-pull;
>>> -                                     slew-rate = <2>;
>>> -                             };
>>> -                     };
>>> -             };
>>> -     };
>>> +&pinctrl{
>>> +     compatible = "st,stm32h743-pinctrl";
>>>    };
>>>

Re: [PATCH 7/8] ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6

[Alexandre TORGUE]

On 3/11/21 1:32 PM, dillon min wrote:
> Hi Alexandre
> 
> On Thu, Mar 11, 2021 at 6:42 PM Alexandre TORGUE
> <alexandre.torgue@foss.st.com> wrote:
>>
>>
>>
>> On 3/3/21 9:05 AM, dillon.minfei@gmail.com wrote:
>>> From: dillon min <dillon.minfei@gmail.com>
>>>
>>> This patchset has following changes:
>>>
>>> - add stm32h750i-art-pi.dtb
>>> - add dts binding usart3 for bt, uart4 for console
>>> - add dts binding sdmmc2 for wifi
>>> - add stm32h750-art-pi.dts to support art-pi board
>>>
>>> board component:
>>> - 8MiB qspi flash
>>> - 16MiB spi flash
>>> - 32MiB sdram
>>> - ap6212 wifi&bt&fm
>>>
>>> the detail board information can be found at:
>>> https://art-pi.gitee.io/website/
>>>
>>> Signed-off-by: dillon min <dillon.minfei@gmail.com>
>>> ---
>>>    arch/arm/boot/dts/Makefile              |   1 +
>>>    arch/arm/boot/dts/stm32h743.dtsi        |  30 +++++
>>>    arch/arm/boot/dts/stm32h750.dtsi        |   5 +
>>>    arch/arm/boot/dts/stm32h750i-art-pi.dts | 224 ++++++++++++++++++++++++++++++++
>>>    4 files changed, 260 insertions(+)
>>>    create mode 100644 arch/arm/boot/dts/stm32h750.dtsi
>>>    create mode 100644 arch/arm/boot/dts/stm32h750i-art-pi.dts
>>>
>>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>>> index 8e5d4ab4e75e..a19c5ab9df84 100644
>>> --- a/arch/arm/boot/dts/Makefile
>>> +++ b/arch/arm/boot/dts/Makefile
>>> @@ -1071,6 +1071,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
>>>        stm32746g-eval.dtb \
>>>        stm32h743i-eval.dtb \
>>>        stm32h743i-disco.dtb \
>>> +     stm32h750i-art-pi.dtb \
>>>        stm32mp153c-dhcom-drc02.dtb \
>>>        stm32mp157a-avenger96.dtb \
>>>        stm32mp157a-dhcor-avenger96.dtb \
>>> diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
>>> index 4ebffb0a45a3..981d44051007 100644
>>> --- a/arch/arm/boot/dts/stm32h743.dtsi
>>> +++ b/arch/arm/boot/dts/stm32h743.dtsi
>>> @@ -135,6 +135,22 @@
>>>                        clocks = <&rcc USART2_CK>;
>>>                };
>>>
>>> +             usart3: serial@40004800 {
>>> +                     compatible = "st,stm32h7-uart";
>>> +                     reg = <0x40004800 0x400>;
>>> +                     interrupts = <39>;
>>> +                     status = "disabled";
>>> +                     clocks = <&rcc USART3_CK>;
>>> +             };
>>> +
>>> +             uart4: serial@40004c00 {
>>> +                     compatible = "st,stm32h7-uart";
>>> +                     reg = <0x40004c00 0x400>;
>>> +                     interrupts = <52>;
>>> +                     status = "disabled";
>>> +                     clocks = <&rcc UART4_CK>;
>>> +             };
>>> +
>>
>> Those peripherals are available on h743 ?
> Yes, available for stm32h743, but might not used by stm32h743i-disco board.
> the difference between stm32h743xi and stm32h750xb:
>   flash size:  2048/128,
> ad convter : none/3
> crypto-hash: none/aes,hmac,....

Ok, so perfect.

> 
>>
>>>                i2c1: i2c@40005400 {
>>>                        compatible = "st,stm32f7-i2c";
>>>                        #address-cells = <1>;
>>> @@ -368,6 +384,20 @@
>>>                        max-frequency = <120000000>;
>>>                };
>>>
>>> +             sdmmc2: mmc@48022400 {
>>> +                     compatible = "arm,pl18x", "arm,primecell";
>>> +                     arm,primecell-periphid = <0x10153180>;
>>> +                     reg = <0x48022400 0x400>;
>>> +                     interrupts = <124>;
>>> +                     interrupt-names = "cmd_irq";
>>> +                     clocks = <&rcc SDMMC2_CK>;
>>> +                     clock-names = "apb_pclk";
>>> +                     resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
>>> +                     cap-sd-highspeed;
>>> +                     cap-mmc-highspeed;
>>> +                     max-frequency = <120000000>;
>>> +             };
>>> +
>>>                exti: interrupt-controller@58000000 {
>>>                        compatible = "st,stm32h7-exti";
>>>                        interrupt-controller;
>>> diff --git a/arch/arm/boot/dts/stm32h750.dtsi b/arch/arm/boot/dts/stm32h750.dtsi
>>> new file mode 100644
>>> index 000000000000..dd9166223c2f
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/stm32h750.dtsi
>>> @@ -0,0 +1,5 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
>>> +/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */
>>> +
>>> +#include "stm32h743.dtsi"
>>> +
>>> diff --git a/arch/arm/boot/dts/stm32h750i-art-pi.dts b/arch/arm/boot/dts/stm32h750i-art-pi.dts
>>> new file mode 100644
>>> index 000000000000..84cf70d7800c
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/stm32h750i-art-pi.dts
>>> @@ -0,0 +1,224 @@
>>> +/*
>>> + * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
>>> + *
>>> + * This file is dual-licensed: you can use it either under the terms
>>> + * of the GPL or the X11 license, at your option. Note that this dual
>>> + * licensing only applies to this file, and not this project as a
>>> + * whole.
>>> + *
>>> + *  a) This file is free software; you can redistribute it and/or
>>> + *     modify it under the terms of the GNU General Public License as
>>> + *     published by the Free Software Foundation; either version 2 of the
>>> + *     License, or (at your option) any later version.
>>> + *
>>> + *     This file is distributed in the hope that it will be useful,
>>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> + *     GNU General Public License for more details.
>>> + *
>>> + * Or, alternatively,
>>> + *
>>> + *  b) Permission is hereby granted, free of charge, to any person
>>> + *     obtaining a copy of this software and associated documentation
>>> + *     files (the "Software"), to deal in the Software without
>>> + *     restriction, including without limitation the rights to use,
>>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>>> + *     sell copies of the Software, and to permit persons to whom the
>>> + *     Software is furnished to do so, subject to the following
>>> + *     conditions:
>>> + *
>>> + *     The above copyright notice and this permission notice shall be
>>> + *     included in all copies or substantial portions of the Software.
>>> + *
>>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> + *     OTHER DEALINGS IN THE SOFTWARE.
>>> + */
>>> +
>>> +/dts-v1/;
>>> +#include "stm32h750.dtsi"
>>> +#include "stm32h750-pinctrl.dtsi"
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +#include <dt-bindings/gpio/gpio.h>
>>> +
>>> +/ {
>>> +     model = "RT-Thread STM32H750i-ART-PI board";
>>> +     compatible = "st,stm32h750i-art-pi", "st,stm32h750";
>>> +
>>> +     chosen {
>>> +             bootargs = "root=/dev/ram";
>>> +             stdout-path = "serial0:2000000n8";
>>> +     };
>>> +
>>> +     memory@c0000000 {
>>> +             device_type = "memory";
>>> +             reg = <0xc0000000 0x2000000>;
>>> +     };
>>> +
>>> +     reserved-memory {
>>> +             #address-cells = <1>;
>>> +             #size-cells = <1>;
>>> +             ranges;
>>> +
>>> +             linux,cma {
>>> +                     compatible = "shared-dma-pool";
>>> +                     no-map;
>>> +                     size = <0x100000>;
>>> +                     linux,dma-default;
>>> +             };
>>> +     };
>>> +
>>> +     aliases {
>>> +             serial0 = &uart4;
>>> +             serial1 = &usart3;
>>> +     };
>>> +
>>> +     leds {
>>> +             compatible = "gpio-leds";
>>> +             led-red {
>>> +                     gpios = <&gpioi 8 0>;
>>> +             };
>>> +             led-green {
>>> +                     gpios = <&gpioc 15 0>;
>>> +                     linux,default-trigger = "heartbeat";
>>> +             };
>>> +     };
>>> +
>>> +     v3v3: regulator-v3v3 {
>>> +             compatible = "regulator-fixed";
>>> +             regulator-name = "v3v3";
>>> +             regulator-min-microvolt = <3300000>;
>>> +             regulator-max-microvolt = <3300000>;
>>> +             regulator-always-on;
>>> +     };
>>> +
>>> +     wlan_pwr: regulator-wlan {
>>> +             compatible = "regulator-fixed";
>>> +
>>> +             regulator-name = "wl-reg";
>>> +             regulator-min-microvolt = <3300000>;
>>> +             regulator-max-microvolt = <3300000>;
>>> +
>>> +             gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
>>> +             enable-active-high;
>>> +     };
>>> +};
>>> +
>>> +&clk_hse {
>>> +     clock-frequency = <25000000>;
>>> +};
>>> +
>>> +&mac {
>>> +     status = "disabled";
>>> +     pinctrl-0       = <&ethernet_rmii>;
>>> +     pinctrl-names   = "default";
>>> +     phy-mode        = "rmii";
>>> +     phy-handle      = <&phy0>;
>>> +
>>> +     mdio0 {
>>> +             #address-cells = <1>;
>>> +             #size-cells = <0>;
>>> +             compatible = "snps,dwmac-mdio";
>>> +             phy0: ethernet-phy@0 {
>>> +                     reg = <0>;
>>> +             };
>>> +     };
>>> +};
>>> +
>>> +&sdmmc1 {
>>> +     pinctrl-names = "default", "opendrain", "sleep";
>>> +     pinctrl-0 = <&sdmmc1_b4_pins_a>;
>>> +     pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
>>> +     pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
>>> +     broken-cd;
>>> +     st,neg-edge;
>>> +     bus-width = <4>;
>>> +     vmmc-supply = <&v3v3>;
>>> +     status = "okay";
>>> +};
>>> +
>>> +&usart2 {
>>> +     pinctrl-0 = <&usart2_pins>;
>>> +     pinctrl-names = "default";
>>> +     status = "disabled";
>>> +};
>>> +
>>> +&uart4 {
>>> +     pinctrl-0 = <&uart4_pins>;
>>> +     pinctrl-names = "default";
>>> +     status = "okay";
>>> +};
>>> +
>>> +&dma1 {
>>> +     status = "okay";
>>> +};
>>> +
>>
>> Would be better to order by name, but it is your board :)
> Okay, i will follow stm32f7/f4's order next submit.
>>
>>> +&dma2 {
>>> +     status = "okay";
>>> +};
>>> +
>>> +&spi1 {
>>> +     status = "okay";
>>> +     pinctrl-0 = <&spi1_pins>;
>>> +     pinctrl-names = "default";
>>> +     cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
>>> +     dmas = <&dmamux1 37 0x400 0x05>,
>>> +            <&dmamux1 38 0x400 0x05>;
>>> +     dma-names = "rx", "tx";
>>> +
>>> +     flash@0 {
>>> +             #address-cells = <1>;
>>> +             #size-cells = <1>;
>>> +             compatible = "winbond,w25q128", "jedec,spi-nor";
>>> +             reg = <0>;
>>> +             spi-max-frequency = <80000000>;
>>> +
>>> +             partition@0 {
>>> +                     label = "root filesystem";
>>> +                     reg = <0 0x1000000>;
>>> +             };
>>> +     };
>>> +};
>>> +
>>> +&sdmmc2 {
>>> +     pinctrl-names = "default", "opendrain", "sleep";
>>> +     pinctrl-0 = <&sdmmc2_b4_pins_a>;
>>> +     pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
>>> +     pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
>>> +     broken-cd;
>>> +     non-removable;
>>> +     st,neg-edge;
>>> +     bus-width = <4>;
>>> +     vmmc-supply = <&wlan_pwr>;
>>> +     status = "okay";
>>> +
>>> +     #address-cells = <1>;
>>> +     #size-cells = <0>;
>>> +     brcmf: bcrmf@1 {
>>> +             reg = <1>;
>>> +             compatible = "brcm,bcm4329-fmac";
>>> +     };
>>> +};
>>> +
>>> +&usart3 {
>>> +     /delete-property/st,hw-flow-ctrl;
>>> +     cts-gpios = <&gpiod 11 GPIO_ACTIVE_LOW>;
>>> +     rts-gpios = <&gpiod 12 GPIO_ACTIVE_LOW>;
>>> +     dmas = <&dmamux1 45 0x400 0x05>,
>>> +            <&dmamux1 46 0x400 0x05>;
>>> +     dma-names = "rx", "tx";
>>> +     status = "okay";
>>> +
>>> +     bluetooth {
>>> +             host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>;
>>> +             device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
>>> +             shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>;
>>> +             compatible = "brcm,bcm43438-bt";
>>> +             max-speed = <115200>;
>>> +     };
>>> +};
>>>

Re: [PATCH 5/8] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h75x

[dillon min]

Hi Alexandre

On Thu, Mar 11, 2021 at 9:30 PM Alexandre TORGUE
<alexandre.torgue@foss.st.com> wrote:
>
> Hi Dillon
>
> On 3/11/21 1:23 PM, dillon min wrote:
> > Hi Alexandre
> >
> > On Thu, Mar 11, 2021 at 6:40 PM Alexandre TORGUE
> > <alexandre.torgue@foss.st.com> wrote:
> >>
> >> Hi Dillon
> >>
> >> On 3/3/21 9:05 AM, dillon.minfei@gmail.com wrote:
> >>> From: dillon min <dillon.minfei@gmail.com>
> >>>
> >>> To support stm32h750 and stm32h743, we need a base stm32h7-pinctrl.dtsi
> >>> as stm32h743 & h750 has almost the same interface. so, just rename
> >>> stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi
> >>>
> >>
> >> You do not "just" rename but you keel also the old version. I don't
> >> agree with this approach. You have first to rename
> >> stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi (keeping copyright as
> >> they are please) and modify existing H7 boards which currently use
> >> stm32h743-pinctrl.dtsi.
> >> Then you create a second patch adding your pingroups.
> > For stm32h7's new board support , I guess following the stm32f7/stm32f4's style
>
> Yes sorry, I read it too quickly
>
> > is a reasonable way to do it, but add a little optimization。
> > which means :
> > old structure
> > stm32h7-pinctrl.dtsi --> stm32h743-pinctrl.dtsi  (referenced by
> > stm32h743i-disco, -eval)
> >                                  |--> stm32h750-pinctrl.dtsi
> > (referenced by stm32h750i-art-pi, etc)
> > add art-pi other board's pin definition in stm32h750-pinctrl.dtsi with
> > xxx_pins_a, xxx_pins_b
> > xxx_pins_a used for art-pi, xxx_pins_b used for other boards.
> >
> > after more boards add in support, there will be more xxx_pin_c, .... defined
> >
> > as the pin map is according to the hardware schematic diagram io connection.
> > so, why not move xxx_pin_x to a board specific place. such as
> > stm32h750i-art-pi.dts
> >
> > new structure:
> > 1, rename stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi (only
> > preserve gpioa...k,)
> > 2, move xxx_pins_x from stm32h7-pinctrl.dtsi to
> > stm32h7xx-disco/eval/art-pi/etc.dts (as they depends on hardware
> > schematic)
> >
> > stm32h7-pinctrl.dtsi --> stm32h743i-discon.dts
> >                                  |--> stm32h743i-eval.dts
> >                                  |--> stm32h750i-art-pi.dts
> >                                  |--> stm32h7xxx.dts
> > would you agree this ?
>
> :) it remember me an old discussion we had with Ahmad or Marek. My first
> feeling is "The group definition follow the SoC, and the group choice is
> done on the board". But As said in the past I have to think more about
> this topic and check how it could be reorganize (as it would be nice to
> have the same approach for MPU and MCU boards.) I'll try to post
> something soon. Waiting that this patch looks. As you mainly change the
> name can you keep please header (copyright) as they were initially.
Okay, got it. before your patch for pinctrl update. I am just totally following
your current style.
For file author name, copyright. i'm really sorry for that. this is
the first time for me
to add a board support, i'm not intended to replace with my name, just too
many files to change, wasn't beware of the difference with author name for new
created file and existing file . will be changed back in the next submit.
>
> >>
> >> Now regarding "st,stm32h750-pinctrl", I see a patch dealing with this
> >> new binding but no update on driver side. Do I miss something ? what are
> >> differences between h743 and h750 regarding pinctrl ?
> > Oh, i forget to add pin driver under drivers/pinctrl/stm32/
> > will add it next time.
> >>
> >> Regards
> >> Alex
> >>
> >>> Signed-off-by: dillon min <dillon.minfei@gmail.com>
> >>> ---
> >>>    arch/arm/boot/dts/stm32h7-pinctrl.dtsi   | 392 +++++++++++++++++++++++++++++++
> >>>    arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 307 +-----------------------
> >>>    2 files changed, 398 insertions(+), 301 deletions(-)
> >>>    create mode 100644 arch/arm/boot/dts/stm32h7-pinctrl.dtsi
> >>>
> >>> diff --git a/arch/arm/boot/dts/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi
> >>> new file mode 100644
> >>> index 000000000000..7d4b5d683ccc
> >>> --- /dev/null
> >>> +++ b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi
> >>> @@ -0,0 +1,392 @@
> >>> +/*
> >>> + * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
> >>> + *
> >>> + * This file is dual-licensed: you can use it either under the terms
> >>> + * of the GPL or the X11 license, at your option. Note that this dual
> >>> + * licensing only applies to this file, and not this project as a
> >>> + * whole.
> >>> + *
> >>> + *  a) This file is free software; you can redistribute it and/or
> >>> + *     modify it under the terms of the GNU General Public License as
> >>> + *     published by the Free Software Foundation; either version 2 of the
> >>> + *     License, or (at your option) any later version.
> >>> + *
> >>> + *     This file is distributed in the hope that it will be useful,
> >>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> >>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >>> + *     GNU General Public License for more details.
> >>> + *
> >>> + * Or, alternatively,
> >>> + *
> >>> + *  b) Permission is hereby granted, free of charge, to any person
> >>> + *     obtaining a copy of this software and associated documentation
> >>> + *     files (the "Software"), to deal in the Software without
> >>> + *     restriction, including without limitation the rights to use,
> >>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> >>> + *     sell copies of the Software, and to permit persons to whom the
> >>> + *     Software is furnished to do so, subject to the following
> >>> + *     conditions:
> >>> + *
> >>> + *     The above copyright notice and this permission notice shall be
> >>> + *     included in all copies or substantial portions of the Software.
> >>> + *
> >>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> >>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> >>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> >>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> >>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> >>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> >>> + *     OTHER DEALINGS IN THE SOFTWARE.
> >>> + */
> >>> +
> >>> +#include <dt-bindings/pinctrl/stm32-pinfunc.h>
> >>> +
> >>> +/ {
> >>> +     soc {
> >>> +             pinctrl: pin-controller {
> >>> +                     #address-cells = <1>;
> >>> +                     #size-cells = <1>;
> >>> +                     ranges = <0 0x58020000 0x3000>;
> >>> +                     interrupt-parent = <&exti>;
> >>> +                     st,syscfg = <&syscfg 0x8>;
> >>> +                     pins-are-numbered;
> >>> +
> >>> +                     gpioa: gpio@58020000 {
> >>> +                             gpio-controller;
> >>> +                             #gpio-cells = <2>;
> >>> +                             reg = <0x0 0x400>;
> >>> +                             clocks = <&rcc GPIOA_CK>;
> >>> +                             st,bank-name = "GPIOA";
> >>> +                             interrupt-controller;
> >>> +                             #interrupt-cells = <2>;
> >>> +                     };
> >>> +
> >>> +                     gpiob: gpio@58020400 {
> >>> +                             gpio-controller;
> >>> +                             #gpio-cells = <2>;
> >>> +                             reg = <0x400 0x400>;
> >>> +                             clocks = <&rcc GPIOB_CK>;
> >>> +                             st,bank-name = "GPIOB";
> >>> +                             interrupt-controller;
> >>> +                             #interrupt-cells = <2>;
> >>> +                     };
> >>> +
> >>> +                     gpioc: gpio@58020800 {
> >>> +                             gpio-controller;
> >>> +                             #gpio-cells = <2>;
> >>> +                             reg = <0x800 0x400>;
> >>> +                             clocks = <&rcc GPIOC_CK>;
> >>> +                             st,bank-name = "GPIOC";
> >>> +                             interrupt-controller;
> >>> +                             #interrupt-cells = <2>;
> >>> +                     };
> >>> +
> >>> +                     gpiod: gpio@58020c00 {
> >>> +                             gpio-controller;
> >>> +                             #gpio-cells = <2>;
> >>> +                             reg = <0xc00 0x400>;
> >>> +                             clocks = <&rcc GPIOD_CK>;
> >>> +                             st,bank-name = "GPIOD";
> >>> +                             interrupt-controller;
> >>> +                             #interrupt-cells = <2>;
> >>> +                     };
> >>> +
> >>> +                     gpioe: gpio@58021000 {
> >>> +                             gpio-controller;
> >
> >>> +                             reg = <0x1000 0x400>;
> >>> +                             clocks = <&rcc GPIOE_CK>;
> >>> +                             st,bank-name = "GPIOE";
> >>> +                             interrupt-controller;
> >>> +                             #interrupt-cells = <2>;
> >>> +                     };
> >>> +
> >>> +                     gpiof: gpio@58021400 {
> >>> +                             gpio-controller;
> >>> +                             #gpio-cells = <2>;
> >>> +                             reg = <0x1400 0x400>;
> >>> +                             clocks = <&rcc GPIOF_CK>;
> >>> +                             st,bank-name = "GPIOF";
> >>> +                             interrupt-controller;
> >>> +                             #interrupt-cells = <2>;
> >>> +                     };
> >>> +
> >>> +                     gpiog: gpio@58021800 {
> >>> +                             gpio-controller;
> >>> +                             #gpio-cells = <2>;
> >>> +                             reg = <0x1800 0x400>;
> >>> +                             clocks = <&rcc GPIOG_CK>;
> >>> +                             st,bank-name = "GPIOG";
> >>> +                             interrupt-controller;
> >>> +                             #interrupt-cells = <2>;
> >>> +                     };
> >>> +
> >>> +                     gpioh: gpio@58021c00 {
> >>> +                             gpio-controller;
> >>> +                             #gpio-cells = <2>;
> >>> +                             reg = <0x1c00 0x400>;
> >>> +                             clocks = <&rcc GPIOH_CK>;
> >>> +                             st,bank-name = "GPIOH";
> >>> +                             interrupt-controller;
> >>> +                             #interrupt-cells = <2>;
> >>> +                     };
> >>> +
> >>> +                     gpioi: gpio@58022000 {
> >>> +                             gpio-controller;
> >>> +                             #gpio-cells = <2>;
> >>> +                             reg = <0x2000 0x400>;
> >>> +                             clocks = <&rcc GPIOI_CK>;
> >>> +                             st,bank-name = "GPIOI";
> >>> +                             interrupt-controller;
> >>> +                             #interrupt-cells = <2>;
> >>> +                     };
> >>> +
> >>> +                     gpioj: gpio@58022400 {
> >>> +                             gpio-controller;
> >>> +                             #gpio-cells = <2>;
> >>> +                             reg = <0x2400 0x400>;
> >>> +                             clocks = <&rcc GPIOJ_CK>;
> >>> +                             st,bank-name = "GPIOJ";
> >>> +                             interrupt-controller;
> >>> +                             #interrupt-cells = <2>;
> >>> +                     };
> >>> +
> >>> +                     gpiok: gpio@58022800 {
> >>> +                             gpio-controller;
> >>> +                             #gpio-cells = <2>;
> >>> +                             reg = <0x2800 0x400>;
> >>> +                             clocks = <&rcc GPIOK_CK>;
> >>> +                             st,bank-name = "GPIOK";
> >>> +                             interrupt-controller;
> >>> +                             #interrupt-cells = <2>;
> >>> +                     };
> >>> +
> >>> +                     i2c1_pins_a: i2c1-0 {
> >>> +                             pins {
> >>> +                                     pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
> >>> +                                              <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
> >>> +                                     bias-disable;
> >>> +                                     drive-open-drain;
> >>> +                                     slew-rate = <0>;
> >>> +                             };
> >>> +                     };
> >>> +
> >>> +                     ethernet_rmii: rmii-0 {
> >>> +                             pins {
> >>> +                                     pinmux = <STM32_PINMUX('G', 11, AF11)>,
> >>> +                                              <STM32_PINMUX('G', 13, AF11)>,
> >>> +                                              <STM32_PINMUX('G', 12, AF11)>,
> >>> +                                              <STM32_PINMUX('C', 4, AF11)>,
> >>> +                                              <STM32_PINMUX('C', 5, AF11)>,
> >>> +                                              <STM32_PINMUX('A', 7, AF11)>,
> >>> +                                              <STM32_PINMUX('C', 1, AF11)>,
> >>> +                                              <STM32_PINMUX('A', 2, AF11)>,
> >>> +                                              <STM32_PINMUX('A', 1, AF11)>;
> >>> +                                     slew-rate = <2>;
> >>> +                             };
> >>> +                     };
> >>> +
> >>> +                     sdmmc1_b4_pins_a: sdmmc1-b4-0 {
> >>> +                             pins {
> >>> +                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
> >>> +                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
> >>> +                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
> >>> +                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
> >>> +                                              <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
> >>> +                                              <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
> >>> +                                     slew-rate = <3>;
> >>> +                                     drive-push-pull;
> >>> +                                     bias-disable;
> >>> +                             };
> >>> +                     };
> >>> +
> >>> +                     sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
> >>> +                             pins1 {
> >>> +                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
> >>> +                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
> >>> +                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
> >>> +                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
> >>> +                                              <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
> >>> +                                     slew-rate = <3>;
> >>> +                                     drive-push-pull;
> >>> +                                     bias-disable;
> >>> +                             };
> >>> +                             pins2{
> >>> +                                     pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
> >>> +                                     slew-rate = <3>;
> >>> +                                     drive-open-drain;
> >>> +                                     bias-disable;
> >>> +                             };
> >>> +                     };
> >>> +
> >>> +                     sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
> >>> +                             pins {
> >>> +                                     pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
> >>> +                                              <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
> >>> +                                              <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
> >>> +                                              <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
> >>> +                                              <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
> >>> +                                              <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
> >>> +                             };
> >>> +                     };
> >>> +
> >>> +                     sdmmc2_b4_pins_a: sdmmc2-b4-0 {
> >>> +                             pins {
> >>> +                                     pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */
> >>> +                                              <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
> >>> +                                              <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
> >>> +                                              <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
> >>> +                                              <STM32_PINMUX('D', 6, AF11)>, /* SDMMC1_CK */
> >>> +                                              <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
> >>> +                                     slew-rate = <3>;
> >>> +                                     drive-push-pull;
> >>> +                                     bias-disable;
> >>> +                             };
> >>> +                     };
> >>> +
> >>> +                     sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
> >>> +                             pins1 {
> >>> +                                     pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
> >>> +                                              <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
> >>> +                                              <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
> >>> +                                              <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
> >>> +                                              <STM32_PINMUX('D', 6, AF11)>; /* SDMMC1_CK */
> >>> +                                     slew-rate = <3>;
> >>> +                                     drive-push-pull;
> >>> +                                     bias-disable;
> >>> +                             };
> >>> +                             pins2{
> >>> +                                     pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
> >>> +                                     slew-rate = <3>;
> >>> +                                     drive-open-drain;
> >>> +                                     bias-disable;
> >>> +                             };
> >>> +                     };
> >>> +
> >>> +                     sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
> >>> +                             pins {
> >>> +                                     pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC1_D0 */
> >>> +                                              <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC1_D1 */
> >>> +                                              <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC1_D2 */
> >>> +                                              <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC1_D3 */
> >>> +                                              <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC1_CK */
> >>> +                                              <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC1_CMD */
> >>> +                             };
> >>> +                     };
> >>> +
> >>> +                     sdmmc1_dir_pins_a: sdmmc1-dir-0 {
> >>> +                             pins1 {
> >>> +                                     pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
> >>> +                                              <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
> >>> +                                              <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
> >>> +                                     slew-rate = <3>;
> >>> +                                     drive-push-pull;
> >>> +                                     bias-pull-up;
> >>> +                             };
> >>> +                             pins2{
> >>> +                                     pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
> >>> +                                     bias-pull-up;
> >>> +                             };
> >>> +                     };
> >>> +
> >>> +                     sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
> >>> +                             pins {
> >>> +                                     pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
> >>> +                                              <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
> >>> +                                              <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
> >>> +                                              <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
> >>> +                             };
> >>> +                     };
> >>> +
> >>> +                     usart1_pins: usart1-0 {
> >>> +                             pins1 {
> >>> +                                     pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
> >>> +                                     bias-disable;
> >>> +                                     drive-push-pull;
> >>> +                                     slew-rate = <0>;
> >>> +                             };
> >>> +                             pins2 {
> >>> +                                     pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
> >>> +                                     bias-disable;
> >>> +                             };
> >>> +                     };
> >>> +
> >>> +                     usart2_pins: usart2-0 {
> >>> +                             pins1 {
> >>> +                                     pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
> >>> +                                     bias-disable;
> >>> +                                     drive-push-pull;
> >>> +                                     slew-rate = <0>;
> >>> +                             };
> >>> +                             pins2 {
> >>> +                                     pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
> >>> +                                     bias-disable;
> >>> +                             };
> >>> +                     };
> >>> +
> >>> +                     usart3_pins: usart3-0 {
> >>> +                             pins1 {
> >>> +                                     pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
> >>> +                                     bias-disable;
> >>> +                                     drive-push-pull;
> >>> +                                     slew-rate = <0>;
> >>> +                             };
> >>> +                             pins2 {
> >>> +                                     pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
> >>> +                                     bias-disable;
> >>> +                             };
> >>> +                     };
> >>> +
> >>> +                     uart4_pins: uart4-0 {
> >>> +                             pins1 {
> >>> +                                     pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */
> >>> +                                     bias-disable;
> >>> +                                     drive-push-pull;
> >>> +                                     slew-rate = <0>;
> >>> +                             };
> >>> +                             pins2 {
> >>> +                                     pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */
> >>> +                                     bias-disable;
> >>> +                             };
> >>> +                     };
> >>> +
> >>> +                     usbotg_hs_pins_a: usbotg-hs-0 {
> >>> +                             pins {
> >>> +                                     pinmux = <STM32_PINMUX('H', 4, AF10)>,  /* ULPI_NXT */
> >>> +                                                      <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
> >>> +                                                      <STM32_PINMUX('C', 0, AF10)>,  /* ULPI_STP> */
> >>> +                                                      <STM32_PINMUX('A', 5, AF10)>,  /* ULPI_CK> */
> >>> +                                                      <STM32_PINMUX('A', 3, AF10)>,  /* ULPI_D0> */
> >>> +                                                      <STM32_PINMUX('B', 0, AF10)>,  /* ULPI_D1> */
> >>> +                                                      <STM32_PINMUX('B', 1, AF10)>,  /* ULPI_D2> */
> >>> +                                                      <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
> >>> +                                                      <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
> >>> +                                                      <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
> >>> +                                                      <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
> >>> +                                                      <STM32_PINMUX('B', 5, AF10)>;  /* ULPI_D7> */
> >>> +                                     bias-disable;
> >>> +                                     drive-push-pull;
> >>> +                                     slew-rate = <2>;
> >>> +                             };
> >>> +                     };
> >>> +
> >>> +                     spi1_pins: spi1-0 {
> >>> +                             pins1 {
> >>> +                                     pinmux = <STM32_PINMUX('A', 5, AF5)>,
> >>> +                                             /* SPI1_CLK */
> >>> +                                              <STM32_PINMUX('B', 5, AF5)>;
> >>> +                                             /* SPI1_MOSI */
> >>> +                                     bias-disable;
> >>> +                                     drive-push-pull;
> >>> +                                     slew-rate = <2>;
> >>> +                             };
> >>> +                             pins2 {
> >>> +                                     pinmux = <STM32_PINMUX('G', 9, AF5)>;
> >>> +                                             /* SPI1_MISO */
> >>> +                                     bias-disable;
> >>> +                             };
> >>> +                     };
> >>> +             };
> >>> +     };
> >>> +};
> >>> diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
> >>> index fa5dcb6a5fdd..6b1e115307b9 100644
> >>> --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
> >>> +++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
> >>> @@ -1,306 +1,11 @@
> >>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> >>>    /*
> >>> - * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
> >>> - *
> >>> - * This file is dual-licensed: you can use it either under the terms
> >>> - * of the GPL or the X11 license, at your option. Note that this dual
> >>> - * licensing only applies to this file, and not this project as a
> >>> - * whole.
> >>> - *
> >>> - *  a) This file is free software; you can redistribute it and/or
> >>> - *     modify it under the terms of the GNU General Public License as
> >>> - *     published by the Free Software Foundation; either version 2 of the
> >>> - *     License, or (at your option) any later version.
> >>> - *
> >>> - *     This file is distributed in the hope that it will be useful,
> >>> - *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> >>> - *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >>> - *     GNU General Public License for more details.
> >>> - *
> >>> - * Or, alternatively,
> >>> - *
> >>> - *  b) Permission is hereby granted, free of charge, to any person
> >>> - *     obtaining a copy of this software and associated documentation
> >>> - *     files (the "Software"), to deal in the Software without
> >>> - *     restriction, including without limitation the rights to use,
> >>> - *     copy, modify, merge, publish, distribute, sublicense, and/or
> >>> - *     sell copies of the Software, and to permit persons to whom the
> >>> - *     Software is furnished to do so, subject to the following
> >>> - *     conditions:
> >>> - *
> >>> - *     The above copyright notice and this permission notice shall be
> >>> - *     included in all copies or substantial portions of the Software.
> >>> - *
> >>> - *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >>> - *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> >>> - *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> >>> - *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> >>> - *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> >>> - *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> >>> - *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> >>> - *     OTHER DEALINGS IN THE SOFTWARE.
> >>> + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
> >>> + * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
> >>>     */
> >>>
> >>> -#include <dt-bindings/pinctrl/stm32-pinfunc.h>
> >>> +#include "stm32h7-pinctrl.dtsi"
> >>>
> >>> -/ {
> >>> -     soc {
> >>> -             pin-controller {
> >>> -                     #address-cells = <1>;
> >>> -                     #size-cells = <1>;
> >>> -                     compatible = "st,stm32h743-pinctrl";
> >>> -                     ranges = <0 0x58020000 0x3000>;
> >>> -                     interrupt-parent = <&exti>;
> >>> -                     st,syscfg = <&syscfg 0x8>;
> >>> -                     pins-are-numbered;
> >>> -
> >>> -                     gpioa: gpio@58020000 {
> >>> -                             gpio-controller;
> >>> -                             #gpio-cells = <2>;
> >>> -                             reg = <0x0 0x400>;
> >>> -                             clocks = <&rcc GPIOA_CK>;
> >>> -                             st,bank-name = "GPIOA";
> >>> -                             interrupt-controller;
> >>> -                             #interrupt-cells = <2>;
> >>> -                     };
> >>> -
> >>> -                     gpiob: gpio@58020400 {
> >>> -                             gpio-controller;
> >>> -                             #gpio-cells = <2>;
> >>> -                             reg = <0x400 0x400>;
> >>> -                             clocks = <&rcc GPIOB_CK>;
> >>> -                             st,bank-name = "GPIOB";
> >>> -                             interrupt-controller;
> >>> -                             #interrupt-cells = <2>;
> >>> -                     };
> >>> -
> >>> -                     gpioc: gpio@58020800 {
> >>> -                             gpio-controller;
> >>> -                             #gpio-cells = <2>;
> >>> -                             reg = <0x800 0x400>;
> >>> -                             clocks = <&rcc GPIOC_CK>;
> >>> -                             st,bank-name = "GPIOC";
> >>> -                             interrupt-controller;
> >>> -                             #interrupt-cells = <2>;
> >>> -                     };
> >>> -
> >>> -                     gpiod: gpio@58020c00 {
> >>> -                             gpio-controller;
> >>> -                             #gpio-cells = <2>;
> >>> -                             reg = <0xc00 0x400>;
> >>> -                             clocks = <&rcc GPIOD_CK>;
> >>> -                             st,bank-name = "GPIOD";
> >>> -                             interrupt-controller;
> >>> -                             #interrupt-cells = <2>;
> >>> -                     };
> >>> -
> >>> -                     gpioe: gpio@58021000 {
> >>> -                             gpio-controller;
> >>> -                             #gpio-cells = <2>;
> >>> -                             reg = <0x1000 0x400>;
> >>> -                             clocks = <&rcc GPIOE_CK>;
> >>> -                             st,bank-name = "GPIOE";
> >>> -                             interrupt-controller;
> >>> -                             #interrupt-cells = <2>;
> >>> -                     };
> >>> -
> >>> -                     gpiof: gpio@58021400 {
> >>> -                             gpio-controller;
> >>> -                             #gpio-cells = <2>;
> >>> -                             reg = <0x1400 0x400>;
> >>> -                             clocks = <&rcc GPIOF_CK>;
> >>> -                             st,bank-name = "GPIOF";
> >>> -                             interrupt-controller;
> >>> -                             #interrupt-cells = <2>;
> >>> -                     };
> >>> -
> >>> -                     gpiog: gpio@58021800 {
> >>> -                             gpio-controller;
> >>> -                             #gpio-cells = <2>;
> >>> -                             reg = <0x1800 0x400>;
> >>> -                             clocks = <&rcc GPIOG_CK>;
> >>> -                             st,bank-name = "GPIOG";
> >>> -                             interrupt-controller;
> >>> -                             #interrupt-cells = <2>;
> >>> -                     };
> >>> -
> >>> -                     gpioh: gpio@58021c00 {
> >>> -                             gpio-controller;
> >>> -                             #gpio-cells = <2>;
> >>> -                             reg = <0x1c00 0x400>;
> >>> -                             clocks = <&rcc GPIOH_CK>;
> >>> -                             st,bank-name = "GPIOH";
> >>> -                             interrupt-controller;
> >>> -                             #interrupt-cells = <2>;
> >>> -                     };
> >>> -
> >>> -                     gpioi: gpio@58022000 {
> >>> -                             gpio-controller;
> >>> -                             #gpio-cells = <2>;
> >>> -                             reg = <0x2000 0x400>;
> >>> -                             clocks = <&rcc GPIOI_CK>;
> >>> -                             st,bank-name = "GPIOI";
> >>> -                             interrupt-controller;
> >>> -                             #interrupt-cells = <2>;
> >>> -                     };
> >>> -
> >>> -                     gpioj: gpio@58022400 {
> >>> -                             gpio-controller;
> >>> -                             #gpio-cells = <2>;
> >>> -                             reg = <0x2400 0x400>;
> >>> -                             clocks = <&rcc GPIOJ_CK>;
> >>> -                             st,bank-name = "GPIOJ";
> >>> -                             interrupt-controller;
> >>> -                             #interrupt-cells = <2>;
> >>> -                     };
> >>> -
> >>> -                     gpiok: gpio@58022800 {
> >>> -                             gpio-controller;
> >>> -                             #gpio-cells = <2>;
> >>> -                             reg = <0x2800 0x400>;
> >>> -                             clocks = <&rcc GPIOK_CK>;
> >>> -                             st,bank-name = "GPIOK";
> >>> -                             interrupt-controller;
> >>> -                             #interrupt-cells = <2>;
> >>> -                     };
> >>> -
> >>> -                     i2c1_pins_a: i2c1-0 {
> >>> -                             pins {
> >>> -                                     pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
> >>> -                                              <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
> >>> -                                     bias-disable;
> >>> -                                     drive-open-drain;
> >>> -                                     slew-rate = <0>;
> >>> -                             };
> >>> -                     };
> >>> -
> >>> -                     ethernet_rmii: rmii-0 {
> >>> -                             pins {
> >>> -                                     pinmux = <STM32_PINMUX('G', 11, AF11)>,
> >>> -                                              <STM32_PINMUX('G', 13, AF11)>,
> >>> -                                              <STM32_PINMUX('G', 12, AF11)>,
> >>> -                                              <STM32_PINMUX('C', 4, AF11)>,
> >>> -                                              <STM32_PINMUX('C', 5, AF11)>,
> >>> -                                              <STM32_PINMUX('A', 7, AF11)>,
> >>> -                                              <STM32_PINMUX('C', 1, AF11)>,
> >>> -                                              <STM32_PINMUX('A', 2, AF11)>,
> >>> -                                              <STM32_PINMUX('A', 1, AF11)>;
> >>> -                                     slew-rate = <2>;
> >>> -                             };
> >>> -                     };
> >>> -
> >>> -                     sdmmc1_b4_pins_a: sdmmc1-b4-0 {
> >>> -                             pins {
> >>> -                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
> >>> -                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
> >>> -                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
> >>> -                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
> >>> -                                              <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
> >>> -                                              <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
> >>> -                                     slew-rate = <3>;
> >>> -                                     drive-push-pull;
> >>> -                                     bias-disable;
> >>> -                             };
> >>> -                     };
> >>> -
> >>> -                     sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
> >>> -                             pins1 {
> >>> -                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
> >>> -                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
> >>> -                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
> >>> -                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
> >>> -                                              <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
> >>> -                                     slew-rate = <3>;
> >>> -                                     drive-push-pull;
> >>> -                                     bias-disable;
> >>> -                             };
> >>> -                             pins2{
> >>> -                                     pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
> >>> -                                     slew-rate = <3>;
> >>> -                                     drive-open-drain;
> >>> -                                     bias-disable;
> >>> -                             };
> >>> -                     };
> >>> -
> >>> -                     sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
> >>> -                             pins {
> >>> -                                     pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
> >>> -                                              <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
> >>> -                                              <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
> >>> -                                              <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
> >>> -                                              <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
> >>> -                                              <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
> >>> -                             };
> >>> -                     };
> >>> -
> >>> -                     sdmmc1_dir_pins_a: sdmmc1-dir-0 {
> >>> -                             pins1 {
> >>> -                                     pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
> >>> -                                              <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
> >>> -                                              <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
> >>> -                                     slew-rate = <3>;
> >>> -                                     drive-push-pull;
> >>> -                                     bias-pull-up;
> >>> -                             };
> >>> -                             pins2{
> >>> -                                     pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
> >>> -                                     bias-pull-up;
> >>> -                             };
> >>> -                     };
> >>> -
> >>> -                     sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
> >>> -                             pins {
> >>> -                                     pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
> >>> -                                              <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
> >>> -                                              <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
> >>> -                                              <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
> >>> -                             };
> >>> -                     };
> >>> -
> >>> -                     usart1_pins: usart1-0 {
> >>> -                             pins1 {
> >>> -                                     pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
> >>> -                                     bias-disable;
> >>> -                                     drive-push-pull;
> >>> -                                     slew-rate = <0>;
> >>> -                             };
> >>> -                             pins2 {
> >>> -                                     pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
> >>> -                                     bias-disable;
> >>> -                             };
> >>> -                     };
> >>> -
> >>> -                     usart2_pins: usart2-0 {
> >>> -                             pins1 {
> >>> -                                     pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
> >>> -                                     bias-disable;
> >>> -                                     drive-push-pull;
> >>> -                                     slew-rate = <0>;
> >>> -                             };
> >>> -                             pins2 {
> >>> -                                     pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
> >>> -                                     bias-disable;
> >>> -                             };
> >>> -                     };
> >>> -
> >>> -                     usbotg_hs_pins_a: usbotg-hs-0 {
> >>> -                             pins {
> >>> -                                     pinmux = <STM32_PINMUX('H', 4, AF10)>,  /* ULPI_NXT */
> >>> -                                                      <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
> >>> -                                                      <STM32_PINMUX('C', 0, AF10)>,  /* ULPI_STP> */
> >>> -                                                      <STM32_PINMUX('A', 5, AF10)>,  /* ULPI_CK> */
> >>> -                                                      <STM32_PINMUX('A', 3, AF10)>,  /* ULPI_D0> */
> >>> -                                                      <STM32_PINMUX('B', 0, AF10)>,  /* ULPI_D1> */
> >>> -                                                      <STM32_PINMUX('B', 1, AF10)>,  /* ULPI_D2> */
> >>> -                                                      <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
> >>> -                                                      <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
> >>> -                                                      <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
> >>> -                                                      <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
> >>> -                                                      <STM32_PINMUX('B', 5, AF10)>;  /* ULPI_D7> */
> >>> -                                     bias-disable;
> >>> -                                     drive-push-pull;
> >>> -                                     slew-rate = <2>;
> >>> -                             };
> >>> -                     };
> >>> -             };
> >>> -     };
> >>> +&pinctrl{
> >>> +     compatible = "st,stm32h743-pinctrl";
> >>>    };
> >>>

Re: [PATCH 5/8] ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h75x

[Alexandre TORGUE]

On 3/11/21 3:32 PM, dillon min wrote:
> Hi Alexandre
> 
> On Thu, Mar 11, 2021 at 9:30 PM Alexandre TORGUE
> <alexandre.torgue@foss.st.com> wrote:
>>
>> Hi Dillon
>>
>> On 3/11/21 1:23 PM, dillon min wrote:
>>> Hi Alexandre
>>>
>>> On Thu, Mar 11, 2021 at 6:40 PM Alexandre TORGUE
>>> <alexandre.torgue@foss.st.com> wrote:
>>>>
>>>> Hi Dillon
>>>>
>>>> On 3/3/21 9:05 AM, dillon.minfei@gmail.com wrote:
>>>>> From: dillon min <dillon.minfei@gmail.com>
>>>>>
>>>>> To support stm32h750 and stm32h743, we need a base stm32h7-pinctrl.dtsi
>>>>> as stm32h743 & h750 has almost the same interface. so, just rename
>>>>> stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi
>>>>>
>>>>
>>>> You do not "just" rename but you keel also the old version. I don't
>>>> agree with this approach. You have first to rename
>>>> stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi (keeping copyright as
>>>> they are please) and modify existing H7 boards which currently use
>>>> stm32h743-pinctrl.dtsi.
>>>> Then you create a second patch adding your pingroups.
>>> For stm32h7's new board support , I guess following the stm32f7/stm32f4's style
>>
>> Yes sorry, I read it too quickly
>>
>>> is a reasonable way to do it, but add a little optimization。
>>> which means :
>>> old structure
>>> stm32h7-pinctrl.dtsi --> stm32h743-pinctrl.dtsi  (referenced by
>>> stm32h743i-disco, -eval)
>>>                                   |--> stm32h750-pinctrl.dtsi
>>> (referenced by stm32h750i-art-pi, etc)
>>> add art-pi other board's pin definition in stm32h750-pinctrl.dtsi with
>>> xxx_pins_a, xxx_pins_b
>>> xxx_pins_a used for art-pi, xxx_pins_b used for other boards.
>>>
>>> after more boards add in support, there will be more xxx_pin_c, .... defined
>>>
>>> as the pin map is according to the hardware schematic diagram io connection.
>>> so, why not move xxx_pin_x to a board specific place. such as
>>> stm32h750i-art-pi.dts
>>>
>>> new structure:
>>> 1, rename stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi (only
>>> preserve gpioa...k,)
>>> 2, move xxx_pins_x from stm32h7-pinctrl.dtsi to
>>> stm32h7xx-disco/eval/art-pi/etc.dts (as they depends on hardware
>>> schematic)
>>>
>>> stm32h7-pinctrl.dtsi --> stm32h743i-discon.dts
>>>                                   |--> stm32h743i-eval.dts
>>>                                   |--> stm32h750i-art-pi.dts
>>>                                   |--> stm32h7xxx.dts
>>> would you agree this ?
>>
>> :) it remember me an old discussion we had with Ahmad or Marek. My first
>> feeling is "The group definition follow the SoC, and the group choice is
>> done on the board". But As said in the past I have to think more about
>> this topic and check how it could be reorganize (as it would be nice to
>> have the same approach for MPU and MCU boards.) I'll try to post
>> something soon. Waiting that this patch looks. As you mainly change the
>> name can you keep please header (copyright) as they were initially.
> Okay, got it. before your patch for pinctrl update. I am just totally following
> your current style.
> For file author name, copyright. i'm really sorry for that. this is
> the first time for me
> to add a board support, i'm not intended to replace with my name, just too
> many files to change, wasn't beware of the difference with author name for new
> created file and existing file . will be changed back in the next submit.

No problem Dillon, it is minor comments, anyway thanks for adding this 
new STM32 SoC.

Regards

>>>>
>>>> Now regarding "st,stm32h750-pinctrl", I see a patch dealing with this
>>>> new binding but no update on driver side. Do I miss something ? what are
>>>> differences between h743 and h750 regarding pinctrl ?
>>> Oh, i forget to add pin driver under drivers/pinctrl/stm32/
>>> will add it next time.
>>>>
>>>> Regards
>>>> Alex
>>>>
>>>>> Signed-off-by: dillon min <dillon.minfei@gmail.com>
>>>>> ---
>>>>>     arch/arm/boot/dts/stm32h7-pinctrl.dtsi   | 392 +++++++++++++++++++++++++++++++
>>>>>     arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 307 +-----------------------
>>>>>     2 files changed, 398 insertions(+), 301 deletions(-)
>>>>>     create mode 100644 arch/arm/boot/dts/stm32h7-pinctrl.dtsi
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi
>>>>> new file mode 100644
>>>>> index 000000000000..7d4b5d683ccc
>>>>> --- /dev/null
>>>>> +++ b/arch/arm/boot/dts/stm32h7-pinctrl.dtsi
>>>>> @@ -0,0 +1,392 @@
>>>>> +/*
>>>>> + * Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
>>>>> + *
>>>>> + * This file is dual-licensed: you can use it either under the terms
>>>>> + * of the GPL or the X11 license, at your option. Note that this dual
>>>>> + * licensing only applies to this file, and not this project as a
>>>>> + * whole.
>>>>> + *
>>>>> + *  a) This file is free software; you can redistribute it and/or
>>>>> + *     modify it under the terms of the GNU General Public License as
>>>>> + *     published by the Free Software Foundation; either version 2 of the
>>>>> + *     License, or (at your option) any later version.
>>>>> + *
>>>>> + *     This file is distributed in the hope that it will be useful,
>>>>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>>>> + *     GNU General Public License for more details.
>>>>> + *
>>>>> + * Or, alternatively,
>>>>> + *
>>>>> + *  b) Permission is hereby granted, free of charge, to any person
>>>>> + *     obtaining a copy of this software and associated documentation
>>>>> + *     files (the "Software"), to deal in the Software without
>>>>> + *     restriction, including without limitation the rights to use,
>>>>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>>>>> + *     sell copies of the Software, and to permit persons to whom the
>>>>> + *     Software is furnished to do so, subject to the following
>>>>> + *     conditions:
>>>>> + *
>>>>> + *     The above copyright notice and this permission notice shall be
>>>>> + *     included in all copies or substantial portions of the Software.
>>>>> + *
>>>>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>>>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>>>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>>>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>>>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>>>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>>>> + *     OTHER DEALINGS IN THE SOFTWARE.
>>>>> + */
>>>>> +
>>>>> +#include <dt-bindings/pinctrl/stm32-pinfunc.h>
>>>>> +
>>>>> +/ {
>>>>> +     soc {
>>>>> +             pinctrl: pin-controller {
>>>>> +                     #address-cells = <1>;
>>>>> +                     #size-cells = <1>;
>>>>> +                     ranges = <0 0x58020000 0x3000>;
>>>>> +                     interrupt-parent = <&exti>;
>>>>> +                     st,syscfg = <&syscfg 0x8>;
>>>>> +                     pins-are-numbered;
>>>>> +
>>>>> +                     gpioa: gpio@58020000 {
>>>>> +                             gpio-controller;
>>>>> +                             #gpio-cells = <2>;
>>>>> +                             reg = <0x0 0x400>;
>>>>> +                             clocks = <&rcc GPIOA_CK>;
>>>>> +                             st,bank-name = "GPIOA";
>>>>> +                             interrupt-controller;
>>>>> +                             #interrupt-cells = <2>;
>>>>> +                     };
>>>>> +
>>>>> +                     gpiob: gpio@58020400 {
>>>>> +                             gpio-controller;
>>>>> +                             #gpio-cells = <2>;
>>>>> +                             reg = <0x400 0x400>;
>>>>> +                             clocks = <&rcc GPIOB_CK>;
>>>>> +                             st,bank-name = "GPIOB";
>>>>> +                             interrupt-controller;
>>>>> +                             #interrupt-cells = <2>;
>>>>> +                     };
>>>>> +
>>>>> +                     gpioc: gpio@58020800 {
>>>>> +                             gpio-controller;
>>>>> +                             #gpio-cells = <2>;
>>>>> +                             reg = <0x800 0x400>;
>>>>> +                             clocks = <&rcc GPIOC_CK>;
>>>>> +                             st,bank-name = "GPIOC";
>>>>> +                             interrupt-controller;
>>>>> +                             #interrupt-cells = <2>;
>>>>> +                     };
>>>>> +
>>>>> +                     gpiod: gpio@58020c00 {
>>>>> +                             gpio-controller;
>>>>> +                             #gpio-cells = <2>;
>>>>> +                             reg = <0xc00 0x400>;
>>>>> +                             clocks = <&rcc GPIOD_CK>;
>>>>> +                             st,bank-name = "GPIOD";
>>>>> +                             interrupt-controller;
>>>>> +                             #interrupt-cells = <2>;
>>>>> +                     };
>>>>> +
>>>>> +                     gpioe: gpio@58021000 {
>>>>> +                             gpio-controller;
>>>
>>>>> +                             reg = <0x1000 0x400>;
>>>>> +                             clocks = <&rcc GPIOE_CK>;
>>>>> +                             st,bank-name = "GPIOE";
>>>>> +                             interrupt-controller;
>>>>> +                             #interrupt-cells = <2>;
>>>>> +                     };
>>>>> +
>>>>> +                     gpiof: gpio@58021400 {
>>>>> +                             gpio-controller;
>>>>> +                             #gpio-cells = <2>;
>>>>> +                             reg = <0x1400 0x400>;
>>>>> +                             clocks = <&rcc GPIOF_CK>;
>>>>> +                             st,bank-name = "GPIOF";
>>>>> +                             interrupt-controller;
>>>>> +                             #interrupt-cells = <2>;
>>>>> +                     };
>>>>> +
>>>>> +                     gpiog: gpio@58021800 {
>>>>> +                             gpio-controller;
>>>>> +                             #gpio-cells = <2>;
>>>>> +                             reg = <0x1800 0x400>;
>>>>> +                             clocks = <&rcc GPIOG_CK>;
>>>>> +                             st,bank-name = "GPIOG";
>>>>> +                             interrupt-controller;
>>>>> +                             #interrupt-cells = <2>;
>>>>> +                     };
>>>>> +
>>>>> +                     gpioh: gpio@58021c00 {
>>>>> +                             gpio-controller;
>>>>> +                             #gpio-cells = <2>;
>>>>> +                             reg = <0x1c00 0x400>;
>>>>> +                             clocks = <&rcc GPIOH_CK>;
>>>>> +                             st,bank-name = "GPIOH";
>>>>> +                             interrupt-controller;
>>>>> +                             #interrupt-cells = <2>;
>>>>> +                     };
>>>>> +
>>>>> +                     gpioi: gpio@58022000 {
>>>>> +                             gpio-controller;
>>>>> +                             #gpio-cells = <2>;
>>>>> +                             reg = <0x2000 0x400>;
>>>>> +                             clocks = <&rcc GPIOI_CK>;
>>>>> +                             st,bank-name = "GPIOI";
>>>>> +                             interrupt-controller;
>>>>> +                             #interrupt-cells = <2>;
>>>>> +                     };
>>>>> +
>>>>> +                     gpioj: gpio@58022400 {
>>>>> +                             gpio-controller;
>>>>> +                             #gpio-cells = <2>;
>>>>> +                             reg = <0x2400 0x400>;
>>>>> +                             clocks = <&rcc GPIOJ_CK>;
>>>>> +                             st,bank-name = "GPIOJ";
>>>>> +                             interrupt-controller;
>>>>> +                             #interrupt-cells = <2>;
>>>>> +                     };
>>>>> +
>>>>> +                     gpiok: gpio@58022800 {
>>>>> +                             gpio-controller;
>>>>> +                             #gpio-cells = <2>;
>>>>> +                             reg = <0x2800 0x400>;
>>>>> +                             clocks = <&rcc GPIOK_CK>;
>>>>> +                             st,bank-name = "GPIOK";
>>>>> +                             interrupt-controller;
>>>>> +                             #interrupt-cells = <2>;
>>>>> +                     };
>>>>> +
>>>>> +                     i2c1_pins_a: i2c1-0 {
>>>>> +                             pins {
>>>>> +                                     pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
>>>>> +                                              <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
>>>>> +                                     bias-disable;
>>>>> +                                     drive-open-drain;
>>>>> +                                     slew-rate = <0>;
>>>>> +                             };
>>>>> +                     };
>>>>> +
>>>>> +                     ethernet_rmii: rmii-0 {
>>>>> +                             pins {
>>>>> +                                     pinmux = <STM32_PINMUX('G', 11, AF11)>,
>>>>> +                                              <STM32_PINMUX('G', 13, AF11)>,
>>>>> +                                              <STM32_PINMUX('G', 12, AF11)>,
>>>>> +                                              <STM32_PINMUX('C', 4, AF11)>,
>>>>> +                                              <STM32_PINMUX('C', 5, AF11)>,
>>>>> +                                              <STM32_PINMUX('A', 7, AF11)>,
>>>>> +                                              <STM32_PINMUX('C', 1, AF11)>,
>>>>> +                                              <STM32_PINMUX('A', 2, AF11)>,
>>>>> +                                              <STM32_PINMUX('A', 1, AF11)>;
>>>>> +                                     slew-rate = <2>;
>>>>> +                             };
>>>>> +                     };
>>>>> +
>>>>> +                     sdmmc1_b4_pins_a: sdmmc1-b4-0 {
>>>>> +                             pins {
>>>>> +                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
>>>>> +                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
>>>>> +                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
>>>>> +                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
>>>>> +                                              <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
>>>>> +                                              <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
>>>>> +                                     slew-rate = <3>;
>>>>> +                                     drive-push-pull;
>>>>> +                                     bias-disable;
>>>>> +                             };
>>>>> +                     };
>>>>> +
>>>>> +                     sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
>>>>> +                             pins1 {
>>>>> +                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
>>>>> +                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
>>>>> +                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
>>>>> +                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
>>>>> +                                              <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
>>>>> +                                     slew-rate = <3>;
>>>>> +                                     drive-push-pull;
>>>>> +                                     bias-disable;
>>>>> +                             };
>>>>> +                             pins2{
>>>>> +                                     pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
>>>>> +                                     slew-rate = <3>;
>>>>> +                                     drive-open-drain;
>>>>> +                                     bias-disable;
>>>>> +                             };
>>>>> +                     };
>>>>> +
>>>>> +                     sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
>>>>> +                             pins {
>>>>> +                                     pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
>>>>> +                                              <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
>>>>> +                                              <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
>>>>> +                                              <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
>>>>> +                                              <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
>>>>> +                                              <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
>>>>> +                             };
>>>>> +                     };
>>>>> +
>>>>> +                     sdmmc2_b4_pins_a: sdmmc2-b4-0 {
>>>>> +                             pins {
>>>>> +                                     pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */
>>>>> +                                              <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
>>>>> +                                              <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
>>>>> +                                              <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
>>>>> +                                              <STM32_PINMUX('D', 6, AF11)>, /* SDMMC1_CK */
>>>>> +                                              <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
>>>>> +                                     slew-rate = <3>;
>>>>> +                                     drive-push-pull;
>>>>> +                                     bias-disable;
>>>>> +                             };
>>>>> +                     };
>>>>> +
>>>>> +                     sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
>>>>> +                             pins1 {
>>>>> +                                     pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
>>>>> +                                              <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
>>>>> +                                              <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
>>>>> +                                              <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
>>>>> +                                              <STM32_PINMUX('D', 6, AF11)>; /* SDMMC1_CK */
>>>>> +                                     slew-rate = <3>;
>>>>> +                                     drive-push-pull;
>>>>> +                                     bias-disable;
>>>>> +                             };
>>>>> +                             pins2{
>>>>> +                                     pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
>>>>> +                                     slew-rate = <3>;
>>>>> +                                     drive-open-drain;
>>>>> +                                     bias-disable;
>>>>> +                             };
>>>>> +                     };
>>>>> +
>>>>> +                     sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
>>>>> +                             pins {
>>>>> +                                     pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC1_D0 */
>>>>> +                                              <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC1_D1 */
>>>>> +                                              <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC1_D2 */
>>>>> +                                              <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC1_D3 */
>>>>> +                                              <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC1_CK */
>>>>> +                                              <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC1_CMD */
>>>>> +                             };
>>>>> +                     };
>>>>> +
>>>>> +                     sdmmc1_dir_pins_a: sdmmc1-dir-0 {
>>>>> +                             pins1 {
>>>>> +                                     pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
>>>>> +                                              <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
>>>>> +                                              <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
>>>>> +                                     slew-rate = <3>;
>>>>> +                                     drive-push-pull;
>>>>> +                                     bias-pull-up;
>>>>> +                             };
>>>>> +                             pins2{
>>>>> +                                     pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
>>>>> +                                     bias-pull-up;
>>>>> +                             };
>>>>> +                     };
>>>>> +
>>>>> +                     sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
>>>>> +                             pins {
>>>>> +                                     pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
>>>>> +                                              <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
>>>>> +                                              <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
>>>>> +                                              <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
>>>>> +                             };
>>>>> +                     };
>>>>> +
>>>>> +                     usart1_pins: usart1-0 {
>>>>> +                             pins1 {
>>>>> +                                     pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
>>>>> +                                     bias-disable;
>>>>> +                                     drive-push-pull;
>>>>> +                                     slew-rate = <0>;
>>>>> +                             };
>>>>> +                             pins2 {
>>>>> +                                     pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
>>>>> +                                     bias-disable;
>>>>> +                             };
>>>>> +                     };
>>>>> +
>>>>> +                     usart2_pins: usart2-0 {
>>>>> +                             pins1 {
>>>>> +                                     pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
>>>>> +                                     bias-disable;
>>>>> +                                     drive-push-pull;
>>>>> +                                     slew-rate = <0>;
>>>>> +                             };
>>>>> +                             pins2 {
>>>>> +                                     pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
>>>>> +                                     bias-disable;
>>>>> +                             };
>>>>> +                     };
>>>>> +
>>>>> +                     usart3_pins: usart3-0 {
>>>>> +                             pins1 {
>>>>> +                                     pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
>>>>> +                                     bias-disable;
>>>>> +                                     drive-push-pull;
>>>>> +                                     slew-rate = <0>;
>>>>> +                             };
>>>>> +                             pins2 {
>>>>> +                                     pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
>>>>> +                                     bias-disable;
>>>>> +                             };
>>>>> +                     };
>>>>> +
>>>>> +                     uart4_pins: uart4-0 {
>>>>> +                             pins1 {
>>>>> +                                     pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */
>>>>> +                                     bias-disable;
>>>>> +                                     drive-push-pull;
>>>>> +                                     slew-rate = <0>;
>>>>> +                             };
>>>>> +                             pins2 {
>>>>> +                                     pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */
>>>>> +                                     bias-disable;
>>>>> +                             };
>>>>> +                     };
>>>>> +
>>>>> +                     usbotg_hs_pins_a: usbotg-hs-0 {
>>>>> +                             pins {
>>>>> +                                     pinmux = <STM32_PINMUX('H', 4, AF10)>,  /* ULPI_NXT */
>>>>> +                                                      <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
>>>>> +                                                      <STM32_PINMUX('C', 0, AF10)>,  /* ULPI_STP> */
>>>>> +                                                      <STM32_PINMUX('A', 5, AF10)>,  /* ULPI_CK> */
>>>>> +                                                      <STM32_PINMUX('A', 3, AF10)>,  /* ULPI_D0> */
>>>>> +                                                      <STM32_PINMUX('B', 0, AF10)>,  /* ULPI_D1> */
>>>>> +                                                      <STM32_PINMUX('B', 1, AF10)>,  /* ULPI_D2> */
>>>>> +                                                      <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
>>>>> +                                                      <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
>>>>> +                                                      <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
>>>>> +                                                      <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
>>>>> +                                                      <STM32_PINMUX('B', 5, AF10)>;  /* ULPI_D7> */
>>>>> +                                     bias-disable;
>>>>> +                                     drive-push-pull;
>>>>> +                                     slew-rate = <2>;
>>>>> +                             };
>>>>> +                     };
>>>>> +
>>>>> +                     spi1_pins: spi1-0 {
>>>>> +                             pins1 {
>>>>> +                                     pinmux = <STM32_PINMUX('A', 5, AF5)>,
>>>>> +                                             /* SPI1_CLK */
>>>>> +                                              <STM32_PINMUX('B', 5, AF5)>;
>>>>> +                                             /* SPI1_MOSI */
>>>>> +                                     bias-disable;
>>>>> +                                     drive-push-pull;
>>>>> +                                     slew-rate = <2>;
>>>>> +                             };
>>>>> +                             pins2 {
>>>>> +                                     pinmux = <STM32_PINMUX('G', 9, AF5)>;
>>>>> +                                             /* SPI1_MISO */
>>>>> +                                     bias-disable;
>>>>> +                             };
>>>>> +                     };
>>>>> +             };
>>>>> +     };
>>>>> +};
>>>>> diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
>>>>> index fa5dcb6a5fdd..6b1e115307b9 100644
>>>>> --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
>>>>> @@ -1,306 +1,11 @@
>>>>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>>>>>     /*
>>>>> - * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
>>>>> - *
>>>>> - * This file is dual-licensed: you can use it either under the terms
>>>>> - * of the GPL or the X11 license, at your option. Note that this dual
>>>>> - * licensing only applies to this file, and not this project as a
>>>>> - * whole.
>>>>> - *
>>>>> - *  a) This file is free software; you can redistribute it and/or
>>>>> - *     modify it under the terms of the GNU General Public License as
>>>>> - *     published by the Free Software Foundation; either version 2 of the
>>>>> - *     License, or (at your option) any later version.
>>>>> - *
>>>>> - *     This file is distributed in the hope that it will be useful,
>>>>> - *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>>> - *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>>>> - *     GNU General Public License for more details.
>>>>> - *
>>>>> - * Or, alternatively,
>>>>> - *
>>>>> - *  b) Permission is hereby granted, free of charge, to any person
>>>>> - *     obtaining a copy of this software and associated documentation
>>>>> - *     files (the "Software"), to deal in the Software without
>>>>> - *     restriction, including without limitation the rights to use,
>>>>> - *     copy, modify, merge, publish, distribute, sublicense, and/or
>>>>> - *     sell copies of the Software, and to permit persons to whom the
>>>>> - *     Software is furnished to do so, subject to the following
>>>>> - *     conditions:
>>>>> - *
>>>>> - *     The above copyright notice and this permission notice shall be
>>>>> - *     included in all copies or substantial portions of the Software.
>>>>> - *
>>>>> - *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>>>> - *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>>>> - *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>>>> - *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>>>> - *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>>>> - *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>>> - *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>>>> - *     OTHER DEALINGS IN THE SOFTWARE.
>>>>> + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
>>>>> + * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
>>>>>      */
>>>>>
>>>>> -#include <dt-bindings/pinctrl/stm32-pinfunc.h>
>>>>> +#include "stm32h7-pinctrl.dtsi"
>>>>>
>>>>> -/ {
>>>>> -     soc {
>>>>> -             pin-controller {
>>>>> -                     #address-cells = <1>;
>>>>> -                     #size-cells = <1>;
>>>>> -                     compatible = "st,stm32h743-pinctrl";
>>>>> -                     ranges = <0 0x58020000 0x3000>;
>>>>> -                     interrupt-parent = <&exti>;
>>>>> -                     st,syscfg = <&syscfg 0x8>;
>>>>> -                     pins-are-numbered;
>>>>> -
>>>>> -                     gpioa: gpio@58020000 {
>>>>> -                             gpio-controller;
>>>>> -                             #gpio-cells = <2>;
>>>>> -                             reg = <0x0 0x400>;
>>>>> -                             clocks = <&rcc GPIOA_CK>;
>>>>> -                             st,bank-name = "GPIOA";
>>>>> -                             interrupt-controller;
>>>>> -                             #interrupt-cells = <2>;
>>>>> -                     };
>>>>> -
>>>>> -                     gpiob: gpio@58020400 {
>>>>> -                             gpio-controller;
>>>>> -                             #gpio-cells = <2>;
>>>>> -                             reg = <0x400 0x400>;
>>>>> -                             clocks = <&rcc GPIOB_CK>;
>>>>> -                             st,bank-name = "GPIOB";
>>>>> -                             interrupt-controller;
>>>>> -                             #interrupt-cells = <2>;
>>>>> -                     };
>>>>> -
>>>>> -                     gpioc: gpio@58020800 {
>>>>> -                             gpio-controller;
>>>>> -                             #gpio-cells = <2>;
>>>>> -                             reg = <0x800 0x400>;
>>>>> -                             clocks = <&rcc GPIOC_CK>;
>>>>> -                             st,bank-name = "GPIOC";
>>>>> -                             interrupt-controller;
>>>>> -                             #interrupt-cells = <2>;
>>>>> -                     };
>>>>> -
>>>>> -                     gpiod: gpio@58020c00 {
>>>>> -                             gpio-controller;
>>>>> -                             #gpio-cells = <2>;
>>>>> -                             reg = <0xc00 0x400>;
>>>>> -                             clocks = <&rcc GPIOD_CK>;
>>>>> -                             st,bank-name = "GPIOD";
>>>>> -                             interrupt-controller;
>>>>> -                             #interrupt-cells = <2>;
>>>>> -                     };
>>>>> -
>>>>> -                     gpioe: gpio@58021000 {
>>>>> -                             gpio-controller;
>>>>> -                             #gpio-cells = <2>;
>>>>> -                             reg = <0x1000 0x400>;
>>>>> -                             clocks = <&rcc GPIOE_CK>;
>>>>> -                             st,bank-name = "GPIOE";
>>>>> -                             interrupt-controller;
>>>>> -                             #interrupt-cells = <2>;
>>>>> -                     };
>>>>> -
>>>>> -                     gpiof: gpio@58021400 {
>>>>> -                             gpio-controller;
>>>>> -                             #gpio-cells = <2>;
>>>>> -                             reg = <0x1400 0x400>;
>>>>> -                             clocks = <&rcc GPIOF_CK>;
>>>>> -                             st,bank-name = "GPIOF";
>>>>> -                             interrupt-controller;
>>>>> -                             #interrupt-cells = <2>;
>>>>> -                     };
>>>>> -
>>>>> -                     gpiog: gpio@58021800 {
>>>>> -                             gpio-controller;
>>>>> -                             #gpio-cells = <2>;
>>>>> -                             reg = <0x1800 0x400>;
>>>>> -                             clocks = <&rcc GPIOG_CK>;
>>>>> -                             st,bank-name = "GPIOG";
>>>>> -                             interrupt-controller;
>>>>> -                             #interrupt-cells = <2>;
>>>>> -                     };
>>>>> -
>>>>> -                     gpioh: gpio@58021c00 {
>>>>> -                             gpio-controller;
>>>>> -                             #gpio-cells = <2>;
>>>>> -                             reg = <0x1c00 0x400>;
>>>>> -                             clocks = <&rcc GPIOH_CK>;
>>>>> -                             st,bank-name = "GPIOH";
>>>>> -                             interrupt-controller;
>>>>> -                             #interrupt-cells = <2>;
>>>>> -                     };
>>>>> -
>>>>> -                     gpioi: gpio@58022000 {
>>>>> -                             gpio-controller;
>>>>> -                             #gpio-cells = <2>;
>>>>> -                             reg = <0x2000 0x400>;
>>>>> -                             clocks = <&rcc GPIOI_CK>;
>>>>> -                             st,bank-name = "GPIOI";
>>>>> -                             interrupt-controller;
>>>>> -                             #interrupt-cells = <2>;
>>>>> -                     };
>>>>> -
>>>>> -                     gpioj: gpio@58022400 {
>>>>> -                             gpio-controller;
>>>>> -                             #gpio-cells = <2>;
>>>>> -                             reg = <0x2400 0x400>;
>>>>> -                             clocks = <&rcc GPIOJ_CK>;
>>>>> -                             st,bank-name = "GPIOJ";
>>>>> -                             interrupt-controller;
>>>>> -                             #interrupt-cells = <2>;
>>>>> -                     };
>>>>> -
>>>>> -                     gpiok: gpio@58022800 {
>>>>> -                             gpio-controller;
>>>>> -                             #gpio-cells = <2>;
>>>>> -                             reg = <0x2800 0x400>;
>>>>> -                             clocks = <&rcc GPIOK_CK>;
>>>>> -                             st,bank-name = "GPIOK";
>>>>> -                             interrupt-controller;
>>>>> -                             #interrupt-cells = <2>;
>>>>> -                     };
>>>>> -
>>>>> -                     i2c1_pins_a: i2c1-0 {
>>>>> -                             pins {
>>>>> -                                     pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
>>>>> -                                              <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
>>>>> -                                     bias-disable;
>>>>> -                                     drive-open-drain;
>>>>> -                                     slew-rate = <0>;
>>>>> -                             };
>>>>> -                     };
>>>>> -
>>>>> -                     ethernet_rmii: rmii-0 {
>>>>> -                             pins {
>>>>> -                                     pinmux = <STM32_PINMUX('G', 11, AF11)>,
>>>>> -                                              <STM32_PINMUX('G', 13, AF11)>,
>>>>> -                                              <STM32_PINMUX('G', 12, AF11)>,
>>>>> -                                              <STM32_PINMUX('C', 4, AF11)>,
>>>>> -                                              <STM32_PINMUX('C', 5, AF11)>,
>>>>> -                                              <STM32_PINMUX('A', 7, AF11)>,
>>>>> -                                              <STM32_PINMUX('C', 1, AF11)>,
>>>>> -                                              <STM32_PINMUX('A', 2, AF11)>,
>>>>> -                                              <STM32_PINMUX('A', 1, AF11)>;
>>>>> -                                     slew-rate = <2>;
>>>>> -                             };
>>>>> -                     };
>>>>> -
>>>>> -                     sdmmc1_b4_pins_a: sdmmc1-b4-0 {
>>>>> -                             pins {
>>>>> -                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
>>>>> -                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
>>>>> -                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
>>>>> -                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
>>>>> -                                              <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
>>>>> -                                              <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
>>>>> -                                     slew-rate = <3>;
>>>>> -                                     drive-push-pull;
>>>>> -                                     bias-disable;
>>>>> -                             };
>>>>> -                     };
>>>>> -
>>>>> -                     sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
>>>>> -                             pins1 {
>>>>> -                                     pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
>>>>> -                                              <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
>>>>> -                                              <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
>>>>> -                                              <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
>>>>> -                                              <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
>>>>> -                                     slew-rate = <3>;
>>>>> -                                     drive-push-pull;
>>>>> -                                     bias-disable;
>>>>> -                             };
>>>>> -                             pins2{
>>>>> -                                     pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
>>>>> -                                     slew-rate = <3>;
>>>>> -                                     drive-open-drain;
>>>>> -                                     bias-disable;
>>>>> -                             };
>>>>> -                     };
>>>>> -
>>>>> -                     sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
>>>>> -                             pins {
>>>>> -                                     pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
>>>>> -                                              <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
>>>>> -                                              <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
>>>>> -                                              <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
>>>>> -                                              <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
>>>>> -                                              <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
>>>>> -                             };
>>>>> -                     };
>>>>> -
>>>>> -                     sdmmc1_dir_pins_a: sdmmc1-dir-0 {
>>>>> -                             pins1 {
>>>>> -                                     pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
>>>>> -                                              <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
>>>>> -                                              <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
>>>>> -                                     slew-rate = <3>;
>>>>> -                                     drive-push-pull;
>>>>> -                                     bias-pull-up;
>>>>> -                             };
>>>>> -                             pins2{
>>>>> -                                     pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
>>>>> -                                     bias-pull-up;
>>>>> -                             };
>>>>> -                     };
>>>>> -
>>>>> -                     sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
>>>>> -                             pins {
>>>>> -                                     pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
>>>>> -                                              <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
>>>>> -                                              <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
>>>>> -                                              <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
>>>>> -                             };
>>>>> -                     };
>>>>> -
>>>>> -                     usart1_pins: usart1-0 {
>>>>> -                             pins1 {
>>>>> -                                     pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
>>>>> -                                     bias-disable;
>>>>> -                                     drive-push-pull;
>>>>> -                                     slew-rate = <0>;
>>>>> -                             };
>>>>> -                             pins2 {
>>>>> -                                     pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
>>>>> -                                     bias-disable;
>>>>> -                             };
>>>>> -                     };
>>>>> -
>>>>> -                     usart2_pins: usart2-0 {
>>>>> -                             pins1 {
>>>>> -                                     pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
>>>>> -                                     bias-disable;
>>>>> -                                     drive-push-pull;
>>>>> -                                     slew-rate = <0>;
>>>>> -                             };
>>>>> -                             pins2 {
>>>>> -                                     pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
>>>>> -                                     bias-disable;
>>>>> -                             };
>>>>> -                     };
>>>>> -
>>>>> -                     usbotg_hs_pins_a: usbotg-hs-0 {
>>>>> -                             pins {
>>>>> -                                     pinmux = <STM32_PINMUX('H', 4, AF10)>,  /* ULPI_NXT */
>>>>> -                                                      <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
>>>>> -                                                      <STM32_PINMUX('C', 0, AF10)>,  /* ULPI_STP> */
>>>>> -                                                      <STM32_PINMUX('A', 5, AF10)>,  /* ULPI_CK> */
>>>>> -                                                      <STM32_PINMUX('A', 3, AF10)>,  /* ULPI_D0> */
>>>>> -                                                      <STM32_PINMUX('B', 0, AF10)>,  /* ULPI_D1> */
>>>>> -                                                      <STM32_PINMUX('B', 1, AF10)>,  /* ULPI_D2> */
>>>>> -                                                      <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
>>>>> -                                                      <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
>>>>> -                                                      <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
>>>>> -                                                      <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
>>>>> -                                                      <STM32_PINMUX('B', 5, AF10)>;  /* ULPI_D7> */
>>>>> -                                     bias-disable;
>>>>> -                                     drive-push-pull;
>>>>> -                                     slew-rate = <2>;
>>>>> -                             };
>>>>> -                     };
>>>>> -             };
>>>>> -     };
>>>>> +&pinctrl{
>>>>> +     compatible = "st,stm32h743-pinctrl";
>>>>>     };
>>>>>