From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BA79C43470 for ; Thu, 1 Apr 2021 06:40:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0780F610EA for ; Thu, 1 Apr 2021 06:40:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233508AbhDAGkc (ORCPT ); Thu, 1 Apr 2021 02:40:32 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:42190 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233479AbhDAGkF (ORCPT ); Thu, 1 Apr 2021 02:40:05 -0400 X-UUID: b69d389aeb684c2d8d98f974038db1bb-20210401 X-UUID: b69d389aeb684c2d8d98f974038db1bb-20210401 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 681871245; Thu, 01 Apr 2021 14:40:02 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 1 Apr 2021 14:40:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 1 Apr 2021 14:40:00 +0800 From: Nina Wu To: Rob Herring , Matthias Brugger CC: Nina Wu , Zhen Lei , Neal Liu , , , , , , Subject: [PATCH v2 4/6] soc: mediatek: devapc: rename variable for new IC support Date: Thu, 1 Apr 2021 14:38:05 +0800 Message-ID: <1617259087-5502-4-git-send-email-nina-cm.wu@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1617259087-5502-1-git-send-email-nina-cm.wu@mediatek.com> References: <1617259087-5502-1-git-send-email-nina-cm.wu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 364F31474881FC23DBD493D6B787402F121E93BF61208FF85A79730EBA4AABE52000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Nina Wu For new ICs, there are multiple devapc HWs for different subsys. For example, there is devapc respectively for infra, peri, peri2, etc. So we rename the variable 'infra_base' to 'base' for code readability. Signed-off-by: Nina Wu --- drivers/soc/mediatek/mtk-devapc.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c index 68c3e35..bcf6e3c 100644 --- a/drivers/soc/mediatek/mtk-devapc.c +++ b/drivers/soc/mediatek/mtk-devapc.c @@ -45,7 +45,7 @@ struct mtk_devapc_data { struct mtk_devapc_context { struct device *dev; - void __iomem *infra_base; + void __iomem *base; u32 vio_idx_num; struct clk *infra_clk; const struct mtk_devapc_data *data; @@ -56,7 +56,7 @@ static void clear_vio_status(struct mtk_devapc_context *ctx) void __iomem *reg; int i; - reg = ctx->infra_base + ctx->data->vio_sta_offset; + reg = ctx->base + ctx->data->vio_sta_offset; for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++) writel(GENMASK(31, 0), reg + 4 * i); @@ -71,7 +71,7 @@ static void mask_module_irq(struct mtk_devapc_context *ctx, bool mask) u32 val; int i; - reg = ctx->infra_base + ctx->data->vio_mask_offset; + reg = ctx->base + ctx->data->vio_mask_offset; if (mask) val = GENMASK(31, 0); @@ -113,11 +113,11 @@ static int devapc_sync_vio_dbg(struct mtk_devapc_context *ctx) int ret; u32 val; - pd_vio_shift_sta_reg = ctx->infra_base + + pd_vio_shift_sta_reg = ctx->base + ctx->data->vio_shift_sta_offset; - pd_vio_shift_sel_reg = ctx->infra_base + + pd_vio_shift_sel_reg = ctx->base + ctx->data->vio_shift_sel_offset; - pd_vio_shift_con_reg = ctx->infra_base + + pd_vio_shift_con_reg = ctx->base + ctx->data->vio_shift_con_offset; /* Find the minimum shift group which has violation */ @@ -159,8 +159,8 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx) void __iomem *vio_dbg0_reg; void __iomem *vio_dbg1_reg; - vio_dbg0_reg = ctx->infra_base + ctx->data->vio_dbg0_offset; - vio_dbg1_reg = ctx->infra_base + ctx->data->vio_dbg1_offset; + vio_dbg0_reg = ctx->base + ctx->data->vio_dbg0_offset; + vio_dbg1_reg = ctx->base + ctx->data->vio_dbg1_offset; vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg); vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg); @@ -198,7 +198,7 @@ static irqreturn_t devapc_violation_irq(int irq_number, void *data) */ static void start_devapc(struct mtk_devapc_context *ctx) { - writel(BIT(31), ctx->infra_base + ctx->data->apc_con_offset); + writel(BIT(31), ctx->base + ctx->data->apc_con_offset); mask_module_irq(ctx, false); } @@ -210,7 +210,7 @@ static void stop_devapc(struct mtk_devapc_context *ctx) { mask_module_irq(ctx, true); - writel(BIT(2), ctx->infra_base + ctx->data->apc_con_offset); + writel(BIT(2), ctx->base + ctx->data->apc_con_offset); } static const struct mtk_devapc_data devapc_mt6779 = { @@ -249,8 +249,8 @@ static int mtk_devapc_probe(struct platform_device *pdev) ctx->data = of_device_get_match_data(&pdev->dev); ctx->dev = &pdev->dev; - ctx->infra_base = of_iomap(node, 0); - if (!ctx->infra_base) + ctx->base = of_iomap(node, 0); + if (!ctx->base) return -EINVAL; if (of_property_read_u32(node, "vio_idx_num", &ctx->vio_idx_num)) -- 2.6.4