From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
To: <vkoul@kernel.org>, <robh+dt@kernel.org>, <michal.simek@xilinx.com>
Cc: <dmaengine@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <git@xilinx.com>,
Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Subject: [RFC v2 PATCH 0/7] Xilinx DMA enhancements and optimization
Date: Fri, 9 Apr 2021 23:25:58 +0530 [thread overview]
Message-ID: <1617990965-35337-1-git-send-email-radhey.shyam.pandey@xilinx.com> (raw)
Some background about the patch series: Xilinx Axi Ethernet device driver
(xilinx_axienet_main.c) currently has axi-dma code inside it. The goal
is to refactor axiethernet driver and use existing AXI DMA driver using
DMAEngine API.
This patchset does feature addition and optimization to support
axidma integration with axiethernet network driver. Once axidma
version is accepted mcdma specific changes will be added in
followup version.
This series is based on dmaengine tree commit: #a38fd8748464
Changes for v2:
- Use metadata API[1] for passing metadata from dma to netdev client.
- Read irq-delay from DT.
- Remove desc_callback_valid check.
- Addressed RFC v1 comments[2].
- Minor code refactoring.
Comments, suggestions are very welcome!
[1] https://www.spinics.net/lists/dmaengine/msg16583.html
[2] https://www.spinics.net/lists/dmaengine/msg15208.html
Radhey Shyam Pandey (7):
dt-bindings: dmaengine: xilinx_dma: Add xlnx,axistream-connected
property
dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property
dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client
dmaengine: xilinx_dma: Increase AXI DMA transaction segment count
dmaengine: xilinx_dma: Freeup active list based on descriptor
completion bit
dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical
usecase
dmaengine: xilinx_dma: Program interrupt delay timeout
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++
drivers/dma/xilinx/xilinx_dma.c | 68 ++++++++++++++++++----
2 files changed, 61 insertions(+), 11 deletions(-)
--
2.7.4
next reply other threads:[~2021-04-09 17:56 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-09 17:55 Radhey Shyam Pandey [this message]
2021-04-09 17:55 ` [RFC v2 PATCH 1/7] dt-bindings: dmaengine: xilinx_dma: Add xlnx,axistream-connected property Radhey Shyam Pandey
2021-04-12 18:25 ` Rob Herring
2021-04-09 17:56 ` [RFC v2 PATCH 2/7] dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property Radhey Shyam Pandey
2021-04-12 18:25 ` Rob Herring
2021-04-09 17:56 ` [RFC v2 PATCH 3/7] dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client Radhey Shyam Pandey
2021-04-09 17:56 ` [RFC v2 PATCH 4/7] dmaengine: xilinx_dma: Increase AXI DMA transaction segment count Radhey Shyam Pandey
2021-04-09 17:56 ` [RFC v2 PATCH 5/7] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit Radhey Shyam Pandey
2021-04-15 7:08 ` Lars-Peter Clausen
2021-06-11 16:16 ` Radhey Shyam Pandey
2021-04-15 7:26 ` Lars-Peter Clausen
2021-06-11 18:58 ` Radhey Shyam Pandey
2021-04-09 17:56 ` [RFC v2 PATCH 6/7] dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical usecase Radhey Shyam Pandey
2021-04-15 7:10 ` Lars-Peter Clausen
2021-06-11 18:30 ` Radhey Shyam Pandey
2021-04-09 17:56 ` [RFC v2 PATCH 7/7] dmaengine: xilinx_dma: Program interrupt delay timeout Radhey Shyam Pandey
2021-04-15 7:33 ` Lars-Peter Clausen
2021-06-11 19:33 ` Radhey Shyam Pandey
2021-04-15 7:06 ` [RFC v2 PATCH 0/7] Xilinx DMA enhancements and optimization Lars-Peter Clausen
2021-06-11 16:13 ` Radhey Shyam Pandey
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