From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2671C433B4 for ; Tue, 20 Apr 2021 10:46:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 74BC0613D2 for ; Tue, 20 Apr 2021 10:46:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231700AbhDTKrT (ORCPT ); Tue, 20 Apr 2021 06:47:19 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:51660 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231574AbhDTKrO (ORCPT ); Tue, 20 Apr 2021 06:47:14 -0400 Date: Tue, 20 Apr 2021 10:46:41 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1618915601; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XkrD1L5nueXeJZrckvtVOjYvPICdIW/we7aLIC4kJF4=; b=X2gwRjaJG2zWmk5v62dvfpKVP7jNmOKWSh5GHm5g3Xp+fEPWRVp9QBM1LDO8+XRPAf3zQw sqnIXsMBz96CexJz+PPnviPeJQOq8RpyvMAtV0TD/dsUKDAyRLZIEtl/H8kKSSLGcwyWNn 76AVykmEqk+XW6zkMtUs2+Cdq/486wINa6BXam5oCATViVRuA9o4B7LLQVUCelWxXnX/M1 AbFmwKq7a1x2u9qrVMvcs2K4wHgVfXoMmuVHHgqKGJEtLlU96JE0i1eiExhiy2e8TZp/M2 z3KZRC8obxieDWDkAR/FEWYK7B5mE/eIlhE9RfHWFZLkDaIyPcaGF7IOepOZ8Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1618915601; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XkrD1L5nueXeJZrckvtVOjYvPICdIW/we7aLIC4kJF4=; b=vjDQVuurIO4CpWwD/SjteRxLCI269evbvc6DgUy1mdBw6cmFFoKITQQR+QhzhoEM9HITZA PBtJsSzbNKwzSRCA== From: "tip-bot2 for Kan Liang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/msr: Add Alder Lake CPU support Cc: Kan Liang , "Peter Zijlstra (Intel)" , Andi Kleen , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <1618237865-33448-24-git-send-email-kan.liang@linux.intel.com> References: <1618237865-33448-24-git-send-email-kan.liang@linux.intel.com> MIME-Version: 1.0 Message-ID: <161891560119.29796.11364634587535953691.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the perf/core branch of tip: Commit-ID: 19d3a81fd92dc9b73950564955164ecfd0dfbea1 Gitweb: https://git.kernel.org/tip/19d3a81fd92dc9b73950564955164ecfd0dfbea1 Author: Kan Liang AuthorDate: Mon, 12 Apr 2021 07:31:03 -07:00 Committer: Peter Zijlstra CommitterDate: Mon, 19 Apr 2021 20:03:29 +02:00 perf/x86/msr: Add Alder Lake CPU support PPERF and SMI_COUNT MSRs are also supported on Alder Lake. The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source. The patch has been tested on real hardware. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Andi Kleen Link: https://lkml.kernel.org/r/1618237865-33448-24-git-send-email-kan.liang@linux.intel.com --- arch/x86/events/msr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 680404c..c853b28 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -100,6 +100,8 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_TIGERLAKE_L: case INTEL_FAM6_TIGERLAKE: case INTEL_FAM6_ROCKETLAKE: + case INTEL_FAM6_ALDERLAKE: + case INTEL_FAM6_ALDERLAKE_L: if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) return true; break;