[PATCH 2/2] drm/amd/amdgpu: Add dwc quirk for Stoney/CZ platforms

[Vijendar Mukunda <Vijendar.Mukunda@amd.com>]

Add a quirk DW_I2S_QUIRK_STOP_ON_SHUTDOWN for Stoney/CZ
platforms.

For CZ/StoneyRidge platforms, ACP DMA between ACP SRAM and
I2S FIFO should be stopped before stopping I2S Controller DMA.

When DMA is progressing and stop request received, while DMA
transfer ongoing between ACP SRAM and I2S FIFO, Stopping I2S DMA
prior to ACP DMA stop resulting ACP DMA channel stop failure.

ACP DMA driver can't fix this issue due to design constraint.
By setting this quirk, I2S DMA gets stopped after ACP DMA stop
which will fix the ACP DMA stop failure.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 38 +++++++++++----------------------
 1 file changed, 13 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index b8655ff..6866b73 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -245,42 +245,30 @@ static int acp_hw_init(void *handle)
 		goto failure;
 	}
 
-	switch (adev->asic_type) {
-	case CHIP_STONEY:
-		i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
-			DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
-		break;
-	default:
-		i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
-	}
+	i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
+			      DW_I2S_QUIRK_STOP_ON_SHUTDOWN;
+	if (adev->asic_type == CHIP_STONEY)
+		i2s_pdata[0].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
+
 	i2s_pdata[0].cap = DWC_I2S_PLAY;
 	i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
 	i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
 	i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
-	switch (adev->asic_type) {
-	case CHIP_STONEY:
-		i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
-			DW_I2S_QUIRK_COMP_PARAM1 |
-			DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
-		break;
-	default:
-		i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
-			DW_I2S_QUIRK_COMP_PARAM1;
-	}
+	i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
+			      DW_I2S_QUIRK_COMP_PARAM1 |
+			      DW_I2S_QUIRK_STOP_ON_SHUTDOWN;
+	if (adev->asic_type == CHIP_STONEY)
+		i2s_pdata[1].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
 
 	i2s_pdata[1].cap = DWC_I2S_RECORD;
 	i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
 	i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
 	i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
 
-	i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
-	switch (adev->asic_type) {
-	case CHIP_STONEY:
+	i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
+			      DW_I2S_QUIRK_STOP_ON_SHUTDOWN;
+	if (adev->asic_type == CHIP_STONEY)
 		i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
-		break;
-	default:
-		break;
-	}
 
 	i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
 	i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
-- 
2.7.4