From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 098A7C47080 for ; Tue, 1 Jun 2021 13:32:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DFB9E613B1 for ; Tue, 1 Jun 2021 13:32:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234144AbhFANeZ (ORCPT ); Tue, 1 Jun 2021 09:34:25 -0400 Received: from mail-oo1-f46.google.com ([209.85.161.46]:40804 "EHLO mail-oo1-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234072AbhFANeF (ORCPT ); Tue, 1 Jun 2021 09:34:05 -0400 Received: by mail-oo1-f46.google.com with SMTP id w20-20020a4a35540000b02902458551c0d6so1680452oog.7; Tue, 01 Jun 2021 06:32:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:in-reply-to:references:subject:date :message-id; bh=cbbANktLK+nxqt4uUwCIqegFj6C7KopoJQcn0d/pISM=; b=ApsoDh9VYkKMiGaqrPjWkHbxo9xMTg4lMmq6s7GJjzCUAqqAt1YvWzjjXrMrS6F35X Raw0/oNmx2zGHMyOd4IDxlKM2CHPDIIsHqtCAKBZDIzWrvJtRQ5qIGDymA5DrtlqJNWx a4WqJ5SKYk+ovlf2UN4rl93S8JvFEUWf8bFYA6yf+yXt6xdRSljtROghrororpC4hs7G jW/O/FhUc1vF2gBLYi5KtpyYO0dtL7hcoE2QnCE+AbgrRnePN5NznXrICI464N6vG+9K yPDbNULwAq8X82bMgiJmWaUNipAMGH7SrQ8u/tiKpSccbBGeXvHP0d3TgsHLBjpdl1cl fzdw== X-Gm-Message-State: AOAM531t6eFcUKLA+C1rNm7PiumPuXeZ3a4gyGfryM8GAl2k1xR+lbKU e8MztF/oHNEaBYIyN26WoA== X-Google-Smtp-Source: ABdhPJzeNcFyGQm1lJ+4LJMre1TykO8SPIZ4q+FLDdGzVeNgU89lwPVka2DuK9V5/kTBHs/BfedkyQ== X-Received: by 2002:a4a:3f53:: with SMTP id x19mr20741442ooe.88.1622554342745; Tue, 01 Jun 2021 06:32:22 -0700 (PDT) Received: from robh.at.kernel.org (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id s4sm3809013otr.80.2021.06.01.06.32.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jun 2021 06:32:21 -0700 (PDT) Received: (nullmailer pid 242357 invoked by uid 1000); Tue, 01 Jun 2021 13:32:10 -0000 From: Rob Herring To: Sean Anderson Cc: linux-kernel@vger.kernel.org, Alvaro Gamez , devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, michal.simek@xilinx.com, linux-arm-kernel@lists.infradead.org In-Reply-To: <20210528214522.617435-1-sean.anderson@seco.com> References: <20210528214522.617435-1-sean.anderson@seco.com> Subject: Re: [PATCH v4 1/3] dt-bindings: pwm: Add Xilinx AXI Timer Date: Tue, 01 Jun 2021 08:32:10 -0500 Message-Id: <1622554330.014931.242356.nullmailer@robh.at.kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 28 May 2021 17:45:20 -0400, Sean Anderson wrote: > This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is > a "soft" block, so it has many parameters which would not be > configurable in most hardware. This binding is usually automatically > generated by Xilinx's tools, so the names and values of some properties > must be kept as they are. Replacement properties have been provided for > new device trees. > > Because we need to init timer devices so early in boot, the easiest way > to configure things is to use a device tree property. For the moment > this is 'xlnx,pwm', but this could be extended/renamed/etc. in the > future if these is a need for a generic property. > > Signed-off-by: Sean Anderson > --- > > Changes in v4: > - Remove references to generate polarity so this can get merged > - Predicate PWM driver on the presence of #pwm-cells > - Make some properties optional for clocksource drivers > > Changes in v3: > - Mark all boolean-as-int properties as deprecated > - Add xlnx,pwm and xlnx,gen?-active-low properties. > - Make newer replacement properties mutually-exclusive with what they > replace > - Add an example with non-deprecated properties only. > > Changes in v2: > - Use 32-bit addresses for example binding > > .../bindings/pwm/xlnx,axi-timer.yaml | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml:16:10: [warning] wrong indentation: expected 10 but found 9 (indentation) ./Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml:19:10: [warning] wrong indentation: expected 10 but found 9 (indentation) dtschema/dtc warnings/errors: See https://patchwork.ozlabs.org/patch/1485318 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.