From: guoren@kernel.org
To: guoren@kernel.org, anup.patel@wdc.com, palmerdabbelt@google.com,
arnd@arndb.de, wens@csie.org, maxime@cerno.tech,
drew@beagleboard.org, liush@allwinnertech.com,
lazyparser@gmail.com, wefu@redhat.com
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arch@vger.kernel.org, linux-sunxi@lists.linux.dev,
Guo Ren <guoren@linux.alibaba.com>,
Christoph Hellwig <hch@lst.de>
Subject: [RFC PATCH v2 06/11] riscv: pgtable: Add DMA_COHERENT with custom PTE attributes
Date: Sun, 6 Jun 2021 09:04:04 +0000 [thread overview]
Message-ID: <1622970249-50770-10-git-send-email-guoren@kernel.org> (raw)
In-Reply-To: <1622970249-50770-1-git-send-email-guoren@kernel.org>
From: Guo Ren <guoren@linux.alibaba.com>
The dma-noncoherent SOCs need different virtual memory mappings
with different attributes:
- noncached + Strong Order (for IO/DMA descriptor)
- noncached + Weak Order (for writecombine usage, eg: frame
buffer)
All above base on PTE attributes by MMU hardware. That means
address attributes are determined by PTE entry, not PMA. RISC-V
soc vendors have defined their own custom PTE attributes for
dma-noncoherency.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Liu Shaohua <liush@allwinnertech.com>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Anup Patel <anup.patel@wdc.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Drew Fustini <drew@beagleboard.org>
Cc: Wei Fu <wefu@redhat.com>
Cc: Wei Wu <lazyparser@gmail.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime@cerno.tech>
---
arch/riscv/include/asm/pgtable-bits.h | 20 +++++++++++++++++++-
arch/riscv/include/asm/pgtable.h | 11 ++++-------
arch/riscv/include/asm/soc.h | 1 +
arch/riscv/include/asm/vendorid_list.h | 1 +
arch/riscv/kernel/soc.c | 22 ++++++++++++++++++++++
arch/riscv/mm/init.c | 4 ++++
6 files changed, 51 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index bbaeb5d..080a9eb 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -24,6 +24,11 @@
#define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */
#define _PAGE_SOFT (1 << 8) /* Reserved for software */
+#define _PAGE_DMA_MASK __riscv_custom_pte.mask
+#define _PAGE_DMA_CACHE __riscv_custom_pte.cache
+#define _PAGE_DMA_IO __riscv_custom_pte.io
+#define _PAGE_DMA_WC __riscv_custom_pte.wc
+
#define _PAGE_SPECIAL _PAGE_SOFT
#define _PAGE_TABLE _PAGE_PRESENT
@@ -35,9 +40,22 @@
#define _PAGE_PFN_SHIFT 10
+#ifndef __ASSEMBLY__
+
+struct riscv_custom_pte {
+ unsigned long cache;
+ unsigned long mask;
+ unsigned long io;
+ unsigned long wc;
+};
+
+extern struct riscv_custom_pte __riscv_custom_pte;
+
/* Set of bits to preserve across pte_modify() */
#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
_PAGE_WRITE | _PAGE_EXEC | \
- _PAGE_USER | _PAGE_GLOBAL))
+ _PAGE_USER | _PAGE_GLOBAL | \
+ _PAGE_DMA_MASK))
+#endif
#endif /* _ASM_RISCV_PGTABLE_BITS_H */
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 13a79643..6ddeb49 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -114,7 +114,7 @@
#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
/* Page protection bits */
-#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER)
+#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER | _PAGE_DMA_CACHE)
#define PAGE_NONE __pgprot(_PAGE_PROT_NONE)
#define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ)
@@ -135,7 +135,8 @@
| _PAGE_PRESENT \
| _PAGE_ACCESSED \
| _PAGE_DIRTY \
- | _PAGE_GLOBAL)
+ | _PAGE_GLOBAL \
+ | _PAGE_DMA_CACHE)
#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
#define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE)
@@ -145,11 +146,7 @@
#define PAGE_TABLE __pgprot(_PAGE_TABLE)
-/*
- * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't
- * change the properties of memory regions.
- */
-#define _PAGE_IOREMAP _PAGE_KERNEL
+#define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_DMA_MASK) | _PAGE_DMA_IO)
extern pgd_t swapper_pg_dir[];
diff --git a/arch/riscv/include/asm/soc.h b/arch/riscv/include/asm/soc.h
index f494066..fc587d7 100644
--- a/arch/riscv/include/asm/soc.h
+++ b/arch/riscv/include/asm/soc.h
@@ -17,6 +17,7 @@
= { .compatible = compat, .data = fn }
void soc_early_init(void);
+void soc_setup_vm(void);
extern unsigned long __soc_early_init_table_start;
extern unsigned long __soc_early_init_table_end;
diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
index 9d93421..c2710f3 100644
--- a/arch/riscv/include/asm/vendorid_list.h
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -6,5 +6,6 @@
#define ASM_VENDOR_LIST_H
#define SIFIVE_VENDOR_ID 0x489
+#define THEAD_VENDOR_ID 0x401
#endif
diff --git a/arch/riscv/kernel/soc.c b/arch/riscv/kernel/soc.c
index a051617..05fa764 100644
--- a/arch/riscv/kernel/soc.c
+++ b/arch/riscv/kernel/soc.c
@@ -3,8 +3,10 @@
* Copyright (C) 2020 Western Digital Corporation or its affiliates.
*/
#include <linux/init.h>
+#include <linux/mm.h>
#include <linux/libfdt.h>
#include <linux/pgtable.h>
+#include <asm/image.h>
#include <asm/soc.h>
/*
@@ -26,3 +28,23 @@ void __init soc_early_init(void)
}
}
}
+
+static void __init thead_init(void)
+{
+ __riscv_custom_pte.cache = 0x7000000000000000;
+ __riscv_custom_pte.mask = 0xf800000000000000;
+ __riscv_custom_pte.io = BIT(63);
+ __riscv_custom_pte.wc = 0;
+}
+
+void __init soc_setup_vm(void)
+{
+ unsigned long vendor_id =
+ ((struct riscv_image_header *)(&_start))->res1;
+
+ switch (vendor_id) {
+ case THEAD_VENDOR_ID:
+ thead_init();
+ break;
+ }
+};
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 4b398c6..fb70c49 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -524,6 +524,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
pmd_t fix_bmap_spmd, fix_bmap_epmd;
#endif
+ soc_setup_vm();
setup_protection_map();
#ifdef CONFIG_XIP_KERNEL
@@ -911,3 +912,6 @@ int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node,
return vmemmap_populate_basepages(start, end, node, NULL);
}
#endif
+
+struct riscv_custom_pte __riscv_custom_pte __ro_after_init;
+EXPORT_SYMBOL(__riscv_custom_pte);
--
2.7.4
next prev parent reply other threads:[~2021-06-06 9:05 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-06 9:03 [RFC PATCH v2 00/11] riscv: Add DMA_COHERENT support for Allwinner D1 guoren
2021-06-06 9:03 ` [RFC PATCH v2 01/11] riscv: asid: Use global mappings for kernel pages guoren
2021-06-06 9:03 ` [PATCH V5 1/3] riscv: " guoren
2021-06-06 9:03 ` [PATCH V5 2/3] riscv: Add ASID-based tlbflushing methods guoren
2021-06-06 14:38 ` Christoph Hellwig
2021-06-06 9:03 ` [RFC PATCH v2 02/11] riscv: asid: " guoren
2021-06-06 9:04 ` [RFC PATCH v2 03/11] riscv: asid: Optimize tlbflush coding convention guoren
2021-06-06 9:04 ` [PATCH V5 3/3] riscv: tlbflush: Optimize " guoren
2021-06-06 9:04 ` [RFC PATCH v2 04/11] riscv: pgtable: Fixup _PAGE_CHG_MASK usage guoren
2021-06-06 9:04 ` [RFC PATCH v2 05/11] riscv: pgtable: Add custom protection_map init guoren
2021-06-06 9:04 ` guoren [this message]
2021-06-06 14:39 ` [RFC PATCH v2 06/11] riscv: pgtable: Add DMA_COHERENT with custom PTE attributes Christoph Hellwig
2021-06-06 15:08 ` Guo Ren
2021-06-06 17:22 ` Nick Kossifidis
2021-06-07 6:19 ` Christoph Hellwig
2021-06-06 9:04 ` [RFC PATCH v2 07/11] riscv: cmo: Add dma-noncoherency support guoren
2021-10-17 9:28 ` twd2
2021-10-20 8:11 ` Guo Ren
2021-06-06 9:04 ` [RFC PATCH v2 08/11] riscv: cmo: Add vendor custom icache sync guoren
2021-06-06 9:04 ` [RFC PATCH v2 09/11] riscv: soc: Initial DTS for Allwinner D1 NeZha board guoren
2021-06-06 16:26 ` Jernej Škrabec
2021-06-06 17:05 ` Guo Ren
2021-06-07 3:44 ` Guo Ren
2021-06-07 7:27 ` Maxime Ripard
2021-06-07 7:53 ` Guo Ren
2021-06-07 7:24 ` Maxime Ripard
2021-06-07 8:07 ` Guo Ren
2021-06-14 15:33 ` Maxime Ripard
2021-06-14 16:28 ` Guo Ren
2021-06-14 16:31 ` Jernej Škrabec
2021-06-06 9:04 ` [RFC PATCH v2 10/11] riscv: soc: Add Allwinner SoC kconfig option guoren
2021-06-07 7:19 ` Maxime Ripard
2021-06-07 7:27 ` Arnd Bergmann
2021-06-07 7:45 ` Guo Ren
2021-06-07 7:43 ` Guo Ren
2021-06-07 12:12 ` Maxime Ripard
2021-06-07 12:39 ` Guo Ren
2021-06-06 9:04 ` [RFC PATCH v2 11/11] riscv: soc: Allwinner D1 GMAC driver only for temp use guoren
2021-06-06 10:50 ` Andre Przywara
2021-06-06 15:32 ` Guo Ren
2021-06-06 15:39 ` Jernej Škrabec
2021-06-06 15:41 ` Guo Ren
2021-06-06 16:16 ` Arnd Bergmann
2021-06-06 16:32 ` Jernej Škrabec
2021-06-06 16:53 ` Guo Ren
2021-06-06 16:53 ` Guo Ren
2021-06-06 16:29 ` [RFC PATCH v2 00/11] riscv: Add DMA_COHERENT support for Allwinner D1 Jernej Škrabec
2021-06-06 16:54 ` Guo Ren
2021-06-06 17:14 ` Jernej Škrabec
2021-06-06 23:42 ` Guo Ren
2021-06-07 3:44 ` Anup Patel
2021-06-07 4:36 ` Guo Ren
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