* [PATCH 0/3] add i2c support for mt8195
@ 2021-06-08 3:16 Kewei Xu
2021-06-08 3:16 ` [PATCH 1/3] dt-bindings: i2c: update bindings for MT8195 SoC Kewei Xu
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Kewei Xu @ 2021-06-08 3:16 UTC (permalink / raw)
To: wsa
Cc: matthias.bgg, robh+dt, linux-i2c, devicetree, linux-arm-kernel,
linux-kernel, linux-mediatek, srv_heupstream, leilk.liu,
qii.wang, qiangming.xia, kewei.xu
This series are based on 5.13-rc1 and we provide three i2c patches
to support mt8195 SoC.
Kewei.Xu (3):
dt-bindings: i2c: update bindings for MT8195 SoC
i2c: mediatek: Dump i2c/dma register when a timeout occurs
i2c: mediatek: Reset the handshake signal between i2c and dma
.../devicetree/bindings/i2c/i2c-mt65xx.txt | 1 +
drivers/i2c/busses/i2c-mt65xx.c | 111 ++++++++++++++++++++-
2 files changed, 110 insertions(+), 2 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/3] dt-bindings: i2c: update bindings for MT8195 SoC 2021-06-08 3:16 [PATCH 0/3] add i2c support for mt8195 Kewei Xu @ 2021-06-08 3:16 ` Kewei Xu 2021-06-08 13:59 ` Matthias Brugger 2021-06-18 20:27 ` Rob Herring 2021-06-08 3:16 ` [PATCH 2/3] i2c: mediatek: Dump i2c/dma register when a timeout occurs Kewei Xu 2021-06-08 3:16 ` [PATCH 3/3] i2c: mediatek: Reset the handshake signal between i2c and dma Kewei Xu 2 siblings, 2 replies; 10+ messages in thread From: Kewei Xu @ 2021-06-08 3:16 UTC (permalink / raw) To: wsa Cc: matthias.bgg, robh+dt, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream, leilk.liu, qii.wang, qiangming.xia, kewei.xu From: "Kewei.Xu" <kewei.xu@mediatek.com> Add a DT binding documentation for the MT8195 soc. Signed-off-by: Kewei.Xu <kewei.xu@mediatek.com> --- Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt index 7f0194f..7c4915bc 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt @@ -15,6 +15,7 @@ Required properties: "mediatek,mt8173-i2c": for MediaTek MT8173 "mediatek,mt8183-i2c": for MediaTek MT8183 "mediatek,mt8192-i2c": for MediaTek MT8192 + "mediatek,mt8195-i2c", "mediatek,mt8192-i2c": for MediaTek MT8195 "mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516 - reg: physical base address of the controller and dma base, length of memory mapped region. -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] dt-bindings: i2c: update bindings for MT8195 SoC 2021-06-08 3:16 ` [PATCH 1/3] dt-bindings: i2c: update bindings for MT8195 SoC Kewei Xu @ 2021-06-08 13:59 ` Matthias Brugger 2021-06-18 20:27 ` Rob Herring 1 sibling, 0 replies; 10+ messages in thread From: Matthias Brugger @ 2021-06-08 13:59 UTC (permalink / raw) To: Kewei Xu, wsa Cc: robh+dt, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream, leilk.liu, qii.wang, qiangming.xia On 08/06/2021 05:16, Kewei Xu wrote: > From: "Kewei.Xu" <kewei.xu@mediatek.com> > > Add a DT binding documentation for the MT8195 soc. > > Signed-off-by: Kewei.Xu <kewei.xu@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt > index 7f0194f..7c4915bc 100644 > --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt > +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt > @@ -15,6 +15,7 @@ Required properties: > "mediatek,mt8173-i2c": for MediaTek MT8173 > "mediatek,mt8183-i2c": for MediaTek MT8183 > "mediatek,mt8192-i2c": for MediaTek MT8192 > + "mediatek,mt8195-i2c", "mediatek,mt8192-i2c": for MediaTek MT8195 > "mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516 > - reg: physical base address of the controller and dma base, length of memory > mapped region. > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] dt-bindings: i2c: update bindings for MT8195 SoC 2021-06-08 3:16 ` [PATCH 1/3] dt-bindings: i2c: update bindings for MT8195 SoC Kewei Xu 2021-06-08 13:59 ` Matthias Brugger @ 2021-06-18 20:27 ` Rob Herring 1 sibling, 0 replies; 10+ messages in thread From: Rob Herring @ 2021-06-18 20:27 UTC (permalink / raw) To: Kewei Xu Cc: qii.wang, qiangming.xia, matthias.bgg, wsa, devicetree, linux-kernel, srv_heupstream, linux-i2c, linux-arm-kernel, leilk.liu, linux-mediatek, robh+dt On Tue, 08 Jun 2021 11:16:38 +0800, Kewei Xu wrote: > From: "Kewei.Xu" <kewei.xu@mediatek.com> > > Add a DT binding documentation for the MT8195 soc. > > Signed-off-by: Kewei.Xu <kewei.xu@mediatek.com> > --- > Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/3] i2c: mediatek: Dump i2c/dma register when a timeout occurs 2021-06-08 3:16 [PATCH 0/3] add i2c support for mt8195 Kewei Xu 2021-06-08 3:16 ` [PATCH 1/3] dt-bindings: i2c: update bindings for MT8195 SoC Kewei Xu @ 2021-06-08 3:16 ` Kewei Xu 2021-06-08 14:01 ` Matthias Brugger 2021-06-08 3:16 ` [PATCH 3/3] i2c: mediatek: Reset the handshake signal between i2c and dma Kewei Xu 2 siblings, 1 reply; 10+ messages in thread From: Kewei Xu @ 2021-06-08 3:16 UTC (permalink / raw) To: wsa Cc: matthias.bgg, robh+dt, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream, leilk.liu, qii.wang, qiangming.xia, kewei.xu From: "Kewei.Xu" <kewei.xu@mediatek.com> When a timeout error occurs in i2c transter, it is usually related to the i2c/dma IP hardware configuration. Therefore, the purpose of this patch is to dump the key register values of i2c/dma when a timeout occurs in i2c for debugging. Signed-off-by: Kewei.Xu <kewei.xu@mediatek.com> --- drivers/i2c/busses/i2c-mt65xx.c | 97 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 95 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index 5ddfa4e..e65a41e 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -125,6 +125,7 @@ enum I2C_REGS_OFFSET { OFFSET_HS, OFFSET_SOFTRESET, OFFSET_DCM_EN, + OFFSET_MULTI_DMA, OFFSET_PATH_DIR, OFFSET_DEBUGSTAT, OFFSET_DEBUGCTRL, @@ -192,8 +193,9 @@ enum I2C_REGS_OFFSET { [OFFSET_TRANSFER_LEN_AUX] = 0x44, [OFFSET_CLOCK_DIV] = 0x48, [OFFSET_SOFTRESET] = 0x50, + [OFFSET_MULTI_DMA] = 0x84, [OFFSET_SCL_MIS_COMP_POINT] = 0x90, - [OFFSET_DEBUGSTAT] = 0xe0, + [OFFSET_DEBUGSTAT] = 0xe4, [OFFSET_DEBUGCTRL] = 0xe8, [OFFSET_FIFO_STAT] = 0xf4, [OFFSET_FIFO_THRESH] = 0xf8, @@ -828,6 +830,96 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) return 0; } +static void i2c_dump_register(struct mtk_i2c *i2c) +{ + dev_err(i2c->dev, "SLAVE_ADDR[0x%x]: 0x%x, INTR_MASK[0x%x]: 0x%x\n", + OFFSET_SLAVE_ADDR, + (mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR)), + OFFSET_INTR_MASK, + (mtk_i2c_readw(i2c, OFFSET_INTR_MASK))); + dev_err(i2c->dev, "INTR_STAT[0x%x]: 0x%x, CONTROL[0x%x]: 0x%x\n", + OFFSET_INTR_STAT, + (mtk_i2c_readw(i2c, OFFSET_INTR_STAT)), + OFFSET_CONTROL, + (mtk_i2c_readw(i2c, OFFSET_CONTROL))); + dev_err(i2c->dev, "TRANSFER_LEN[0x%x]: 0x%x, TRANSAC_LEN[0x%x]: 0x%x\n", + OFFSET_TRANSFER_LEN, + (mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN)), + OFFSET_TRANSAC_LEN, + (mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN))); + dev_err(i2c->dev, "DELAY_LEN[0x%x]: 0x%x, HTIMING[0x%x]: 0x%x\n", + OFFSET_DELAY_LEN, + (mtk_i2c_readw(i2c, OFFSET_DELAY_LEN)), + OFFSET_TIMING, + (mtk_i2c_readw(i2c, OFFSET_TIMING))); + dev_err(i2c->dev, "OFFSET_START[0x%x]: 0x%x\n", + OFFSET_START, + mtk_i2c_readw(i2c, OFFSET_START)); + dev_err(i2c->dev, "OFFSET_EXT_CONF[0x%x]: 0x%x\n", + OFFSET_EXT_CONF, + mtk_i2c_readw(i2c, OFFSET_EXT_CONF)); + dev_err(i2c->dev, "OFFSET_HS[0x%x]: 0x%x\n", + OFFSET_HS, + mtk_i2c_readw(i2c, OFFSET_HS)); + dev_err(i2c->dev, "OFFSET_IO_CONFIG[0x%x]: 0x%x\n", + OFFSET_IO_CONFIG, + mtk_i2c_readw(i2c, OFFSET_IO_CONFIG)); + dev_err(i2c->dev, "OFFSET_FIFO_ADDR_CLR[0x%x]: 0x%x\n", + OFFSET_FIFO_ADDR_CLR, + mtk_i2c_readw(i2c, OFFSET_FIFO_ADDR_CLR)); + dev_err(i2c->dev, "TRANSFER_LEN_AUX[0x%x]: 0x%x\n", + OFFSET_TRANSFER_LEN_AUX, + mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX)); + dev_err(i2c->dev, "CLOCK_DIV[0x%x]: 0x%x\n", + OFFSET_CLOCK_DIV, + mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV)); + dev_err(i2c->dev, "FIFO_STAT[0x%x]: 0x%x, FIFO_THRESH[0x%x]: 0x%x\n", + OFFSET_FIFO_STAT, + mtk_i2c_readw(i2c, OFFSET_FIFO_STAT), + OFFSET_FIFO_THRESH, + mtk_i2c_readw(i2c, OFFSET_FIFO_THRESH)); + dev_err(i2c->dev, "DCM_EN[0x%x] 0x%x\n", + OFFSET_DCM_EN, + mtk_i2c_readw(i2c, OFFSET_DCM_EN)); + dev_err(i2c->dev, "DEBUGSTAT[0x%x]: 0x%x, DEBUGCTRL[0x%x]: 0x%x\n", + OFFSET_DEBUGSTAT, + (mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT)), + OFFSET_DEBUGCTRL, + (mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL))); + + if (i2c->dev_comp->regs == mt_i2c_regs_v2) { + dev_err(i2c->dev, "OFFSET_LTIMING[0x%x]: 0x%x\n", + OFFSET_LTIMING, + mtk_i2c_readw(i2c, OFFSET_LTIMING)); + dev_err(i2c->dev, "MULTI_DMA[0x%x]: 0x%x\n", + OFFSET_MULTI_DMA, + (mtk_i2c_readw(i2c, OFFSET_MULTI_DMA))); + } + + dev_err(i2c->dev, "OFFSET_INT_FLAG = 0x%x\n", + readl(i2c->pdmabase + OFFSET_INT_FLAG)); + dev_err(i2c->dev, "OFFSET_INT_EN = 0x%x\n", + readl(i2c->pdmabase + OFFSET_INT_EN)); + dev_err(i2c->dev, "OFFSET_EN = 0x%x\n", + readl(i2c->pdmabase + OFFSET_EN)); + dev_err(i2c->dev, "OFFSET_RST = 0x%x\n", + readl(i2c->pdmabase + OFFSET_RST)); + dev_err(i2c->dev, "OFFSET_CON = 0x%x\n", + readl(i2c->pdmabase + OFFSET_CON)); + dev_err(i2c->dev, "OFFSET_TX_MEM_ADDR = 0x%x\n", + readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR)); + dev_err(i2c->dev, "OFFSET_RX_MEM_ADDR = 0x%x\n", + readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR)); + dev_err(i2c->dev, "OFFSET_TX_LEN = 0x%x\n", + readl(i2c->pdmabase + OFFSET_TX_LEN)); + dev_err(i2c->dev, "OFFSET_RX_LEN = 0x%x\n", + readl(i2c->pdmabase + OFFSET_RX_LEN)); + dev_err(i2c->dev, "OFFSET_TX_4G_MODE = 0x%x\n", + readl(i2c->pdmabase + OFFSET_TX_4G_MODE)); + dev_err(i2c->dev, "OFFSET_RX_4G_MODE = 0x%x\n", + readl(i2c->pdmabase + OFFSET_RX_4G_MODE)); +} + static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, int num, int left_num) { @@ -1034,7 +1126,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, } if (ret == 0) { - dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); + dev_err(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); + i2c_dump_register(i2c); mtk_i2c_init_hw(i2c); return -ETIMEDOUT; } -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] i2c: mediatek: Dump i2c/dma register when a timeout occurs 2021-06-08 3:16 ` [PATCH 2/3] i2c: mediatek: Dump i2c/dma register when a timeout occurs Kewei Xu @ 2021-06-08 14:01 ` Matthias Brugger 2021-06-09 2:43 ` Kewei Xu 0 siblings, 1 reply; 10+ messages in thread From: Matthias Brugger @ 2021-06-08 14:01 UTC (permalink / raw) To: Kewei Xu, wsa Cc: robh+dt, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream, leilk.liu, qii.wang, qiangming.xia On 08/06/2021 05:16, Kewei Xu wrote: > From: "Kewei.Xu" <kewei.xu@mediatek.com> > > When a timeout error occurs in i2c transter, it is usually related > to the i2c/dma IP hardware configuration. Therefore, the purpose of > this patch is to dump the key register values of i2c/dma when a > timeout occurs in i2c for debugging. > > Signed-off-by: Kewei.Xu <kewei.xu@mediatek.com> > --- > drivers/i2c/busses/i2c-mt65xx.c | 97 ++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 95 insertions(+), 2 deletions(-) > > diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c > index 5ddfa4e..e65a41e 100644 > --- a/drivers/i2c/busses/i2c-mt65xx.c > +++ b/drivers/i2c/busses/i2c-mt65xx.c > @@ -125,6 +125,7 @@ enum I2C_REGS_OFFSET { > OFFSET_HS, > OFFSET_SOFTRESET, > OFFSET_DCM_EN, > + OFFSET_MULTI_DMA, > OFFSET_PATH_DIR, > OFFSET_DEBUGSTAT, > OFFSET_DEBUGCTRL, > @@ -192,8 +193,9 @@ enum I2C_REGS_OFFSET { > [OFFSET_TRANSFER_LEN_AUX] = 0x44, > [OFFSET_CLOCK_DIV] = 0x48, > [OFFSET_SOFTRESET] = 0x50, > + [OFFSET_MULTI_DMA] = 0x84, > [OFFSET_SCL_MIS_COMP_POINT] = 0x90, > - [OFFSET_DEBUGSTAT] = 0xe0, > + [OFFSET_DEBUGSTAT] = 0xe4, Is this offset only for mt8192 or also for mt8183? In any case that should go in as another patch. Either a fix or a new mt_i2c_regs_v3[] Regards, Matthias > [OFFSET_DEBUGCTRL] = 0xe8, > [OFFSET_FIFO_STAT] = 0xf4, > [OFFSET_FIFO_THRESH] = 0xf8, > @@ -828,6 +830,96 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) > return 0; > } > > +static void i2c_dump_register(struct mtk_i2c *i2c) > +{ > + dev_err(i2c->dev, "SLAVE_ADDR[0x%x]: 0x%x, INTR_MASK[0x%x]: 0x%x\n", > + OFFSET_SLAVE_ADDR, > + (mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR)), > + OFFSET_INTR_MASK, > + (mtk_i2c_readw(i2c, OFFSET_INTR_MASK))); > + dev_err(i2c->dev, "INTR_STAT[0x%x]: 0x%x, CONTROL[0x%x]: 0x%x\n", > + OFFSET_INTR_STAT, > + (mtk_i2c_readw(i2c, OFFSET_INTR_STAT)), > + OFFSET_CONTROL, > + (mtk_i2c_readw(i2c, OFFSET_CONTROL))); > + dev_err(i2c->dev, "TRANSFER_LEN[0x%x]: 0x%x, TRANSAC_LEN[0x%x]: 0x%x\n", > + OFFSET_TRANSFER_LEN, > + (mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN)), > + OFFSET_TRANSAC_LEN, > + (mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN))); > + dev_err(i2c->dev, "DELAY_LEN[0x%x]: 0x%x, HTIMING[0x%x]: 0x%x\n", > + OFFSET_DELAY_LEN, > + (mtk_i2c_readw(i2c, OFFSET_DELAY_LEN)), > + OFFSET_TIMING, > + (mtk_i2c_readw(i2c, OFFSET_TIMING))); > + dev_err(i2c->dev, "OFFSET_START[0x%x]: 0x%x\n", > + OFFSET_START, > + mtk_i2c_readw(i2c, OFFSET_START)); > + dev_err(i2c->dev, "OFFSET_EXT_CONF[0x%x]: 0x%x\n", > + OFFSET_EXT_CONF, > + mtk_i2c_readw(i2c, OFFSET_EXT_CONF)); > + dev_err(i2c->dev, "OFFSET_HS[0x%x]: 0x%x\n", > + OFFSET_HS, > + mtk_i2c_readw(i2c, OFFSET_HS)); > + dev_err(i2c->dev, "OFFSET_IO_CONFIG[0x%x]: 0x%x\n", > + OFFSET_IO_CONFIG, > + mtk_i2c_readw(i2c, OFFSET_IO_CONFIG)); > + dev_err(i2c->dev, "OFFSET_FIFO_ADDR_CLR[0x%x]: 0x%x\n", > + OFFSET_FIFO_ADDR_CLR, > + mtk_i2c_readw(i2c, OFFSET_FIFO_ADDR_CLR)); > + dev_err(i2c->dev, "TRANSFER_LEN_AUX[0x%x]: 0x%x\n", > + OFFSET_TRANSFER_LEN_AUX, > + mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX)); > + dev_err(i2c->dev, "CLOCK_DIV[0x%x]: 0x%x\n", > + OFFSET_CLOCK_DIV, > + mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV)); > + dev_err(i2c->dev, "FIFO_STAT[0x%x]: 0x%x, FIFO_THRESH[0x%x]: 0x%x\n", > + OFFSET_FIFO_STAT, > + mtk_i2c_readw(i2c, OFFSET_FIFO_STAT), > + OFFSET_FIFO_THRESH, > + mtk_i2c_readw(i2c, OFFSET_FIFO_THRESH)); > + dev_err(i2c->dev, "DCM_EN[0x%x] 0x%x\n", > + OFFSET_DCM_EN, > + mtk_i2c_readw(i2c, OFFSET_DCM_EN)); > + dev_err(i2c->dev, "DEBUGSTAT[0x%x]: 0x%x, DEBUGCTRL[0x%x]: 0x%x\n", > + OFFSET_DEBUGSTAT, > + (mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT)), > + OFFSET_DEBUGCTRL, > + (mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL))); > + > + if (i2c->dev_comp->regs == mt_i2c_regs_v2) { > + dev_err(i2c->dev, "OFFSET_LTIMING[0x%x]: 0x%x\n", > + OFFSET_LTIMING, > + mtk_i2c_readw(i2c, OFFSET_LTIMING)); > + dev_err(i2c->dev, "MULTI_DMA[0x%x]: 0x%x\n", > + OFFSET_MULTI_DMA, > + (mtk_i2c_readw(i2c, OFFSET_MULTI_DMA))); > + } > + > + dev_err(i2c->dev, "OFFSET_INT_FLAG = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_INT_FLAG)); > + dev_err(i2c->dev, "OFFSET_INT_EN = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_INT_EN)); > + dev_err(i2c->dev, "OFFSET_EN = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_EN)); > + dev_err(i2c->dev, "OFFSET_RST = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_RST)); > + dev_err(i2c->dev, "OFFSET_CON = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_CON)); > + dev_err(i2c->dev, "OFFSET_TX_MEM_ADDR = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR)); > + dev_err(i2c->dev, "OFFSET_RX_MEM_ADDR = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR)); > + dev_err(i2c->dev, "OFFSET_TX_LEN = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_TX_LEN)); > + dev_err(i2c->dev, "OFFSET_RX_LEN = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_RX_LEN)); > + dev_err(i2c->dev, "OFFSET_TX_4G_MODE = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_TX_4G_MODE)); > + dev_err(i2c->dev, "OFFSET_RX_4G_MODE = 0x%x\n", > + readl(i2c->pdmabase + OFFSET_RX_4G_MODE)); > +} > + > static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, > int num, int left_num) > { > @@ -1034,7 +1126,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, > } > > if (ret == 0) { > - dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); > + dev_err(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); > + i2c_dump_register(i2c); > mtk_i2c_init_hw(i2c); > return -ETIMEDOUT; > } > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] i2c: mediatek: Dump i2c/dma register when a timeout occurs 2021-06-08 14:01 ` Matthias Brugger @ 2021-06-09 2:43 ` Kewei Xu 2021-06-29 4:19 ` Tzung-Bi Shih 0 siblings, 1 reply; 10+ messages in thread From: Kewei Xu @ 2021-06-09 2:43 UTC (permalink / raw) To: Matthias Brugger Cc: wsa, robh+dt, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream, leilk.liu, qii.wang, qiangming.xia, liguo.zhang On Tue, 2021-06-08 at 16:01 +0200, Matthias Brugger wrote: > > On 08/06/2021 05:16, Kewei Xu wrote: > > From: "Kewei.Xu" <kewei.xu@mediatek.com> > > > > When a timeout error occurs in i2c transter, it is usually related > > to the i2c/dma IP hardware configuration. Therefore, the purpose of > > this patch is to dump the key register values of i2c/dma when a > > timeout occurs in i2c for debugging. > > > > Signed-off-by: Kewei.Xu <kewei.xu@mediatek.com> > > --- > > drivers/i2c/busses/i2c-mt65xx.c | 97 ++++++++++++++++++++++++++++++++++++++++- > > 1 file changed, 95 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c > > index 5ddfa4e..e65a41e 100644 > > --- a/drivers/i2c/busses/i2c-mt65xx.c > > +++ b/drivers/i2c/busses/i2c-mt65xx.c > > @@ -125,6 +125,7 @@ enum I2C_REGS_OFFSET { > > OFFSET_HS, > > OFFSET_SOFTRESET, > > OFFSET_DCM_EN, > > + OFFSET_MULTI_DMA, > > OFFSET_PATH_DIR, > > OFFSET_DEBUGSTAT, > > OFFSET_DEBUGCTRL, > > @@ -192,8 +193,9 @@ enum I2C_REGS_OFFSET { > > [OFFSET_TRANSFER_LEN_AUX] = 0x44, > > [OFFSET_CLOCK_DIV] = 0x48, > > [OFFSET_SOFTRESET] = 0x50, > > + [OFFSET_MULTI_DMA] = 0x84, > > [OFFSET_SCL_MIS_COMP_POINT] = 0x90, > > - [OFFSET_DEBUGSTAT] = 0xe0, > > + [OFFSET_DEBUGSTAT] = 0xe4, > > Is this offset only for mt8192 or also for mt8183? > In any case that should go in as another patch. Either a fix or a new > mt_i2c_regs_v3[] > > Regards, Matthias Hi Matthias, This offset value is suitable for the IC of mt_i2c_regs_v2 hardware design similar to mt8192/8195, not for 8183. The reason for the modification here is that the previous offset information is incorrect, OFFSET_DEBUGSTAT = 0XE4 is the correct value. Regards, Kewei ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] i2c: mediatek: Dump i2c/dma register when a timeout occurs 2021-06-09 2:43 ` Kewei Xu @ 2021-06-29 4:19 ` Tzung-Bi Shih 2021-06-29 12:12 ` Kewei Xu 0 siblings, 1 reply; 10+ messages in thread From: Tzung-Bi Shih @ 2021-06-29 4:19 UTC (permalink / raw) To: Kewei Xu Cc: Matthias Brugger, wsa, robh+dt, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream, leilk.liu, qii.wang, qiangming.xia, liguo.zhang On Wed, Jun 9, 2021 at 10:44 AM Kewei Xu <kewei.xu@mediatek.com> wrote: > > On Tue, 2021-06-08 at 16:01 +0200, Matthias Brugger wrote: > > Is this offset only for mt8192 or also for mt8183? > > In any case that should go in as another patch. Either a fix or a new > > mt_i2c_regs_v3[] > > This offset value is suitable for the IC of mt_i2c_regs_v2 hardware > design similar to mt8192/8195, not for 8183. > > The reason for the modification here is that the previous > offset information is incorrect, OFFSET_DEBUGSTAT = 0XE4 is > the correct value. Please submit another patch for fixing the incorrect value. ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] i2c: mediatek: Dump i2c/dma register when a timeout occurs 2021-06-29 4:19 ` Tzung-Bi Shih @ 2021-06-29 12:12 ` Kewei Xu 0 siblings, 0 replies; 10+ messages in thread From: Kewei Xu @ 2021-06-29 12:12 UTC (permalink / raw) To: Tzung-Bi Shih Cc: Matthias Brugger, wsa, robh+dt, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream, leilk.liu, qii.wang, qiangming.xia, liguo.zhang On Tue, 2021-06-29 at 12:19 +0800, Tzung-Bi Shih wrote: > On Wed, Jun 9, 2021 at 10:44 AM Kewei Xu <kewei.xu@mediatek.com> wrote: > > > > On Tue, 2021-06-08 at 16:01 +0200, Matthias Brugger wrote: > > > Is this offset only for mt8192 or also for mt8183? > > > In any case that should go in as another patch. Either a fix or a new > > > mt_i2c_regs_v3[] > > > > This offset value is suitable for the IC of mt_i2c_regs_v2 hardware > > design similar to mt8192/8195, not for 8183. > > > > The reason for the modification here is that the previous > > offset information is incorrect, OFFSET_DEBUGSTAT = 0XE4 is > > the correct value. > > Please submit another patch for fixing the incorrect value. Okay, I will resubmit a patch to fixing the incorrect value,Thanks. ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] i2c: mediatek: Reset the handshake signal between i2c and dma 2021-06-08 3:16 [PATCH 0/3] add i2c support for mt8195 Kewei Xu 2021-06-08 3:16 ` [PATCH 1/3] dt-bindings: i2c: update bindings for MT8195 SoC Kewei Xu 2021-06-08 3:16 ` [PATCH 2/3] i2c: mediatek: Dump i2c/dma register when a timeout occurs Kewei Xu @ 2021-06-08 3:16 ` Kewei Xu 2 siblings, 0 replies; 10+ messages in thread From: Kewei Xu @ 2021-06-08 3:16 UTC (permalink / raw) To: wsa Cc: matthias.bgg, robh+dt, linux-i2c, devicetree, linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream, leilk.liu, qii.wang, qiangming.xia, kewei.xu From: "Kewei.Xu" <kewei.xu@mediatek.com> Due to changes in the hardware design of the handshaking signal between i2c and dma, it is necessary to reset the handshaking signal before each transfer to ensure that the multi-msgs can be transferred correctly. Signed-off-by: Kewei.Xu <kewei.xu@mediatek.com> --- drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index e65a41e..ded94f9 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -47,6 +47,9 @@ #define I2C_RD_TRANAC_VALUE 0x0001 #define I2C_SCL_MIS_COMP_VALUE 0x0000 #define I2C_CHN_CLR_FLAG 0x0000 +#define I2C_CLR_DEBUGCTR 0x0000 +#define I2C_RELIABILITY 0x0010 +#define I2C_DMAACK_ENABLE 0x0008 #define I2C_DMA_CON_TX 0x0000 #define I2C_DMA_CON_RX 0x0001 @@ -942,6 +945,17 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, reinit_completion(&i2c->msg_complete); + if (i2c->dev_comp->apdma_sync) { + mtk_i2c_writew(i2c, I2C_CLR_DEBUGCTR, OFFSET_DEBUGCTRL); + writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST, + i2c->pdmabase + OFFSET_RST); + writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); + mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET); + mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); + mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE, + OFFSET_DEBUGCTRL); + } + control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1)) -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-06-29 12:13 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-06-08 3:16 [PATCH 0/3] add i2c support for mt8195 Kewei Xu 2021-06-08 3:16 ` [PATCH 1/3] dt-bindings: i2c: update bindings for MT8195 SoC Kewei Xu 2021-06-08 13:59 ` Matthias Brugger 2021-06-18 20:27 ` Rob Herring 2021-06-08 3:16 ` [PATCH 2/3] i2c: mediatek: Dump i2c/dma register when a timeout occurs Kewei Xu 2021-06-08 14:01 ` Matthias Brugger 2021-06-09 2:43 ` Kewei Xu 2021-06-29 4:19 ` Tzung-Bi Shih 2021-06-29 12:12 ` Kewei Xu 2021-06-08 3:16 ` [PATCH 3/3] i2c: mediatek: Reset the handshake signal between i2c and dma Kewei Xu
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