From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@redhat.com,
gregkh@linuxfoundation.org, acme@kernel.org,
linux-kernel@vger.kernel.org
Cc: eranian@google.com, namhyung@kernel.org, jolsa@redhat.com,
ak@linux.intel.com, yao.jin@linux.intel.com,
Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V4 08/16] perf/x86/intel/uncore: Add Sapphire Rapids server M2M support
Date: Wed, 30 Jun 2021 14:08:32 -0700 [thread overview]
Message-ID: <1625087320-194204-9-git-send-email-kan.liang@linux.intel.com> (raw)
In-Reply-To: <1625087320-194204-1-git-send-email-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
The M2M blocks manage the interface between the mesh (operating on both
the mesh and the SMI3 protocol) and the memory controllers.
The layout of the control registers for a M2M uncore unit is a little
bit different from the generic one. So a specific format and ops are
required. Expose the common PCI ops which can be reused.
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/uncore_discovery.c | 14 +++++++-------
arch/x86/events/intel/uncore_discovery.h | 8 ++++++++
arch/x86/events/intel/uncore_snbep.c | 30 +++++++++++++++++++++++++++++-
3 files changed, 44 insertions(+), 8 deletions(-)
diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/intel/uncore_discovery.c
index cc44311..6322df1 100644
--- a/arch/x86/events/intel/uncore_discovery.c
+++ b/arch/x86/events/intel/uncore_discovery.c
@@ -377,7 +377,7 @@ static struct intel_uncore_ops generic_uncore_msr_ops = {
.read_counter = uncore_msr_read_counter,
};
-static void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box)
+void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box)
{
struct pci_dev *pdev = box->pci_dev;
int box_ctl = uncore_pci_box_ctl(box);
@@ -386,7 +386,7 @@ static void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box)
pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_INT);
}
-static void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box)
+void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box)
{
struct pci_dev *pdev = box->pci_dev;
int box_ctl = uncore_pci_box_ctl(box);
@@ -394,7 +394,7 @@ static void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box)
pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_FRZ);
}
-static void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box)
+void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box)
{
struct pci_dev *pdev = box->pci_dev;
int box_ctl = uncore_pci_box_ctl(box);
@@ -411,8 +411,8 @@ static void intel_generic_uncore_pci_enable_event(struct intel_uncore_box *box,
pci_write_config_dword(pdev, hwc->config_base, hwc->config);
}
-static void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,
- struct perf_event *event)
+void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,
+ struct perf_event *event)
{
struct pci_dev *pdev = box->pci_dev;
struct hw_perf_event *hwc = &event->hw;
@@ -420,8 +420,8 @@ static void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,
pci_write_config_dword(pdev, hwc->config_base, 0);
}
-static u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,
- struct perf_event *event)
+u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,
+ struct perf_event *event)
{
struct pci_dev *pdev = box->pci_dev;
struct hw_perf_event *hwc = &event->hw;
diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/intel/uncore_discovery.h
index eeab94c..c2c2231 100644
--- a/arch/x86/events/intel/uncore_discovery.h
+++ b/arch/x86/events/intel/uncore_discovery.h
@@ -140,5 +140,13 @@ void intel_generic_uncore_mmio_enable_box(struct intel_uncore_box *box);
void intel_generic_uncore_mmio_disable_event(struct intel_uncore_box *box,
struct perf_event *event);
+void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box);
+void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box);
+void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box);
+void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,
+ struct perf_event *event);
+u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,
+ struct perf_event *event);
+
struct intel_uncore_type **
intel_uncore_generic_init_uncores(enum uncore_access_type type_id);
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index e6827e3..ff2cc02 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -5512,6 +5512,34 @@ static struct intel_uncore_type spr_uncore_imc = {
.ops = &spr_uncore_mmio_ops,
};
+static void spr_uncore_pci_enable_event(struct intel_uncore_box *box,
+ struct perf_event *event)
+{
+ struct pci_dev *pdev = box->pci_dev;
+ struct hw_perf_event *hwc = &event->hw;
+
+ pci_write_config_dword(pdev, hwc->config_base + 4, (u32)(hwc->config >> 32));
+ pci_write_config_dword(pdev, hwc->config_base, (u32)hwc->config);
+}
+
+static struct intel_uncore_ops spr_uncore_pci_ops = {
+ .init_box = intel_generic_uncore_pci_init_box,
+ .disable_box = intel_generic_uncore_pci_disable_box,
+ .enable_box = intel_generic_uncore_pci_enable_box,
+ .disable_event = intel_generic_uncore_pci_disable_event,
+ .enable_event = spr_uncore_pci_enable_event,
+ .read_counter = intel_generic_uncore_pci_read_counter,
+};
+
+#define SPR_UNCORE_PCI_COMMON_FORMAT() \
+ SPR_UNCORE_COMMON_FORMAT(), \
+ .ops = &spr_uncore_pci_ops
+
+static struct intel_uncore_type spr_uncore_m2m = {
+ SPR_UNCORE_PCI_COMMON_FORMAT(),
+ .name = "m2m",
+};
+
#define UNCORE_SPR_NUM_UNCORE_TYPES 12
static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
@@ -5522,7 +5550,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
&spr_uncore_pcu,
NULL,
&spr_uncore_imc,
- NULL,
+ &spr_uncore_m2m,
NULL,
NULL,
NULL,
--
2.7.4
next prev parent reply other threads:[~2021-06-30 21:10 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-30 21:08 [PATCH V4 00/16] perf: Add Sapphire Rapids server uncore support kan.liang
2021-06-30 21:08 ` [PATCH V4 01/16] perf/x86/intel/uncore: Add Sapphire Rapids server framework kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 02/16] perf/x86/intel/uncore: Add Sapphire Rapids server CHA support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 03/16] perf/x86/intel/uncore: Add Sapphire Rapids server IIO support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 04/16] perf/x86/intel/uncore: Add Sapphire Rapids server IRP support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 05/16] perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 06/16] perf/x86/intel/uncore: Add Sapphire Rapids server PCU support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 07/16] perf/x86/intel/uncore: Add Sapphire Rapids server IMC support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` kan.liang [this message]
2021-07-05 7:53 ` [tip: perf/core] perf/x86/intel/uncore: Add Sapphire Rapids server M2M support tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 09/16] perf/x86/intel/uncore: Add Sapphire Rapids server UPI support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 10/16] perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 11/16] perf/x86/intel/uncore: Add Sapphire Rapids server MDF support kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 12/16] perf/x86/intel/uncore: Add alias PMU name kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 13/16] perf/x86/intel/uncore: Factor out snr_uncore_mmio_map() kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 14/16] perf/x86/intel/uncore: Support IIO free-running counters on Sapphire Rapids server kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 15/16] perf/x86/intel/uncore: Support IMC " kan.liang
2021-07-05 7:53 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-06-30 21:08 ` [PATCH V4 16/16] perf pmu: Add PMU alias support kan.liang
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