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From: Stephen Boyd <sboyd@kernel.org>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	linux-clk@vger.kernel.org, mturquette@baylibre.com
Cc: narmstrong@baylibre.com, jbrunet@baylibre.com,
	khilman@baylibre.com, linux-kernel@vger.kernel.org,
	linux-amlogic@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: Re: [PATCH v3 2/3] clk: divider: Switch from .round_rate to .determine_rate by default
Date: Thu, 01 Jul 2021 18:04:18 -0700	[thread overview]
Message-ID: <162518785878.3570193.8070459883237401552@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20210627223959.188139-3-martin.blumenstingl@googlemail.com>

Quoting Martin Blumenstingl (2021-06-27 15:39:58)
> .determine_rate is meant to replace .round_rate. The former comes with a
> benefit which is especially relevant on 32-bit systems: since
> .determine_rate uses an "unsigned long" (compared to a "signed long"
> which is used by .round_rate) the maximum value on 32-bit systems
> increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz).
> Switch to a .determine_rate implementation by default so 32-bit systems
> can benefit from the increased maximum value as well as so we have one
> fewer user of .round_rate.
> 
> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  drivers/clk/clk-divider.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 87ba4966b0e8..9e05e81116af 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -425,8 +425,8 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
>  }
>  EXPORT_SYMBOL_GPL(divider_ro_round_rate_parent);
>  
> -static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
> -                               unsigned long *prate)
> +static int clk_divider_determine_rate(struct clk_hw *hw,
> +                                     struct clk_rate_request *req)
>  {
>         struct clk_divider *divider = to_clk_divider(hw);
>  
> @@ -437,13 +437,13 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
>                 val = clk_div_readl(divider) >> divider->shift;
>                 val &= clk_div_mask(divider->width);
>  
> -               return divider_ro_round_rate(hw, rate, prate, divider->table,
> -                                            divider->width, divider->flags,
> -                                            val);
> +               return divider_ro_determine_rate(hw, req, divider->table,
> +                                                divider->width,
> +                                                divider->flags, val);
>         }
>  
> -       return divider_round_rate(hw, rate, prate, divider->table,
> -                                 divider->width, divider->flags);
> +       return divider_determine_rate(hw, req, divider->table, divider->width,
> +                                     divider->flags);
>  }
>  
>  int divider_get_val(unsigned long rate, unsigned long parent_rate,
> @@ -500,14 +500,14 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
>  
>  const struct clk_ops clk_divider_ops = {
>         .recalc_rate = clk_divider_recalc_rate,
> -       .round_rate = clk_divider_round_rate,
> +       .determine_rate = clk_divider_determine_rate,

Guess was right.

 $ git grep clk_divider_ops -- drivers/clk/imx/
 drivers/clk/imx/clk-divider-gate.c:     return clk_divider_ops.round_rate(hw, rate, prate);

>         .set_rate = clk_divider_set_rate,
>  };
>  EXPORT_SYMBOL_GPL(clk_divider_ops);
>  
>  const struct clk_ops clk_divider_ro_ops = {
>         .recalc_rate = clk_divider_recalc_rate,
> -       .round_rate = clk_divider_round_rate,
> +       .determine_rate = clk_divider_determine_rate,

  parent reply	other threads:[~2021-07-02  1:04 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-27 22:39 [PATCH v3 0/3] clk: meson: rounding for fast clocks on 32-bit SoCs Martin Blumenstingl
2021-06-27 22:39 ` [PATCH v3 1/3] clk: divider: Add re-usable determine_rate implementations Martin Blumenstingl
2021-06-30 18:39   ` Stephen Boyd
2021-06-27 22:39 ` [PATCH v3 2/3] clk: divider: Switch from .round_rate to .determine_rate by default Martin Blumenstingl
2021-06-30 18:39   ` Stephen Boyd
2021-07-01 20:25   ` Guenter Roeck
2021-07-01 20:57     ` Martin Blumenstingl
2021-07-01 21:43       ` Guenter Roeck
2021-07-02  0:53         ` Stephen Boyd
2021-07-02  1:02       ` Stephen Boyd
2021-07-02  9:19         ` Martin Blumenstingl
     [not found]           ` <CGME20210702124612eucas1p1762911deb37e4fb03adc9239bb715135@eucas1p1.samsung.com>
2021-07-02 12:46             ` Marek Szyprowski
2021-07-02 21:00               ` Stephen Boyd
2021-07-02 20:59           ` Stephen Boyd
2021-07-02 22:57             ` Martin Blumenstingl
2021-07-02  1:04   ` Stephen Boyd [this message]
2021-06-27 22:39 ` [PATCH v3 3/3] clk: meson: regmap: switch to determine_rate for the dividers Martin Blumenstingl
2021-06-30 18:39   ` Stephen Boyd

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