From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD1A9C07E9B for ; Fri, 9 Jul 2021 09:51:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C7528613E3 for ; Fri, 9 Jul 2021 09:51:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232246AbhGIJyS (ORCPT ); Fri, 9 Jul 2021 05:54:18 -0400 Received: from mga05.intel.com ([192.55.52.43]:54438 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232225AbhGIJyO (ORCPT ); Fri, 9 Jul 2021 05:54:14 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10039"; a="295316526" X-IronPort-AV: E=Sophos;i="5.84,226,1620716400"; d="scan'208";a="295316526" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jul 2021 02:51:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,226,1620716400"; d="scan'208";a="498856350" Received: from michael-optiplex-9020.sh.intel.com ([10.239.159.182]) by fmsmga002.fm.intel.com with ESMTP; 09 Jul 2021 02:51:28 -0700 From: Yang Weijiang To: pbonzini@redhat.com, seanjc@google.com, vkuznets@redhat.com, jmattson@google.com, wei.w.wang@intel.com, like.xu.linux@gmail.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Like Xu , Yang Weijiang Subject: [PATCH v5 11/13] KVM: x86: Add XSAVE Support for Architectural LBR Date: Fri, 9 Jul 2021 18:05:09 +0800 Message-Id: <1625825111-6604-12-git-send-email-weijiang.yang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1625825111-6604-1-git-send-email-weijiang.yang@intel.com> References: <1625825111-6604-1-git-send-email-weijiang.yang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Like Xu On processors supporting XSAVES and XRSTORS, Architectural LBR XSAVE support is enumerated from CPUID.(EAX=0DH, ECX=1):ECX[bit 15]. The detailed sub-leaf for Arch LBR is enumerated in CPUID.(0DH, 0FH). XSAVES provides a faster means than RDMSR for guest to read all LBRs. When guest IA32_XSS[bit 15] is set, the Arch LBR state can be saved using XSAVES and restored by XRSTORS with the appropriate RFBM. Signed-off-by: Like Xu Signed-off-by: Yang Weijiang --- arch/x86/kvm/vmx/vmx.c | 4 ++++ arch/x86/kvm/x86.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 636c50b95038..3eccda710495 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7337,6 +7337,10 @@ static __init void vmx_set_cpu_caps(void) kvm_cpu_cap_clear(X86_FEATURE_INVPCID); if (vmx_pt_mode_is_host_guest()) kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT); + if (!cpu_has_vmx_arch_lbr()) { + kvm_cpu_cap_clear(X86_FEATURE_ARCH_LBR); + supported_xss &= ~XFEATURE_MASK_LBR; + } if (!enable_sgx) { kvm_cpu_cap_clear(X86_FEATURE_SGX); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 2424d475a4d7..c09522c1f3ec 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -203,7 +203,7 @@ static struct kvm_user_return_msrs __percpu *user_return_msrs; | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | XFEATURE_MASK_PKRU) -#define KVM_SUPPORTED_XSS 0 +#define KVM_SUPPORTED_XSS XFEATURE_MASK_LBR u64 __read_mostly host_efer; EXPORT_SYMBOL_GPL(host_efer); -- 2.21.1