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* [PATCH v14 0/6] Re-introduce TX FIFO resize for larger EP bursting
@ 2021-07-10  9:13 Wesley Cheng
  2021-07-10  9:13 ` [PATCH v14 1/6] usb: gadget: udc: core: Introduce check_config to verify USB configuration Wesley Cheng
                   ` (5 more replies)
  0 siblings, 6 replies; 18+ messages in thread
From: Wesley Cheng @ 2021-07-10  9:13 UTC (permalink / raw)
  To: balbi, gregkh, agross, bjorn.andersson, robh+dt, frowand.list
  Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree, jackp, Wesley Cheng

Changes in V14:
 - Adding missing comment for do_fifo_resize parameter.

Changes in V13:
 - Added some more comments on the background of the APIs and how they work.
 - Check for the do_fifo_resize flag before reading out the max number of fifos
   DT property.

Changes in V12:
 - Re-added change to add a stub for of_add_property(), and exporting it as well
   so that it can be used by modules.
 - Minor updates to some of the APIs, including updating comments, adding error
   handling, etc...

Changes in V11:
 - Added a DWC3 controller revision check to use a different calculation, based
   on Ferry's testing.
 - Removed descriptor loop in configfs, and utilize the fact that the ep->claimed
   parameter is still valid as ep_autoconf_reset() isn't called at the time of
   check_config()
 - Fix compilation errors if CONFIG_OF is not defined
 - Removed patch to add stubs for of_add_property()

Changes in V10:
 - Fixed compilation errors in config where OF is not used (error due to
   unknown symbol for of_add_property()).  Add of_add_property() stub.
 - Fixed compilation warning for incorrect argument being passed to dwc3_mdwidth

Changes in V9:
 - Fixed incorrect patch in series.  Removed changes in DTSI, as dwc3-qcom will
   add the property by default from the kernel.

Changes in V8:
 - Rebased to usb-testing
 - Using devm_kzalloc for adding txfifo property in dwc3-qcom
 - Removed DWC3 QCOM ACPI property for enabling the txfifo resize

Changes in V7:
 - Added a new property tx-fifo-max-num for limiting how much fifo space the
   resizing logic can allocate for endpoints with large burst values.  This
   can differ across platforms, and tie in closely with overall system latency.
 - Added recommended checks for DWC32.
 - Added changes to set the tx-fifo-resize property from dwc3-qcom by default
   instead of modifying the current DTSI files.
 - Added comments on all APIs/variables introduced.
 - Updated the DWC3 YAML to include a better description of the tx-fifo-resize
   property and added an entry for tx-fifo-max-num.

Changes in V6:
 - Rebased patches to usb-testing.
 - Renamed to PATCH series instead of RFC.
 - Checking for fs_descriptors instead of ss_descriptors for determining the
   endpoint count for a particular configuration.
 - Re-ordered patch series to fix patch dependencies.

Changes in V5:
 - Added check_config() logic, which is used to communicate the number of EPs
   used in a particular configuration.  Based on this, the DWC3 gadget driver
   has the ability to know the maximum number of eps utilized in all configs.
   This helps reduce unnecessary allocation to unused eps, and will catch fifo
   allocation issues at bind() time.
 - Fixed variable declaration to single line per variable, and reverse xmas.
 - Created a helper for fifo clearing, which is used by ep0.c

Changes in V4:
 - Removed struct dwc3* as an argument for dwc3_gadget_resize_tx_fifos()
 - Removed WARN_ON(1) in case we run out of fifo space
 
Changes in V3:
 - Removed "Reviewed-by" tags
 - Renamed series back to RFC
 - Modified logic to ensure that fifo_size is reset if we pass the minimum
   threshold.  Tested with binding multiple FDs requesting 6 FIFOs.

Changes in V2:
 - Modified TXFIFO resizing logic to ensure that each EP is reserved a
   FIFO.
 - Removed dev_dbg() prints and fixed typos from patches
 - Added some more description on the dt-bindings commit message

Currently, there is no functionality to allow for resizing the TXFIFOs, and
relying on the HW default setting for the TXFIFO depth.  In most cases, the
HW default is probably sufficient, but for USB compositions that contain
multiple functions that require EP bursting, the default settings
might not be enough.  Also to note, the current SW will assign an EP to a
function driver w/o checking to see if the TXFIFO size for that particular
EP is large enough. (this is a problem if there are multiple HW defined
values for the TXFIFO size)

It is mentioned in the SNPS databook that a minimum of TX FIFO depth = 3
is required for an EP that supports bursting.  Otherwise, there may be
frequent occurences of bursts ending.  For high bandwidth functions,
such as data tethering (protocols that support data aggregation), mass
storage, and media transfer protocol (over FFS), the bMaxBurst value can be
large, and a bigger TXFIFO depth may prove to be beneficial in terms of USB
throughput. (which can be associated to system access latency, etc...)  It
allows for a more consistent burst of traffic, w/o any interruptions, as
data is readily available in the FIFO.

With testing done using the mass storage function driver, the results show
that with a larger TXFIFO depth, the bandwidth increased significantly.

Test Parameters:
 - Platform: Qualcomm SM8150
 - bMaxBurst = 6
 - USB req size = 256kB
 - Num of USB reqs = 16
 - USB Speed = Super-Speed
 - Function Driver: Mass Storage (w/ ramdisk)
 - Test Application: CrystalDiskMark

Results:

TXFIFO Depth = 3 max packets

Test Case | Data Size | AVG tput (in MB/s)
-------------------------------------------
Sequential|1 GB x     | 
Read      |9 loops    | 193.60
	  |           | 195.86
          |           | 184.77
          |           | 193.60
-------------------------------------------

TXFIFO Depth = 6 max packets

Test Case | Data Size | AVG tput (in MB/s)
-------------------------------------------
Sequential|1 GB x     | 
Read      |9 loops    | 287.35
	  |           | 304.94
          |           | 289.64
          |           | 293.61
-------------------------------------------

Wesley Cheng (6):
  usb: gadget: udc: core: Introduce check_config to verify USB
    configuration
  usb: gadget: configfs: Check USB configuration before adding
  usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
  of: Add stub for of_add_property()
  usb: dwc3: dwc3-qcom: Enable tx-fifo-resize property by default
  dt-bindings: usb: dwc3: Update dwc3 TX fifo properties

 .../devicetree/bindings/usb/snps,dwc3.yaml         |  15 +-
 drivers/of/base.c                                  |   1 +
 drivers/usb/dwc3/core.c                            |  15 ++
 drivers/usb/dwc3/core.h                            |  16 ++
 drivers/usb/dwc3/dwc3-qcom.c                       |  15 ++
 drivers/usb/dwc3/ep0.c                             |   2 +
 drivers/usb/dwc3/gadget.c                          | 232 +++++++++++++++++++++
 drivers/usb/gadget/configfs.c                      |   4 +
 drivers/usb/gadget/udc/core.c                      |  19 ++
 include/linux/of.h                                 |   5 +
 include/linux/usb/gadget.h                         |   4 +
 11 files changed, 326 insertions(+), 2 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 18+ messages in thread

* [PATCH v14 1/6] usb: gadget: udc: core: Introduce check_config to verify USB configuration
  2021-07-10  9:13 [PATCH v14 0/6] Re-introduce TX FIFO resize for larger EP bursting Wesley Cheng
@ 2021-07-10  9:13 ` Wesley Cheng
  2021-07-10  9:13 ` [PATCH v14 2/6] usb: gadget: configfs: Check USB configuration before adding Wesley Cheng
                   ` (4 subsequent siblings)
  5 siblings, 0 replies; 18+ messages in thread
From: Wesley Cheng @ 2021-07-10  9:13 UTC (permalink / raw)
  To: balbi, gregkh, agross, bjorn.andersson, robh+dt, frowand.list
  Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree, jackp, Wesley Cheng

Some UDCs may have constraints on how many high bandwidth endpoints it can
support in a certain configuration.  This API allows for the composite
driver to pass down the total number of endpoints to the UDC so it can verify
it has the required resources to support the configuration.

Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
---
 drivers/usb/gadget/udc/core.c | 19 +++++++++++++++++++
 include/linux/usb/gadget.h    |  4 ++++
 2 files changed, 23 insertions(+)

diff --git a/drivers/usb/gadget/udc/core.c b/drivers/usb/gadget/udc/core.c
index b7f0b1e..14fdf91 100644
--- a/drivers/usb/gadget/udc/core.c
+++ b/drivers/usb/gadget/udc/core.c
@@ -1003,6 +1003,25 @@ int usb_gadget_ep_match_desc(struct usb_gadget *gadget,
 }
 EXPORT_SYMBOL_GPL(usb_gadget_ep_match_desc);
 
+/**
+ * usb_gadget_check_config - checks if the UDC can support the binded
+ *	configuration
+ * @gadget: controller to check the USB configuration
+ *
+ * Ensure that a UDC is able to support the requested resources by a
+ * configuration, and that there are no resource limitations, such as
+ * internal memory allocated to all requested endpoints.
+ *
+ * Returns zero on success, else a negative errno.
+ */
+int usb_gadget_check_config(struct usb_gadget *gadget)
+{
+	if (gadget->ops->check_config)
+		return gadget->ops->check_config(gadget);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(usb_gadget_check_config);
+
 /* ------------------------------------------------------------------------- */
 
 static void usb_gadget_state_work(struct work_struct *work)
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
index 75c7538..776851e 100644
--- a/include/linux/usb/gadget.h
+++ b/include/linux/usb/gadget.h
@@ -329,6 +329,7 @@ struct usb_gadget_ops {
 	struct usb_ep *(*match_ep)(struct usb_gadget *,
 			struct usb_endpoint_descriptor *,
 			struct usb_ss_ep_comp_descriptor *);
+	int	(*check_config)(struct usb_gadget *gadget);
 };
 
 /**
@@ -608,6 +609,7 @@ int usb_gadget_connect(struct usb_gadget *gadget);
 int usb_gadget_disconnect(struct usb_gadget *gadget);
 int usb_gadget_deactivate(struct usb_gadget *gadget);
 int usb_gadget_activate(struct usb_gadget *gadget);
+int usb_gadget_check_config(struct usb_gadget *gadget);
 #else
 static inline int usb_gadget_frame_number(struct usb_gadget *gadget)
 { return 0; }
@@ -631,6 +633,8 @@ static inline int usb_gadget_deactivate(struct usb_gadget *gadget)
 { return 0; }
 static inline int usb_gadget_activate(struct usb_gadget *gadget)
 { return 0; }
+static inline int usb_gadget_check_config(struct usb_gadget *gadget)
+{ return 0; }
 #endif /* CONFIG_USB_GADGET */
 
 /*-------------------------------------------------------------------------*/
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 18+ messages in thread

* [PATCH v14 2/6] usb: gadget: configfs: Check USB configuration before adding
  2021-07-10  9:13 [PATCH v14 0/6] Re-introduce TX FIFO resize for larger EP bursting Wesley Cheng
  2021-07-10  9:13 ` [PATCH v14 1/6] usb: gadget: udc: core: Introduce check_config to verify USB configuration Wesley Cheng
@ 2021-07-10  9:13 ` Wesley Cheng
  2021-07-10  9:13 ` [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements Wesley Cheng
                   ` (3 subsequent siblings)
  5 siblings, 0 replies; 18+ messages in thread
From: Wesley Cheng @ 2021-07-10  9:13 UTC (permalink / raw)
  To: balbi, gregkh, agross, bjorn.andersson, robh+dt, frowand.list
  Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree, jackp, Wesley Cheng

Ensure that the USB gadget is able to support the configuration being
added based on the number of endpoints required from all interfaces.  This
is for accounting for any bandwidth or space limitations.

Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
---
 drivers/usb/gadget/configfs.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/usb/gadget/configfs.c b/drivers/usb/gadget/configfs.c
index 15a607c..f4c7c82 100644
--- a/drivers/usb/gadget/configfs.c
+++ b/drivers/usb/gadget/configfs.c
@@ -1404,6 +1404,10 @@ static int configfs_composite_bind(struct usb_gadget *gadget,
 				goto err_purge_funcs;
 			}
 		}
+		ret = usb_gadget_check_config(cdev->gadget);
+		if (ret)
+			goto err_purge_funcs;
+
 		usb_ep_autoconfig_reset(cdev->gadget);
 	}
 	if (cdev->use_os_string) {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 18+ messages in thread

* [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
  2021-07-10  9:13 [PATCH v14 0/6] Re-introduce TX FIFO resize for larger EP bursting Wesley Cheng
  2021-07-10  9:13 ` [PATCH v14 1/6] usb: gadget: udc: core: Introduce check_config to verify USB configuration Wesley Cheng
  2021-07-10  9:13 ` [PATCH v14 2/6] usb: gadget: configfs: Check USB configuration before adding Wesley Cheng
@ 2021-07-10  9:13 ` Wesley Cheng
  2021-07-12 23:38   ` Thinh Nguyen
  2021-07-10  9:13 ` [PATCH v14 4/6] of: Add stub for of_add_property() Wesley Cheng
                   ` (2 subsequent siblings)
  5 siblings, 1 reply; 18+ messages in thread
From: Wesley Cheng @ 2021-07-10  9:13 UTC (permalink / raw)
  To: balbi, gregkh, agross, bjorn.andersson, robh+dt, frowand.list
  Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree, jackp, Wesley Cheng

Some devices have USB compositions which may require multiple endpoints
that support EP bursting.  HW defined TX FIFO sizes may not always be
sufficient for these compositions.  By utilizing flexible TX FIFO
allocation, this allows for endpoints to request the required FIFO depth to
achieve higher bandwidth.  With some higher bMaxBurst configurations, using
a larger TX FIFO size results in better TX throughput.

By introducing the check_config() callback, the resizing logic can fetch
the maximum number of endpoints used in the USB composition (can contain
multiple configurations), which helps ensure that the resizing logic can
fulfill the configuration(s), or return an error to the gadget layer
otherwise during bind time.

Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
---
 drivers/usb/dwc3/core.c   |  15 +++
 drivers/usb/dwc3/core.h   |  16 ++++
 drivers/usb/dwc3/ep0.c    |   2 +
 drivers/usb/dwc3/gadget.c | 232 ++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 265 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index ba74ad7..b194aecd 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1267,6 +1267,7 @@ static void dwc3_get_properties(struct dwc3 *dwc)
 	u8			rx_max_burst_prd;
 	u8			tx_thr_num_pkt_prd;
 	u8			tx_max_burst_prd;
+	u8			tx_fifo_resize_max_num;
 	const char		*usb_psy_name;
 	int			ret;
 
@@ -1282,6 +1283,13 @@ static void dwc3_get_properties(struct dwc3 *dwc)
 	 */
 	hird_threshold = 12;
 
+	/*
+	 * default to a TXFIFO size large enough to fit 6 max packets.  This
+	 * allows for systems with larger bus latencies to have some headroom
+	 * for endpoints that have a large bMaxBurst value.
+	 */
+	tx_fifo_resize_max_num = 6;
+
 	dwc->maximum_speed = usb_get_maximum_speed(dev);
 	dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
 	dwc->dr_mode = usb_get_dr_mode(dev);
@@ -1325,6 +1333,11 @@ static void dwc3_get_properties(struct dwc3 *dwc)
 				&tx_thr_num_pkt_prd);
 	device_property_read_u8(dev, "snps,tx-max-burst-prd",
 				&tx_max_burst_prd);
+	dwc->do_fifo_resize = device_property_read_bool(dev,
+							"tx-fifo-resize");
+	if (dwc->do_fifo_resize)
+		device_property_read_u8(dev, "tx-fifo-max-num",
+					&tx_fifo_resize_max_num);
 
 	dwc->disable_scramble_quirk = device_property_read_bool(dev,
 				"snps,disable_scramble_quirk");
@@ -1390,6 +1403,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
 	dwc->tx_max_burst_prd = tx_max_burst_prd;
 
 	dwc->imod_interval = 0;
+
+	dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
 }
 
 /* check whether the core supports IMOD */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index dccdf13..735e9be 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -1023,6 +1023,7 @@ struct dwc3_scratchpad_array {
  * @rx_max_burst_prd: max periodic ESS receive burst size
  * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
  * @tx_max_burst_prd: max periodic ESS transmit burst size
+ * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize
  * @hsphy_interface: "utmi" or "ulpi"
  * @connected: true when we're connected to a host, false otherwise
  * @delayed_status: true when gadget driver asks for delayed status
@@ -1037,6 +1038,7 @@ struct dwc3_scratchpad_array {
  *	1	- utmi_l1_suspend_n
  * @is_fpga: true when we are using the FPGA board
  * @pending_events: true when we have pending IRQs to be handled
+ * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
  * @pullups_connected: true when Run/Stop bit is set
  * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
  * @three_stage_setup: set if we perform a three phase setup
@@ -1079,6 +1081,11 @@ struct dwc3_scratchpad_array {
  * @dis_split_quirk: set to disable split boundary.
  * @imod_interval: set the interrupt moderation interval in 250ns
  *			increments or 0 to disable.
+ * @max_cfg_eps: current max number of IN eps used across all USB configs.
+ * @last_fifo_depth: last fifo depth used to determine next fifo ram start
+ *		     address.
+ * @num_ep_resized: carries the current number endpoints which have had its tx
+ *		    fifo resized.
  */
 struct dwc3 {
 	struct work_struct	drd_work;
@@ -1233,6 +1240,7 @@ struct dwc3 {
 	u8			rx_max_burst_prd;
 	u8			tx_thr_num_pkt_prd;
 	u8			tx_max_burst_prd;
+	u8			tx_fifo_resize_max_num;
 
 	const char		*hsphy_interface;
 
@@ -1246,6 +1254,7 @@ struct dwc3 {
 	unsigned		is_utmi_l1_suspend:1;
 	unsigned		is_fpga:1;
 	unsigned		pending_events:1;
+	unsigned		do_fifo_resize:1;
 	unsigned		pullups_connected:1;
 	unsigned		setup_packet_pending:1;
 	unsigned		three_stage_setup:1;
@@ -1281,6 +1290,10 @@ struct dwc3 {
 	unsigned		dis_split_quirk:1;
 
 	u16			imod_interval;
+
+	int			max_cfg_eps;
+	int			last_fifo_depth;
+	int			num_ep_resized;
 };
 
 #define INCRX_BURST_MODE 0
@@ -1512,6 +1525,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
 		struct dwc3_gadget_ep_cmd_params *params);
 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
 		u32 param);
+void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc);
 #else
 static inline int dwc3_gadget_init(struct dwc3 *dwc)
 { return 0; }
@@ -1531,6 +1545,8 @@ static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
 		int cmd, u32 param)
 { return 0; }
+static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
+{ }
 #endif
 
 #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 3cd2942..d28d085 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -619,6 +619,8 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 		return -EINVAL;
 
 	case USB_STATE_ADDRESS:
+		dwc3_gadget_clear_tx_fifos(dwc);
+
 		ret = dwc3_ep0_delegate_req(dwc, ctrl);
 		/* if the cfg matches and the cfg is non zero */
 		if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index af6d7f1..e56f1a6 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -632,6 +632,187 @@ static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
 		bool interrupt);
 
 /**
+ * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
+ * @dwc: pointer to the DWC3 context
+ * @nfifos: number of fifos to calculate for
+ *
+ * Calculates the size value based on the equation below:
+ *
+ * DWC3 revision 280A and prior:
+ * fifo_size = mult * (max_packet / mdwidth) + 1;
+ *
+ * DWC3 revision 290A and onwards:
+ * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
+ *
+ * The max packet size is set to 1024, as the txfifo requirements mainly apply
+ * to super speed USB use cases.  However, it is safe to overestimate the fifo
+ * allocations for other scenarios, i.e. high speed USB.
+ */
+static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
+{
+	int max_packet = 1024;
+	int fifo_size;
+	int mdwidth;
+
+	mdwidth = dwc3_mdwidth(dwc);
+
+	/* MDWIDTH is represented in bits, we need it in bytes */
+	mdwidth >>= 3;
+
+	if (DWC3_VER_IS_PRIOR(DWC3, 290A))
+		fifo_size = mult * (max_packet / mdwidth) + 1;
+	else
+		fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
+	return fifo_size;
+}
+
+/**
+ * dwc3_gadget_clear_tx_fifo_size - Clears txfifo allocation
+ * @dwc: pointer to the DWC3 context
+ *
+ * Iterates through all the endpoint registers and clears the previous txfifo
+ * allocations.
+ */
+void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
+{
+	struct dwc3_ep *dep;
+	int fifo_depth;
+	int size;
+	int num;
+
+	if (!dwc->do_fifo_resize)
+		return;
+
+	/* Read ep0IN related TXFIFO size */
+	dep = dwc->eps[1];
+	size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+	if (DWC3_IP_IS(DWC3))
+		fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
+	else
+		fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
+
+	dwc->last_fifo_depth = fifo_depth;
+	/* Clear existing TXFIFO for all IN eps except ep0 */
+	for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
+	     num += 2) {
+		dep = dwc->eps[num];
+		/* Don't change TXFRAMNUM on usb31 version */
+		size = DWC3_IP_IS(DWC3) ? 0 :
+			dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
+				   DWC31_GTXFIFOSIZ_TXFRAMNUM;
+
+		dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
+	}
+	dwc->num_ep_resized = 0;
+}
+
+/*
+ * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
+ * @dwc: pointer to our context structure
+ *
+ * This function will a best effort FIFO allocation in order
+ * to improve FIFO usage and throughput, while still allowing
+ * us to enable as many endpoints as possible.
+ *
+ * Keep in mind that this operation will be highly dependent
+ * on the configured size for RAM1 - which contains TxFifo -,
+ * the amount of endpoints enabled on coreConsultant tool, and
+ * the width of the Master Bus.
+ *
+ * In general, FIFO depths are represented with the following equation:
+ *
+ * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
+ *
+ * In conjunction with dwc3_gadget_check_config(), this resizing logic will
+ * ensure that all endpoints will have enough internal memory for one max
+ * packet per endpoint.
+ */
+static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
+{
+	struct dwc3 *dwc = dep->dwc;
+	int fifo_0_start;
+	int ram1_depth;
+	int fifo_size;
+	int min_depth;
+	int num_in_ep;
+	int remaining;
+	int num_fifos = 1;
+	int fifo;
+	int tmp;
+
+	if (!dwc->do_fifo_resize)
+		return 0;
+
+	/* resize IN endpoints except ep0 */
+	if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
+		return 0;
+
+	ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+
+	if ((dep->endpoint.maxburst > 1 &&
+	     usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
+	    usb_endpoint_xfer_isoc(dep->endpoint.desc))
+		num_fifos = 3;
+
+	if (dep->endpoint.maxburst > 6 &&
+	    usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31))
+		num_fifos = dwc->tx_fifo_resize_max_num;
+
+	/* FIFO size for a single buffer */
+	fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
+
+	/* Calculate the number of remaining EPs w/o any FIFO */
+	num_in_ep = dwc->max_cfg_eps;
+	num_in_ep -= dwc->num_ep_resized;
+
+	/* Reserve at least one FIFO for the number of IN EPs */
+	min_depth = num_in_ep * (fifo + 1);
+	remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
+	remaining = max_t(int, 0, remaining);
+	/*
+	 * We've already reserved 1 FIFO per EP, so check what we can fit in
+	 * addition to it.  If there is not enough remaining space, allocate
+	 * all the remaining space to the EP.
+	 */
+	fifo_size = (num_fifos - 1) * fifo;
+	if (remaining < fifo_size)
+		fifo_size = remaining;
+
+	fifo_size += fifo;
+	/* Last increment according to the TX FIFO size equation */
+	fifo_size++;
+
+	/* Check if TXFIFOs start at non-zero addr */
+	tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+	fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
+
+	fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
+	if (DWC3_IP_IS(DWC3))
+		dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
+	else
+		dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
+
+	/* Check fifo size allocation doesn't exceed available RAM size. */
+	if (dwc->last_fifo_depth >= ram1_depth) {
+		dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
+			dwc->last_fifo_depth, ram1_depth,
+			dep->endpoint.name, fifo_size);
+		if (DWC3_IP_IS(DWC3))
+			fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
+		else
+			fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
+
+		dwc->last_fifo_depth -= fifo_size;
+		return -ENOMEM;
+	}
+
+	dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
+	dwc->num_ep_resized++;
+
+	return 0;
+}
+
+/**
  * __dwc3_gadget_ep_enable - initializes a hw endpoint
  * @dep: endpoint to be initialized
  * @action: one of INIT, MODIFY or RESTORE
@@ -648,6 +829,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
 	int			ret;
 
 	if (!(dep->flags & DWC3_EP_ENABLED)) {
+		ret = dwc3_gadget_resize_tx_fifos(dep);
+		if (ret)
+			return ret;
+
 		ret = dwc3_gadget_start_config(dep);
 		if (ret)
 			return ret;
@@ -2498,6 +2683,7 @@ static int dwc3_gadget_stop(struct usb_gadget *g)
 
 	spin_lock_irqsave(&dwc->lock, flags);
 	dwc->gadget_driver	= NULL;
+	dwc->max_cfg_eps = 0;
 	spin_unlock_irqrestore(&dwc->lock, flags);
 
 	free_irq(dwc->irq_gadget, dwc->ev_buf);
@@ -2585,6 +2771,51 @@ static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
 	return ret;
 }
 
+/**
+ * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
+ * @g: pointer to the USB gadget
+ *
+ * Used to record the maximum number of endpoints being used in a USB composite
+ * device. (across all configurations)  This is to be used in the calculation
+ * of the TXFIFO sizes when resizing internal memory for individual endpoints.
+ * It will help ensured that the resizing logic reserves enough space for at
+ * least one max packet.
+ */
+static int dwc3_gadget_check_config(struct usb_gadget *g)
+{
+	struct dwc3 *dwc = gadget_to_dwc(g);
+	struct usb_ep *ep;
+	int fifo_size = 0;
+	int ram1_depth;
+	int ep_num = 0;
+
+	if (!dwc->do_fifo_resize)
+		return 0;
+
+	list_for_each_entry(ep, &g->ep_list, ep_list) {
+		/* Only interested in the IN endpoints */
+		if (ep->claimed && (ep->address & USB_DIR_IN))
+			ep_num++;
+	}
+
+	if (ep_num <= dwc->max_cfg_eps)
+		return 0;
+
+	/* Update the max number of eps in the composition */
+	dwc->max_cfg_eps = ep_num;
+
+	fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
+	/* Based on the equation, increment by one for every ep */
+	fifo_size += dwc->max_cfg_eps;
+
+	/* Check if we can fit a single fifo per endpoint */
+	ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+	if (fifo_size > ram1_depth)
+		return -ENOMEM;
+
+	return 0;
+}
+
 static const struct usb_gadget_ops dwc3_gadget_ops = {
 	.get_frame		= dwc3_gadget_get_frame,
 	.wakeup			= dwc3_gadget_wakeup,
@@ -2596,6 +2827,7 @@ static const struct usb_gadget_ops dwc3_gadget_ops = {
 	.udc_set_ssp_rate	= dwc3_gadget_set_ssp_rate,
 	.get_config_params	= dwc3_gadget_config_params,
 	.vbus_draw		= dwc3_gadget_vbus_draw,
+	.check_config		= dwc3_gadget_check_config,
 };
 
 /* -------------------------------------------------------------------------- */
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 18+ messages in thread

* [PATCH v14 4/6] of: Add stub for of_add_property()
  2021-07-10  9:13 [PATCH v14 0/6] Re-introduce TX FIFO resize for larger EP bursting Wesley Cheng
                   ` (2 preceding siblings ...)
  2021-07-10  9:13 ` [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements Wesley Cheng
@ 2021-07-10  9:13 ` Wesley Cheng
  2021-07-10  9:13 ` [PATCH v14 5/6] usb: dwc3: dwc3-qcom: Enable tx-fifo-resize property by default Wesley Cheng
  2021-07-10  9:13 ` [PATCH v14 6/6] dt-bindings: usb: dwc3: Update dwc3 TX fifo properties Wesley Cheng
  5 siblings, 0 replies; 18+ messages in thread
From: Wesley Cheng @ 2021-07-10  9:13 UTC (permalink / raw)
  To: balbi, gregkh, agross, bjorn.andersson, robh+dt, frowand.list
  Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree, jackp, Wesley Cheng

If building with OF Kconfig disabled, this can lead to errors for
drivers utilizing of_add_property().  Add a stub for the add API, as
it exists for the remove variant as well, and to avoid compliation
issues.  Also, export this API so that it can be used by modules.

Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
---
 drivers/of/base.c  | 1 +
 include/linux/of.h | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/of/base.c b/drivers/of/base.c
index 48e941f..5883d63 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1821,6 +1821,7 @@ int of_add_property(struct device_node *np, struct property *prop)
 
 	return rc;
 }
+EXPORT_SYMBOL_GPL(of_add_property);
 
 int __of_remove_property(struct device_node *np, struct property *prop)
 {
diff --git a/include/linux/of.h b/include/linux/of.h
index 9c2e71e..0e786b60 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -946,6 +946,11 @@ static inline int of_machine_is_compatible(const char *compat)
 	return 0;
 }
 
+static inline int of_add_property(struct device_node *np, struct property *prop)
+{
+	return 0;
+}
+
 static inline int of_remove_property(struct device_node *np, struct property *prop)
 {
 	return 0;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 18+ messages in thread

* [PATCH v14 5/6] usb: dwc3: dwc3-qcom: Enable tx-fifo-resize property by default
  2021-07-10  9:13 [PATCH v14 0/6] Re-introduce TX FIFO resize for larger EP bursting Wesley Cheng
                   ` (3 preceding siblings ...)
  2021-07-10  9:13 ` [PATCH v14 4/6] of: Add stub for of_add_property() Wesley Cheng
@ 2021-07-10  9:13 ` Wesley Cheng
  2021-07-10  9:13 ` [PATCH v14 6/6] dt-bindings: usb: dwc3: Update dwc3 TX fifo properties Wesley Cheng
  5 siblings, 0 replies; 18+ messages in thread
From: Wesley Cheng @ 2021-07-10  9:13 UTC (permalink / raw)
  To: balbi, gregkh, agross, bjorn.andersson, robh+dt, frowand.list
  Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree, jackp, Wesley Cheng

In order to take advantage of the TX fifo resizing logic, manually add
these properties to the DWC3 child node by default.  This will allow
the DWC3 gadget to resize the TX fifos for the IN endpoints, which
help with performance.

Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
---
 drivers/usb/dwc3/dwc3-qcom.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 49e6ca9..2223b59 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -645,6 +645,7 @@ static int dwc3_qcom_of_register_core(struct platform_device *pdev)
 	struct dwc3_qcom	*qcom = platform_get_drvdata(pdev);
 	struct device_node	*np = pdev->dev.of_node, *dwc3_np;
 	struct device		*dev = &pdev->dev;
+	struct property		*prop;
 	int			ret;
 
 	dwc3_np = of_get_compatible_child(np, "snps,dwc3");
@@ -653,6 +654,20 @@ static int dwc3_qcom_of_register_core(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
+	prop = devm_kzalloc(dev, sizeof(*prop), GFP_KERNEL);
+	if (!prop) {
+		ret = -ENOMEM;
+		dev_err(dev, "unable to allocate memory for property\n");
+		goto node_put;
+	}
+
+	prop->name = "tx-fifo-resize";
+	ret = of_add_property(dwc3_np, prop);
+	if (ret) {
+		dev_err(dev, "unable to add property\n");
+		goto node_put;
+	}
+
 	ret = of_platform_populate(np, NULL, NULL, dev);
 	if (ret) {
 		dev_err(dev, "failed to register dwc3 core - %d\n", ret);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 18+ messages in thread

* [PATCH v14 6/6] dt-bindings: usb: dwc3: Update dwc3 TX fifo properties
  2021-07-10  9:13 [PATCH v14 0/6] Re-introduce TX FIFO resize for larger EP bursting Wesley Cheng
                   ` (4 preceding siblings ...)
  2021-07-10  9:13 ` [PATCH v14 5/6] usb: dwc3: dwc3-qcom: Enable tx-fifo-resize property by default Wesley Cheng
@ 2021-07-10  9:13 ` Wesley Cheng
  5 siblings, 0 replies; 18+ messages in thread
From: Wesley Cheng @ 2021-07-10  9:13 UTC (permalink / raw)
  To: balbi, gregkh, agross, bjorn.andersson, robh+dt, frowand.list
  Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree, jackp, Wesley Cheng

Update the tx-fifo-resize property with a better description, while
adding the tx-fifo-max-num, which is a new parameter allowing
adjustments for the maximum number of packets the txfifo resizing logic
can account for while resizing the endpoints.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
---
 Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
index 41416fb..078fb78 100644
--- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
@@ -289,10 +289,21 @@ properties:
     maximum: 16
 
   tx-fifo-resize:
-    description: Determines if the FIFO *has* to be reallocated
-    deprecated: true
+    description: Determines if the TX fifos can be dynamically resized depending
+      on the number of IN endpoints used and if bursting is supported.  This
+      may help improve bandwidth on platforms with higher system latencies, as
+      increased fifo space allows for the controller to prefetch data into its
+      internal memory.
     type: boolean
 
+  tx-fifo-max-num:
+    description: Specifies the max number of packets the txfifo resizing logic
+      can account for when higher endpoint bursting is used. (bMaxBurst > 6) The
+      higher the number, the more fifo space the txfifo resizing logic will
+      allocate for that endpoint.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 3
+
   snps,incr-burst-type-adjustment:
     description:
       Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
  2021-07-10  9:13 ` [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements Wesley Cheng
@ 2021-07-12 23:38   ` Thinh Nguyen
  2021-07-13  8:39     ` Felipe Balbi
  2021-07-14  2:59     ` Thinh Nguyen
  0 siblings, 2 replies; 18+ messages in thread
From: Thinh Nguyen @ 2021-07-12 23:38 UTC (permalink / raw)
  To: Wesley Cheng, balbi, gregkh, agross, bjorn.andersson, robh+dt,
	frowand.list
  Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree, jackp

Hi,

Wesley Cheng wrote:
> Some devices have USB compositions which may require multiple endpoints
> that support EP bursting.  HW defined TX FIFO sizes may not always be
> sufficient for these compositions.  By utilizing flexible TX FIFO
> allocation, this allows for endpoints to request the required FIFO depth to
> achieve higher bandwidth.  With some higher bMaxBurst configurations, using
> a larger TX FIFO size results in better TX throughput.
> 
> By introducing the check_config() callback, the resizing logic can fetch
> the maximum number of endpoints used in the USB composition (can contain
> multiple configurations), which helps ensure that the resizing logic can
> fulfill the configuration(s), or return an error to the gadget layer
> otherwise during bind time.
> 
> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
> ---
>  drivers/usb/dwc3/core.c   |  15 +++
>  drivers/usb/dwc3/core.h   |  16 ++++
>  drivers/usb/dwc3/ep0.c    |   2 +
>  drivers/usb/dwc3/gadget.c | 232 ++++++++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 265 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index ba74ad7..b194aecd 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -1267,6 +1267,7 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>  	u8			rx_max_burst_prd;
>  	u8			tx_thr_num_pkt_prd;
>  	u8			tx_max_burst_prd;
> +	u8			tx_fifo_resize_max_num;
>  	const char		*usb_psy_name;
>  	int			ret;
>  
> @@ -1282,6 +1283,13 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>  	 */
>  	hird_threshold = 12;
>  
> +	/*
> +	 * default to a TXFIFO size large enough to fit 6 max packets.  This
> +	 * allows for systems with larger bus latencies to have some headroom
> +	 * for endpoints that have a large bMaxBurst value.
> +	 */
> +	tx_fifo_resize_max_num = 6;
> +
>  	dwc->maximum_speed = usb_get_maximum_speed(dev);
>  	dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
>  	dwc->dr_mode = usb_get_dr_mode(dev);
> @@ -1325,6 +1333,11 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>  				&tx_thr_num_pkt_prd);
>  	device_property_read_u8(dev, "snps,tx-max-burst-prd",
>  				&tx_max_burst_prd);
> +	dwc->do_fifo_resize = device_property_read_bool(dev,
> +							"tx-fifo-resize");
> +	if (dwc->do_fifo_resize)
> +		device_property_read_u8(dev, "tx-fifo-max-num",
> +					&tx_fifo_resize_max_num);

Why is this check here? The dwc->tx_fifo_resize_max_num should store
whatever property the user sets. Whether the driver wants to use this
property should depend on "dwc->do_fifo_resize". Also why don't we have
"snps," prefix to be consistent with the other properties?

Can we enforce to a single property? If the designer wants to enable
this feature, he/she can to provide the tx-fifo-max-num. This would
simplify the driver a bit. Since this is to optimize for performance,
the user should know/want/test the specific value if they want to set
for their setup and not hoping that the default setting not break their
setup. So we can remove the "do_fifo_resize" property and just check
whether tx_fifo_resize_max_num is set.

>  
>  	dwc->disable_scramble_quirk = device_property_read_bool(dev,
>  				"snps,disable_scramble_quirk");
> @@ -1390,6 +1403,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>  	dwc->tx_max_burst_prd = tx_max_burst_prd;
>  
>  	dwc->imod_interval = 0;
> +
> +	dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;

See comment above

>  }
>  
>  /* check whether the core supports IMOD */
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index dccdf13..735e9be 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -1023,6 +1023,7 @@ struct dwc3_scratchpad_array {
>   * @rx_max_burst_prd: max periodic ESS receive burst size
>   * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
>   * @tx_max_burst_prd: max periodic ESS transmit burst size
> + * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize
>   * @hsphy_interface: "utmi" or "ulpi"
>   * @connected: true when we're connected to a host, false otherwise
>   * @delayed_status: true when gadget driver asks for delayed status
> @@ -1037,6 +1038,7 @@ struct dwc3_scratchpad_array {
>   *	1	- utmi_l1_suspend_n
>   * @is_fpga: true when we are using the FPGA board
>   * @pending_events: true when we have pending IRQs to be handled
> + * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
>   * @pullups_connected: true when Run/Stop bit is set
>   * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
>   * @three_stage_setup: set if we perform a three phase setup
> @@ -1079,6 +1081,11 @@ struct dwc3_scratchpad_array {
>   * @dis_split_quirk: set to disable split boundary.
>   * @imod_interval: set the interrupt moderation interval in 250ns
>   *			increments or 0 to disable.
> + * @max_cfg_eps: current max number of IN eps used across all USB configs.
> + * @last_fifo_depth: last fifo depth used to determine next fifo ram start
> + *		     address.
> + * @num_ep_resized: carries the current number endpoints which have had its tx
> + *		    fifo resized.
>   */
>  struct dwc3 {
>  	struct work_struct	drd_work;
> @@ -1233,6 +1240,7 @@ struct dwc3 {
>  	u8			rx_max_burst_prd;
>  	u8			tx_thr_num_pkt_prd;
>  	u8			tx_max_burst_prd;
> +	u8			tx_fifo_resize_max_num;
>  
>  	const char		*hsphy_interface;
>  
> @@ -1246,6 +1254,7 @@ struct dwc3 {
>  	unsigned		is_utmi_l1_suspend:1;
>  	unsigned		is_fpga:1;
>  	unsigned		pending_events:1;
> +	unsigned		do_fifo_resize:1;
>  	unsigned		pullups_connected:1;
>  	unsigned		setup_packet_pending:1;
>  	unsigned		three_stage_setup:1;
> @@ -1281,6 +1290,10 @@ struct dwc3 {
>  	unsigned		dis_split_quirk:1;
>  
>  	u16			imod_interval;
> +
> +	int			max_cfg_eps;
> +	int			last_fifo_depth;
> +	int			num_ep_resized;
>  };
>  
>  #define INCRX_BURST_MODE 0
> @@ -1512,6 +1525,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
>  		struct dwc3_gadget_ep_cmd_params *params);
>  int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
>  		u32 param);
> +void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc);
>  #else
>  static inline int dwc3_gadget_init(struct dwc3 *dwc)
>  { return 0; }
> @@ -1531,6 +1545,8 @@ static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
>  static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
>  		int cmd, u32 param)
>  { return 0; }
> +static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
> +{ }
>  #endif
>  
>  #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
> diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
> index 3cd2942..d28d085 100644
> --- a/drivers/usb/dwc3/ep0.c
> +++ b/drivers/usb/dwc3/ep0.c
> @@ -619,6 +619,8 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
>  		return -EINVAL;
>  
>  	case USB_STATE_ADDRESS:
> +		dwc3_gadget_clear_tx_fifos(dwc);
> +
>  		ret = dwc3_ep0_delegate_req(dwc, ctrl);
>  		/* if the cfg matches and the cfg is non zero */
>  		if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
> diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
> index af6d7f1..e56f1a6 100644
> --- a/drivers/usb/dwc3/gadget.c
> +++ b/drivers/usb/dwc3/gadget.c
> @@ -632,6 +632,187 @@ static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
>  		bool interrupt);
>  
>  /**
> + * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
> + * @dwc: pointer to the DWC3 context
> + * @nfifos: number of fifos to calculate for
> + *
> + * Calculates the size value based on the equation below:
> + *
> + * DWC3 revision 280A and prior:
> + * fifo_size = mult * (max_packet / mdwidth) + 1;
> + *
> + * DWC3 revision 290A and onwards:
> + * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
> + *
> + * The max packet size is set to 1024, as the txfifo requirements mainly apply
> + * to super speed USB use cases.  However, it is safe to overestimate the fifo
> + * allocations for other scenarios, i.e. high speed USB.
> + */
> +static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
> +{
> +	int max_packet = 1024;
> +	int fifo_size;
> +	int mdwidth;
> +
> +	mdwidth = dwc3_mdwidth(dwc);
> +
> +	/* MDWIDTH is represented in bits, we need it in bytes */
> +	mdwidth >>= 3;
> +
> +	if (DWC3_VER_IS_PRIOR(DWC3, 290A))
> +		fifo_size = mult * (max_packet / mdwidth) + 1;
> +	else
> +		fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
> +	return fifo_size;
> +}
> +
> +/**
> + * dwc3_gadget_clear_tx_fifo_size - Clears txfifo allocation
> + * @dwc: pointer to the DWC3 context
> + *
> + * Iterates through all the endpoint registers and clears the previous txfifo
> + * allocations.
> + */
> +void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
> +{
> +	struct dwc3_ep *dep;
> +	int fifo_depth;
> +	int size;
> +	int num;
> +
> +	if (!dwc->do_fifo_resize)
> +		return;
> +
> +	/* Read ep0IN related TXFIFO size */
> +	dep = dwc->eps[1];
> +	size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
> +	if (DWC3_IP_IS(DWC3))
> +		fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
> +	else
> +		fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
> +
> +	dwc->last_fifo_depth = fifo_depth;
> +	/* Clear existing TXFIFO for all IN eps except ep0 */
> +	for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
> +	     num += 2) {
> +		dep = dwc->eps[num];
> +		/* Don't change TXFRAMNUM on usb31 version */
> +		size = DWC3_IP_IS(DWC3) ? 0 :
> +			dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
> +				   DWC31_GTXFIFOSIZ_TXFRAMNUM;
> +
> +		dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
> +	}
> +	dwc->num_ep_resized = 0;
> +}
> +
> +/*
> + * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
> + * @dwc: pointer to our context structure
> + *
> + * This function will a best effort FIFO allocation in order
> + * to improve FIFO usage and throughput, while still allowing
> + * us to enable as many endpoints as possible.
> + *
> + * Keep in mind that this operation will be highly dependent
> + * on the configured size for RAM1 - which contains TxFifo -,
> + * the amount of endpoints enabled on coreConsultant tool, and
> + * the width of the Master Bus.
> + *
> + * In general, FIFO depths are represented with the following equation:
> + *
> + * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
> + *
> + * In conjunction with dwc3_gadget_check_config(), this resizing logic will
> + * ensure that all endpoints will have enough internal memory for one max
> + * packet per endpoint.
> + */
> +static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
> +{
> +	struct dwc3 *dwc = dep->dwc;
> +	int fifo_0_start;
> +	int ram1_depth;
> +	int fifo_size;
> +	int min_depth;
> +	int num_in_ep;
> +	int remaining;
> +	int num_fifos = 1;
> +	int fifo;
> +	int tmp;
> +
> +	if (!dwc->do_fifo_resize)
> +		return 0;
> +
> +	/* resize IN endpoints except ep0 */
> +	if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
> +		return 0;

> +
> +	ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
> +
> +	if ((dep->endpoint.maxburst > 1 &&
> +	     usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
> +	    usb_endpoint_xfer_isoc(dep->endpoint.desc))
> +		num_fifos = 3;
> +
> +	if (dep->endpoint.maxburst > 6 &&
> +	    usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31))
> +		num_fifos = dwc->tx_fifo_resize_max_num;

Why only bulk? Isoc should be at least equal or more than bulk.
Also, make this applicable to DWC_usb32 also.

> +
> +	/* FIFO size for a single buffer */
> +	fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
> +
> +	/* Calculate the number of remaining EPs w/o any FIFO */
> +	num_in_ep = dwc->max_cfg_eps;
> +	num_in_ep -= dwc->num_ep_resized;

Does this calculation account for multiple alt-setting interfaces?

> +
> +	/* Reserve at least one FIFO for the number of IN EPs */
> +	min_depth = num_in_ep * (fifo + 1);
> +	remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
> +	remaining = max_t(int, 0, remaining);

Add blank line

> +	/*
> +	 * We've already reserved 1 FIFO per EP, so check what we can fit in
> +	 * addition to it.  If there is not enough remaining space, allocate
> +	 * all the remaining space to the EP.
> +	 */
> +	fifo_size = (num_fifos - 1) * fifo;
> +	if (remaining < fifo_size)
> +		fifo_size = remaining;
> +
> +	fifo_size += fifo;
> +	/* Last increment according to the TX FIFO size equation */
> +	fifo_size++;
> +
> +	/* Check if TXFIFOs start at non-zero addr */
> +	tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
> +	fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
> +
> +	fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
> +	if (DWC3_IP_IS(DWC3))
> +		dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
> +	else
> +		dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
> +
> +	/* Check fifo size allocation doesn't exceed available RAM size. */
> +	if (dwc->last_fifo_depth >= ram1_depth) {
> +		dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
> +			dwc->last_fifo_depth, ram1_depth,
> +			dep->endpoint.name, fifo_size);
> +		if (DWC3_IP_IS(DWC3))
> +			fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
> +		else
> +			fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
> +
> +		dwc->last_fifo_depth -= fifo_size;
> +		return -ENOMEM;
> +	}
> +
> +	dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
> +	dwc->num_ep_resized++;
> +
> +	return 0;
> +}
> +
> +/**
>   * __dwc3_gadget_ep_enable - initializes a hw endpoint
>   * @dep: endpoint to be initialized
>   * @action: one of INIT, MODIFY or RESTORE
> @@ -648,6 +829,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
>  	int			ret;
>  
>  	if (!(dep->flags & DWC3_EP_ENABLED)) {
> +		ret = dwc3_gadget_resize_tx_fifos(dep);
> +		if (ret)
> +			return ret;
> +
>  		ret = dwc3_gadget_start_config(dep);
>  		if (ret)
>  			return ret;
> @@ -2498,6 +2683,7 @@ static int dwc3_gadget_stop(struct usb_gadget *g)
>  
>  	spin_lock_irqsave(&dwc->lock, flags);
>  	dwc->gadget_driver	= NULL;
> +	dwc->max_cfg_eps = 0;
>  	spin_unlock_irqrestore(&dwc->lock, flags);
>  
>  	free_irq(dwc->irq_gadget, dwc->ev_buf);
> @@ -2585,6 +2771,51 @@ static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
>  	return ret;
>  }
>  
> +/**
> + * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
> + * @g: pointer to the USB gadget
> + *
> + * Used to record the maximum number of endpoints being used in a USB composite
> + * device. (across all configurations)  This is to be used in the calculation
> + * of the TXFIFO sizes when resizing internal memory for individual endpoints.
> + * It will help ensured that the resizing logic reserves enough space for at
> + * least one max packet.
> + */
> +static int dwc3_gadget_check_config(struct usb_gadget *g)
> +{
> +	struct dwc3 *dwc = gadget_to_dwc(g);
> +	struct usb_ep *ep;
> +	int fifo_size = 0;
> +	int ram1_depth;
> +	int ep_num = 0;
> +
> +	if (!dwc->do_fifo_resize)
> +		return 0;
> +
> +	list_for_each_entry(ep, &g->ep_list, ep_list) {
> +		/* Only interested in the IN endpoints */
> +		if (ep->claimed && (ep->address & USB_DIR_IN))
> +			ep_num++;
> +	}
> +
> +	if (ep_num <= dwc->max_cfg_eps)
> +		return 0;
> +
> +	/* Update the max number of eps in the composition */
> +	dwc->max_cfg_eps = ep_num;
> +
> +	fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
> +	/* Based on the equation, increment by one for every ep */
> +	fifo_size += dwc->max_cfg_eps;
> +
> +	/* Check if we can fit a single fifo per endpoint */
> +	ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
> +	if (fifo_size > ram1_depth)
> +		return -ENOMEM;
> +
> +	return 0;
> +}
> +
>  static const struct usb_gadget_ops dwc3_gadget_ops = {
>  	.get_frame		= dwc3_gadget_get_frame,
>  	.wakeup			= dwc3_gadget_wakeup,
> @@ -2596,6 +2827,7 @@ static const struct usb_gadget_ops dwc3_gadget_ops = {
>  	.udc_set_ssp_rate	= dwc3_gadget_set_ssp_rate,
>  	.get_config_params	= dwc3_gadget_config_params,
>  	.vbus_draw		= dwc3_gadget_vbus_draw,
> +	.check_config		= dwc3_gadget_check_config,
>  };
>  
>  /* -------------------------------------------------------------------------- */
> 

Btw, I'm a little busy at the moment and can't review all the
calculations in the patch in detail. I'll comment on what I can. Thanks
for the work and the patches.

BR,
Thinh

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
  2021-07-12 23:38   ` Thinh Nguyen
@ 2021-07-13  8:39     ` Felipe Balbi
  2021-07-14  2:58       ` Thinh Nguyen
  2021-07-14  3:10       ` Thinh Nguyen
  2021-07-14  2:59     ` Thinh Nguyen
  1 sibling, 2 replies; 18+ messages in thread
From: Felipe Balbi @ 2021-07-13  8:39 UTC (permalink / raw)
  To: Thinh Nguyen, Wesley Cheng, gregkh, agross, bjorn.andersson,
	robh+dt, frowand.list
  Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree, jackp

[-- Attachment #1: Type: text/plain, Size: 13470 bytes --]


Hi,

Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
> Wesley Cheng wrote:
>> Some devices have USB compositions which may require multiple endpoints
>> that support EP bursting.  HW defined TX FIFO sizes may not always be
>> sufficient for these compositions.  By utilizing flexible TX FIFO
>> allocation, this allows for endpoints to request the required FIFO depth to
>> achieve higher bandwidth.  With some higher bMaxBurst configurations, using
>> a larger TX FIFO size results in better TX throughput.
>> 
>> By introducing the check_config() callback, the resizing logic can fetch
>> the maximum number of endpoints used in the USB composition (can contain
>> multiple configurations), which helps ensure that the resizing logic can
>> fulfill the configuration(s), or return an error to the gadget layer
>> otherwise during bind time.
>> 
>> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
>> ---
>>  drivers/usb/dwc3/core.c   |  15 +++
>>  drivers/usb/dwc3/core.h   |  16 ++++
>>  drivers/usb/dwc3/ep0.c    |   2 +
>>  drivers/usb/dwc3/gadget.c | 232 ++++++++++++++++++++++++++++++++++++++++++++++
>>  4 files changed, 265 insertions(+)
>> 
>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>> index ba74ad7..b194aecd 100644
>> --- a/drivers/usb/dwc3/core.c
>> +++ b/drivers/usb/dwc3/core.c
>> @@ -1267,6 +1267,7 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>  	u8			rx_max_burst_prd;
>>  	u8			tx_thr_num_pkt_prd;
>>  	u8			tx_max_burst_prd;
>> +	u8			tx_fifo_resize_max_num;
>>  	const char		*usb_psy_name;
>>  	int			ret;
>>  
>> @@ -1282,6 +1283,13 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>  	 */
>>  	hird_threshold = 12;
>>  
>> +	/*
>> +	 * default to a TXFIFO size large enough to fit 6 max packets.  This
>> +	 * allows for systems with larger bus latencies to have some headroom
>> +	 * for endpoints that have a large bMaxBurst value.
>> +	 */
>> +	tx_fifo_resize_max_num = 6;
>> +
>>  	dwc->maximum_speed = usb_get_maximum_speed(dev);
>>  	dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
>>  	dwc->dr_mode = usb_get_dr_mode(dev);
>> @@ -1325,6 +1333,11 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>  				&tx_thr_num_pkt_prd);
>>  	device_property_read_u8(dev, "snps,tx-max-burst-prd",
>>  				&tx_max_burst_prd);
>> +	dwc->do_fifo_resize = device_property_read_bool(dev,
>> +							"tx-fifo-resize");
>> +	if (dwc->do_fifo_resize)
>> +		device_property_read_u8(dev, "tx-fifo-max-num",
>> +					&tx_fifo_resize_max_num);
>
> Why is this check here? The dwc->tx_fifo_resize_max_num should store
> whatever property the user sets. Whether the driver wants to use this

Ack!

> property should depend on "dwc->do_fifo_resize". Also why don't we have
> "snps," prefix to be consistent with the other properties?

Ack!

> Can we enforce to a single property? If the designer wants to enable
> this feature, he/she can to provide the tx-fifo-max-num. This would
> simplify the driver a bit. Since this is to optimize for performance,
> the user should know/want/test the specific value if they want to set
> for their setup and not hoping that the default setting not break their
> setup. So we can remove the "do_fifo_resize" property and just check
> whether tx_fifo_resize_max_num is set.

Ack!

All very valid points :-)

>> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
>> index dccdf13..735e9be 100644
>> --- a/drivers/usb/dwc3/core.h
>> +++ b/drivers/usb/dwc3/core.h
>> @@ -1023,6 +1023,7 @@ struct dwc3_scratchpad_array {
>>   * @rx_max_burst_prd: max periodic ESS receive burst size
>>   * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
>>   * @tx_max_burst_prd: max periodic ESS transmit burst size
>> + * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize
>>   * @hsphy_interface: "utmi" or "ulpi"
>>   * @connected: true when we're connected to a host, false otherwise
>>   * @delayed_status: true when gadget driver asks for delayed status
>> @@ -1037,6 +1038,7 @@ struct dwc3_scratchpad_array {
>>   *	1	- utmi_l1_suspend_n
>>   * @is_fpga: true when we are using the FPGA board
>>   * @pending_events: true when we have pending IRQs to be handled
>> + * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
>>   * @pullups_connected: true when Run/Stop bit is set
>>   * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
>>   * @three_stage_setup: set if we perform a three phase setup
>> @@ -1079,6 +1081,11 @@ struct dwc3_scratchpad_array {
>>   * @dis_split_quirk: set to disable split boundary.
>>   * @imod_interval: set the interrupt moderation interval in 250ns
>>   *			increments or 0 to disable.
>> + * @max_cfg_eps: current max number of IN eps used across all USB configs.
>> + * @last_fifo_depth: last fifo depth used to determine next fifo ram start
>> + *		     address.
>> + * @num_ep_resized: carries the current number endpoints which have had its tx
>> + *		    fifo resized.
>>   */
>>  struct dwc3 {
>>  	struct work_struct	drd_work;
>> @@ -1233,6 +1240,7 @@ struct dwc3 {
>>  	u8			rx_max_burst_prd;
>>  	u8			tx_thr_num_pkt_prd;
>>  	u8			tx_max_burst_prd;
>> +	u8			tx_fifo_resize_max_num;
>>  
>>  	const char		*hsphy_interface;
>>  
>> @@ -1246,6 +1254,7 @@ struct dwc3 {
>>  	unsigned		is_utmi_l1_suspend:1;
>>  	unsigned		is_fpga:1;
>>  	unsigned		pending_events:1;
>> +	unsigned		do_fifo_resize:1;
>>  	unsigned		pullups_connected:1;
>>  	unsigned		setup_packet_pending:1;
>>  	unsigned		three_stage_setup:1;
>> @@ -1281,6 +1290,10 @@ struct dwc3 {
>>  	unsigned		dis_split_quirk:1;
>>  
>>  	u16			imod_interval;
>> +
>> +	int			max_cfg_eps;
>> +	int			last_fifo_depth;
>> +	int			num_ep_resized;
>>  };
>>  
>>  #define INCRX_BURST_MODE 0
>> @@ -1512,6 +1525,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
>>  		struct dwc3_gadget_ep_cmd_params *params);
>>  int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
>>  		u32 param);
>> +void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc);
>>  #else
>>  static inline int dwc3_gadget_init(struct dwc3 *dwc)
>>  { return 0; }
>> @@ -1531,6 +1545,8 @@ static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
>>  static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
>>  		int cmd, u32 param)
>>  { return 0; }
>> +static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
>> +{ }
>>  #endif
>>  
>>  #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
>> diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
>> index 3cd2942..d28d085 100644
>> --- a/drivers/usb/dwc3/ep0.c
>> +++ b/drivers/usb/dwc3/ep0.c
>> @@ -619,6 +619,8 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
>>  		return -EINVAL;
>>  
>>  	case USB_STATE_ADDRESS:
>> +		dwc3_gadget_clear_tx_fifos(dwc);
>> +
>>  		ret = dwc3_ep0_delegate_req(dwc, ctrl);
>>  		/* if the cfg matches and the cfg is non zero */
>>  		if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
>> diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
>> index af6d7f1..e56f1a6 100644
>> --- a/drivers/usb/dwc3/gadget.c
>> +++ b/drivers/usb/dwc3/gadget.c
>> @@ -632,6 +632,187 @@ static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
>>  		bool interrupt);
>>  
>>  /**
>> + * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
>> + * @dwc: pointer to the DWC3 context
>> + * @nfifos: number of fifos to calculate for
>> + *
>> + * Calculates the size value based on the equation below:
>> + *
>> + * DWC3 revision 280A and prior:
>> + * fifo_size = mult * (max_packet / mdwidth) + 1;
>> + *
>> + * DWC3 revision 290A and onwards:
>> + * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
>> + *
>> + * The max packet size is set to 1024, as the txfifo requirements mainly apply
>> + * to super speed USB use cases.  However, it is safe to overestimate the fifo
>> + * allocations for other scenarios, i.e. high speed USB.
>> + */
>> +static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
>> +{
>> +	int max_packet = 1024;
>> +	int fifo_size;
>> +	int mdwidth;
>> +
>> +	mdwidth = dwc3_mdwidth(dwc);
>> +
>> +	/* MDWIDTH is represented in bits, we need it in bytes */
>> +	mdwidth >>= 3;
>> +
>> +	if (DWC3_VER_IS_PRIOR(DWC3, 290A))
>> +		fifo_size = mult * (max_packet / mdwidth) + 1;
>> +	else
>> +		fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
>> +	return fifo_size;
>> +}
>> +
>> +/**
>> + * dwc3_gadget_clear_tx_fifo_size - Clears txfifo allocation
>> + * @dwc: pointer to the DWC3 context
>> + *
>> + * Iterates through all the endpoint registers and clears the previous txfifo
>> + * allocations.
>> + */
>> +void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
>> +{
>> +	struct dwc3_ep *dep;
>> +	int fifo_depth;
>> +	int size;
>> +	int num;
>> +
>> +	if (!dwc->do_fifo_resize)
>> +		return;
>> +
>> +	/* Read ep0IN related TXFIFO size */
>> +	dep = dwc->eps[1];
>> +	size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
>> +	if (DWC3_IP_IS(DWC3))
>> +		fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
>> +	else
>> +		fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
>> +
>> +	dwc->last_fifo_depth = fifo_depth;
>> +	/* Clear existing TXFIFO for all IN eps except ep0 */
>> +	for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
>> +	     num += 2) {
>> +		dep = dwc->eps[num];
>> +		/* Don't change TXFRAMNUM on usb31 version */
>> +		size = DWC3_IP_IS(DWC3) ? 0 :
>> +			dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
>> +				   DWC31_GTXFIFOSIZ_TXFRAMNUM;
>> +
>> +		dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
>> +	}
>> +	dwc->num_ep_resized = 0;
>> +}
>> +
>> +/*
>> + * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
>> + * @dwc: pointer to our context structure
>> + *
>> + * This function will a best effort FIFO allocation in order
>> + * to improve FIFO usage and throughput, while still allowing
>> + * us to enable as many endpoints as possible.
>> + *
>> + * Keep in mind that this operation will be highly dependent
>> + * on the configured size for RAM1 - which contains TxFifo -,
>> + * the amount of endpoints enabled on coreConsultant tool, and
>> + * the width of the Master Bus.
>> + *
>> + * In general, FIFO depths are represented with the following equation:
>> + *
>> + * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
>> + *
>> + * In conjunction with dwc3_gadget_check_config(), this resizing logic will
>> + * ensure that all endpoints will have enough internal memory for one max
>> + * packet per endpoint.
>> + */
>> +static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
>> +{
>> +	struct dwc3 *dwc = dep->dwc;
>> +	int fifo_0_start;
>> +	int ram1_depth;
>> +	int fifo_size;
>> +	int min_depth;
>> +	int num_in_ep;
>> +	int remaining;
>> +	int num_fifos = 1;
>> +	int fifo;
>> +	int tmp;
>> +
>> +	if (!dwc->do_fifo_resize)
>> +		return 0;
>> +
>> +	/* resize IN endpoints except ep0 */
>> +	if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
>> +		return 0;
>
>> +
>> +	ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
>> +
>> +	if ((dep->endpoint.maxburst > 1 &&
>> +	     usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
>> +	    usb_endpoint_xfer_isoc(dep->endpoint.desc))
>> +		num_fifos = 3;
>> +
>> +	if (dep->endpoint.maxburst > 6 &&
>> +	    usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31))
>> +		num_fifos = dwc->tx_fifo_resize_max_num;
>
> Why only bulk? Isoc should be at least equal or more than bulk.
> Also, make this applicable to DWC_usb32 also.

this should be applicable to all DWC3 versions, no? dwc3, 31 and 32.

>> @@ -648,6 +829,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
>>  	int			ret;
>>  
>>  	if (!(dep->flags & DWC3_EP_ENABLED)) {
>> +		ret = dwc3_gadget_resize_tx_fifos(dep);
>> +		if (ret)
>> +			return ret;
>> +
>>  		ret = dwc3_gadget_start_config(dep);
>>  		if (ret)
>>  			return ret;
>> @@ -2498,6 +2683,7 @@ static int dwc3_gadget_stop(struct usb_gadget *g)
>>  
>>  	spin_lock_irqsave(&dwc->lock, flags);
>>  	dwc->gadget_driver	= NULL;
>> +	dwc->max_cfg_eps = 0;
>>  	spin_unlock_irqrestore(&dwc->lock, flags);
>>  
>>  	free_irq(dwc->irq_gadget, dwc->ev_buf);
>> @@ -2585,6 +2771,51 @@ static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
>>  	return ret;
>>  }
>>  
>> +/**
>> + * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
>> + * @g: pointer to the USB gadget
>> + *
>> + * Used to record the maximum number of endpoints being used in a USB composite
>> + * device. (across all configurations)  This is to be used in the calculation
>> + * of the TXFIFO sizes when resizing internal memory for individual endpoints.
>> + * It will help ensured that the resizing logic reserves enough space for at
>> + * least one max packet.
>> + */
>> +static int dwc3_gadget_check_config(struct usb_gadget *g)

Might be better to pass the actual config being used. And, instead of
check_config, perhaps validate_config is a little more fitting.

-- 
balbi

[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
  2021-07-13  8:39     ` Felipe Balbi
@ 2021-07-14  2:58       ` Thinh Nguyen
  2021-07-14  3:10       ` Thinh Nguyen
  1 sibling, 0 replies; 18+ messages in thread
From: Thinh Nguyen @ 2021-07-14  2:58 UTC (permalink / raw)
  To: Felipe Balbi, Thinh Nguyen, Wesley Cheng, gregkh, agross,
	bjorn.andersson, robh+dt, frowand.list
  Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree, jackp

Felipe Balbi wrote:
> 
> Hi,
> 
> Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
>> Wesley Cheng wrote:
>>> Some devices have USB compositions which may require multiple endpoints
>>> that support EP bursting.  HW defined TX FIFO sizes may not always be
>>> sufficient for these compositions.  By utilizing flexible TX FIFO
>>> allocation, this allows for endpoints to request the required FIFO depth to
>>> achieve higher bandwidth.  With some higher bMaxBurst configurations, using
>>> a larger TX FIFO size results in better TX throughput.
>>>
>>> By introducing the check_config() callback, the resizing logic can fetch
>>> the maximum number of endpoints used in the USB composition (can contain
>>> multiple configurations), which helps ensure that the resizing logic can
>>> fulfill the configuration(s), or return an error to the gadget layer
>>> otherwise during bind time.
>>>
>>> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
>>> ---
>>>  drivers/usb/dwc3/core.c   |  15 +++
>>>  drivers/usb/dwc3/core.h   |  16 ++++
>>>  drivers/usb/dwc3/ep0.c    |   2 +
>>>  drivers/usb/dwc3/gadget.c | 232 ++++++++++++++++++++++++++++++++++++++++++++++
>>>  4 files changed, 265 insertions(+)
>>>

<snip>

>>> +/*
>>> + * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
>>> + * @dwc: pointer to our context structure
>>> + *
>>> + * This function will a best effort FIFO allocation in order
>>> + * to improve FIFO usage and throughput, while still allowing
>>> + * us to enable as many endpoints as possible.
>>> + *
>>> + * Keep in mind that this operation will be highly dependent
>>> + * on the configured size for RAM1 - which contains TxFifo -,
>>> + * the amount of endpoints enabled on coreConsultant tool, and
>>> + * the width of the Master Bus.
>>> + *
>>> + * In general, FIFO depths are represented with the following equation:
>>> + *
>>> + * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
>>> + *
>>> + * In conjunction with dwc3_gadget_check_config(), this resizing logic will
>>> + * ensure that all endpoints will have enough internal memory for one max
>>> + * packet per endpoint.
>>> + */
>>> +static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
>>> +{
>>> +	struct dwc3 *dwc = dep->dwc;
>>> +	int fifo_0_start;
>>> +	int ram1_depth;
>>> +	int fifo_size;
>>> +	int min_depth;
>>> +	int num_in_ep;
>>> +	int remaining;
>>> +	int num_fifos = 1;
>>> +	int fifo;
>>> +	int tmp;
>>> +
>>> +	if (!dwc->do_fifo_resize)
>>> +		return 0;
>>> +
>>> +	/* resize IN endpoints except ep0 */
>>> +	if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
>>> +		return 0;
>>
>>> +
>>> +	ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
>>> +
>>> +	if ((dep->endpoint.maxburst > 1 &&
>>> +	     usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
>>> +	    usb_endpoint_xfer_isoc(dep->endpoint.desc))
>>> +		num_fifos = 3;
>>> +
>>> +	if (dep->endpoint.maxburst > 6 &&
>>> +	    usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31))
>>> +		num_fifos = dwc->tx_fifo_resize_max_num;
>>
>> Why only bulk? Isoc should be at least equal or more than bulk.
>> Also, make this applicable to DWC_usb32 also.
> 
> this should be applicable to all DWC3 versions, no? dwc3, 31 and 32.
> 

Yes.

BR,
Thinh

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
  2021-07-12 23:38   ` Thinh Nguyen
  2021-07-13  8:39     ` Felipe Balbi
@ 2021-07-14  2:59     ` Thinh Nguyen
  1 sibling, 0 replies; 18+ messages in thread
From: Thinh Nguyen @ 2021-07-14  2:59 UTC (permalink / raw)
  To: Thinh Nguyen, Wesley Cheng, balbi, gregkh, agross,
	bjorn.andersson, robh+dt, frowand.list
  Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree, jackp

Thinh Nguyen wrote:
> Hi,
> 
> Wesley Cheng wrote:
>> Some devices have USB compositions which may require multiple endpoints
>> that support EP bursting.  HW defined TX FIFO sizes may not always be
>> sufficient for these compositions.  By utilizing flexible TX FIFO
>> allocation, this allows for endpoints to request the required FIFO depth to
>> achieve higher bandwidth.  With some higher bMaxBurst configurations, using
>> a larger TX FIFO size results in better TX throughput.
>>
>> By introducing the check_config() callback, the resizing logic can fetch
>> the maximum number of endpoints used in the USB composition (can contain
>> multiple configurations), which helps ensure that the resizing logic can
>> fulfill the configuration(s), or return an error to the gadget layer
>> otherwise during bind time.
>>
>> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
>> ---
>>  drivers/usb/dwc3/core.c   |  15 +++
>>  drivers/usb/dwc3/core.h   |  16 ++++
>>  drivers/usb/dwc3/ep0.c    |   2 +
>>  drivers/usb/dwc3/gadget.c | 232 ++++++++++++++++++++++++++++++++++++++++++++++
>>  4 files changed, 265 insertions(+)
>>
>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>> index ba74ad7..b194aecd 100644
>> --- a/drivers/usb/dwc3/core.c
>> +++ b/drivers/usb/dwc3/core.c
>> @@ -1267,6 +1267,7 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>  	u8			rx_max_burst_prd;
>>  	u8			tx_thr_num_pkt_prd;
>>  	u8			tx_max_burst_prd;
>> +	u8			tx_fifo_resize_max_num;
>>  	const char		*usb_psy_name;
>>  	int			ret;
>>  
>> @@ -1282,6 +1283,13 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>  	 */
>>  	hird_threshold = 12;
>>  
>> +	/*
>> +	 * default to a TXFIFO size large enough to fit 6 max packets.  This
>> +	 * allows for systems with larger bus latencies to have some headroom
>> +	 * for endpoints that have a large bMaxBurst value.
>> +	 */
>> +	tx_fifo_resize_max_num = 6;
>> +
>>  	dwc->maximum_speed = usb_get_maximum_speed(dev);
>>  	dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
>>  	dwc->dr_mode = usb_get_dr_mode(dev);
>> @@ -1325,6 +1333,11 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>  				&tx_thr_num_pkt_prd);
>>  	device_property_read_u8(dev, "snps,tx-max-burst-prd",
>>  				&tx_max_burst_prd);
>> +	dwc->do_fifo_resize = device_property_read_bool(dev,
>> +							"tx-fifo-resize");
>> +	if (dwc->do_fifo_resize)
>> +		device_property_read_u8(dev, "tx-fifo-max-num",
>> +					&tx_fifo_resize_max_num);
> 
> Why is this check here? The dwc->tx_fifo_resize_max_num should store
> whatever property the user sets. Whether the driver wants to use this
> property should depend on "dwc->do_fifo_resize". Also why don't we have
> "snps," prefix to be consistent with the other properties?
> 
> Can we enforce to a single property? If the designer wants to enable
> this feature, he/she can to provide the tx-fifo-max-num. This would
> simplify the driver a bit. Since this is to optimize for performance,
> the user should know/want/test the specific value if they want to set
> for their setup and not hoping that the default setting not break their
> setup. So we can remove the "do_fifo_resize" property and just check
> whether tx_fifo_resize_max_num is set.
> 
>>  
>>  	dwc->disable_scramble_quirk = device_property_read_bool(dev,
>>  				"snps,disable_scramble_quirk");
>> @@ -1390,6 +1403,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>  	dwc->tx_max_burst_prd = tx_max_burst_prd;
>>  
>>  	dwc->imod_interval = 0;
>> +
>> +	dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
> 
> See comment above
> 
>>  }
>>  
>>  /* check whether the core supports IMOD */
>> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
>> index dccdf13..735e9be 100644
>> --- a/drivers/usb/dwc3/core.h
>> +++ b/drivers/usb/dwc3/core.h
>> @@ -1023,6 +1023,7 @@ struct dwc3_scratchpad_array {
>>   * @rx_max_burst_prd: max periodic ESS receive burst size
>>   * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
>>   * @tx_max_burst_prd: max periodic ESS transmit burst size
>> + * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize
>>   * @hsphy_interface: "utmi" or "ulpi"
>>   * @connected: true when we're connected to a host, false otherwise
>>   * @delayed_status: true when gadget driver asks for delayed status
>> @@ -1037,6 +1038,7 @@ struct dwc3_scratchpad_array {
>>   *	1	- utmi_l1_suspend_n
>>   * @is_fpga: true when we are using the FPGA board
>>   * @pending_events: true when we have pending IRQs to be handled
>> + * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
>>   * @pullups_connected: true when Run/Stop bit is set
>>   * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
>>   * @three_stage_setup: set if we perform a three phase setup
>> @@ -1079,6 +1081,11 @@ struct dwc3_scratchpad_array {
>>   * @dis_split_quirk: set to disable split boundary.
>>   * @imod_interval: set the interrupt moderation interval in 250ns
>>   *			increments or 0 to disable.
>> + * @max_cfg_eps: current max number of IN eps used across all USB configs.
>> + * @last_fifo_depth: last fifo depth used to determine next fifo ram start
>> + *		     address.
>> + * @num_ep_resized: carries the current number endpoints which have had its tx
>> + *		    fifo resized.
>>   */
>>  struct dwc3 {
>>  	struct work_struct	drd_work;
>> @@ -1233,6 +1240,7 @@ struct dwc3 {
>>  	u8			rx_max_burst_prd;
>>  	u8			tx_thr_num_pkt_prd;
>>  	u8			tx_max_burst_prd;
>> +	u8			tx_fifo_resize_max_num;
>>  
>>  	const char		*hsphy_interface;
>>  
>> @@ -1246,6 +1254,7 @@ struct dwc3 {
>>  	unsigned		is_utmi_l1_suspend:1;
>>  	unsigned		is_fpga:1;
>>  	unsigned		pending_events:1;
>> +	unsigned		do_fifo_resize:1;
>>  	unsigned		pullups_connected:1;
>>  	unsigned		setup_packet_pending:1;
>>  	unsigned		three_stage_setup:1;
>> @@ -1281,6 +1290,10 @@ struct dwc3 {
>>  	unsigned		dis_split_quirk:1;
>>  
>>  	u16			imod_interval;
>> +
>> +	int			max_cfg_eps;
>> +	int			last_fifo_depth;
>> +	int			num_ep_resized;
>>  };
>>  
>>  #define INCRX_BURST_MODE 0
>> @@ -1512,6 +1525,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
>>  		struct dwc3_gadget_ep_cmd_params *params);
>>  int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
>>  		u32 param);
>> +void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc);
>>  #else
>>  static inline int dwc3_gadget_init(struct dwc3 *dwc)
>>  { return 0; }
>> @@ -1531,6 +1545,8 @@ static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
>>  static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
>>  		int cmd, u32 param)
>>  { return 0; }
>> +static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
>> +{ }
>>  #endif
>>  
>>  #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
>> diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
>> index 3cd2942..d28d085 100644
>> --- a/drivers/usb/dwc3/ep0.c
>> +++ b/drivers/usb/dwc3/ep0.c
>> @@ -619,6 +619,8 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
>>  		return -EINVAL;
>>  
>>  	case USB_STATE_ADDRESS:
>> +		dwc3_gadget_clear_tx_fifos(dwc);
>> +
>>  		ret = dwc3_ep0_delegate_req(dwc, ctrl);
>>  		/* if the cfg matches and the cfg is non zero */
>>  		if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
>> diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
>> index af6d7f1..e56f1a6 100644
>> --- a/drivers/usb/dwc3/gadget.c
>> +++ b/drivers/usb/dwc3/gadget.c
>> @@ -632,6 +632,187 @@ static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
>>  		bool interrupt);
>>  
>>  /**
>> + * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
>> + * @dwc: pointer to the DWC3 context
>> + * @nfifos: number of fifos to calculate for
>> + *
>> + * Calculates the size value based on the equation below:
>> + *
>> + * DWC3 revision 280A and prior:
>> + * fifo_size = mult * (max_packet / mdwidth) + 1;
>> + *
>> + * DWC3 revision 290A and onwards:
>> + * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
>> + *
>> + * The max packet size is set to 1024, as the txfifo requirements mainly apply
>> + * to super speed USB use cases.  However, it is safe to overestimate the fifo
>> + * allocations for other scenarios, i.e. high speed USB.
>> + */
>> +static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)

"mult" should be "nfifos" just as documented at the start of the function.

>> +{
>> +	int max_packet = 1024;
>> +	int fifo_size;
>> +	int mdwidth;
>> +
>> +	mdwidth = dwc3_mdwidth(dwc);

dwc3_mdwidth() returns u32 type, can we keep it consistent and use
unsigned types where it makes sense? (same for dwc->max_cfg_eps,
last_fifo_depth, and num_ep_resized)

Also, let's have this function return type u32 too. Usually int implies
it may return an error code.

>> +
>> +	/* MDWIDTH is represented in bits, we need it in bytes */
>> +	mdwidth >>= 3;

It's unlikely, but let's check if mdwidth is not 0.

>> +
>> +	if (DWC3_VER_IS_PRIOR(DWC3, 290A))
>> +		fifo_size = mult * (max_packet / mdwidth) + 1;
>> +	else
>> +		fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;

Please add blank line here.

>> +	return fifo_size;
>> +}
>> +
>> +/**
>> + * dwc3_gadget_clear_tx_fifo_size - Clears txfifo allocation
>> + * @dwc: pointer to the DWC3 context
>> + *
>> + * Iterates through all the endpoint registers and clears the previous txfifo
>> + * allocations.
>> + */
>> +void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
>> +{
>> +	struct dwc3_ep *dep;
>> +	int fifo_depth;
>> +	int size;
>> +	int num;
>> +
>> +	if (!dwc->do_fifo_resize)
>> +		return;
>> +
>> +	/* Read ep0IN related TXFIFO size */
>> +	dep = dwc->eps[1];
>> +	size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
>> +	if (DWC3_IP_IS(DWC3))
>> +		fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
>> +	else
>> +		fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
>> +
>> +	dwc->last_fifo_depth = fifo_depth;
>> +	/* Clear existing TXFIFO for all IN eps except ep0 */
>> +	for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
>> +	     num += 2) {
>> +		dep = dwc->eps[num];
>> +		/* Don't change TXFRAMNUM on usb31 version */
>> +		size = DWC3_IP_IS(DWC3) ? 0 :
>> +			dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
>> +				   DWC31_GTXFIFOSIZ_TXFRAMNUM;
>> +
>> +		dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
>> +	}
>> +	dwc->num_ep_resized = 0;
>> +}
>> +
>> +/*
>> + * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
>> + * @dwc: pointer to our context structure
>> + *
>> + * This function will a best effort FIFO allocation in order
>> + * to improve FIFO usage and throughput, while still allowing
>> + * us to enable as many endpoints as possible.
>> + *
>> + * Keep in mind that this operation will be highly dependent
>> + * on the configured size for RAM1 - which contains TxFifo -,
>> + * the amount of endpoints enabled on coreConsultant tool, and
>> + * the width of the Master Bus.
>> + *
>> + * In general, FIFO depths are represented with the following equation:
>> + *
>> + * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
>> + *
>> + * In conjunction with dwc3_gadget_check_config(), this resizing logic will
>> + * ensure that all endpoints will have enough internal memory for one max
>> + * packet per endpoint.
>> + */
>> +static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
>> +{
>> +	struct dwc3 *dwc = dep->dwc;
>> +	int fifo_0_start;
>> +	int ram1_depth;
>> +	int fifo_size;
>> +	int min_depth;
>> +	int num_in_ep;
>> +	int remaining;
>> +	int num_fifos = 1;
>> +	int fifo;
>> +	int tmp;
>> +
>> +	if (!dwc->do_fifo_resize)
>> +		return 0;
>> +
>> +	/* resize IN endpoints except ep0 */
>> +	if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
>> +		return 0;
> 
>> +
>> +	ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
>> +
>> +	if ((dep->endpoint.maxburst > 1 &&
>> +	     usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
>> +	    usb_endpoint_xfer_isoc(dep->endpoint.desc))
>> +		num_fifos = 3;
>> +
>> +	if (dep->endpoint.maxburst > 6 &&
>> +	    usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31))
>> +		num_fifos = dwc->tx_fifo_resize_max_num;
> 
> Why only bulk? Isoc should be at least equal or more than bulk.
> Also, make this applicable to DWC_usb32 also.
> 
>> +
>> +	/* FIFO size for a single buffer */
>> +	fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
>> +
>> +	/* Calculate the number of remaining EPs w/o any FIFO */
>> +	num_in_ep = dwc->max_cfg_eps;
>> +	num_in_ep -= dwc->num_ep_resized;
> 
> Does this calculation account for multiple alt-setting interfaces?
> 
>> +
>> +	/* Reserve at least one FIFO for the number of IN EPs */
>> +	min_depth = num_in_ep * (fifo + 1);
>> +	remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
>> +	remaining = max_t(int, 0, remaining);
> 
> Add blank line
> 
>> +	/*
>> +	 * We've already reserved 1 FIFO per EP, so check what we can fit in
>> +	 * addition to it.  If there is not enough remaining space, allocate
>> +	 * all the remaining space to the EP.
>> +	 */
>> +	fifo_size = (num_fifos - 1) * fifo;
>> +	if (remaining < fifo_size)
>> +		fifo_size = remaining;
>> +
>> +	fifo_size += fifo;
>> +	/* Last increment according to the TX FIFO size equation */
>> +	fifo_size++;
>> +
>> +	/* Check if TXFIFOs start at non-zero addr */
>> +	tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
>> +	fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
>> +
>> +	fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
>> +	if (DWC3_IP_IS(DWC3))
>> +		dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
>> +	else
>> +		dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
>> +
>> +	/* Check fifo size allocation doesn't exceed available RAM size. */
>> +	if (dwc->last_fifo_depth >= ram1_depth) {
>> +		dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
>> +			dwc->last_fifo_depth, ram1_depth,
>> +			dep->endpoint.name, fifo_size);
>> +		if (DWC3_IP_IS(DWC3))
>> +			fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
>> +		else
>> +			fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
>> +
>> +		dwc->last_fifo_depth -= fifo_size;
>> +		return -ENOMEM;
>> +	}
>> +
>> +	dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
>> +	dwc->num_ep_resized++;

I see this num_ep_resized gets incremented, but I don't see where it
gets decremented. Probably should be done in ep disable. This doesn't
seem to account for multiple alt-settings.

>> +
>> +	return 0;
>> +}
>> +
>> +/**
>>   * __dwc3_gadget_ep_enable - initializes a hw endpoint
>>   * @dep: endpoint to be initialized
>>   * @action: one of INIT, MODIFY or RESTORE
>> @@ -648,6 +829,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
>>  	int			ret;
>>  
>>  	if (!(dep->flags & DWC3_EP_ENABLED)) {
>> +		ret = dwc3_gadget_resize_tx_fifos(dep);
>> +		if (ret)
>> +			return ret;
>> +
>>  		ret = dwc3_gadget_start_config(dep);
>>  		if (ret)
>>  			return ret;
>> @@ -2498,6 +2683,7 @@ static int dwc3_gadget_stop(struct usb_gadget *g)
>>  
>>  	spin_lock_irqsave(&dwc->lock, flags);
>>  	dwc->gadget_driver	= NULL;
>> +	dwc->max_cfg_eps = 0;
>>  	spin_unlock_irqrestore(&dwc->lock, flags);
>>  
>>  	free_irq(dwc->irq_gadget, dwc->ev_buf);
>> @@ -2585,6 +2771,51 @@ static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
>>  	return ret;
>>  }
>>  
>> +/**
>> + * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
>> + * @g: pointer to the USB gadget
>> + *
>> + * Used to record the maximum number of endpoints being used in a USB composite
>> + * device. (across all configurations)  This is to be used in the calculation
>> + * of the TXFIFO sizes when resizing internal memory for individual endpoints.
>> + * It will help ensured that the resizing logic reserves enough space for at
>> + * least one max packet.
>> + */
>> +static int dwc3_gadget_check_config(struct usb_gadget *g)
>> +{
>> +	struct dwc3 *dwc = gadget_to_dwc(g);
>> +	struct usb_ep *ep;
>> +	int fifo_size = 0;
>> +	int ram1_depth;
>> +	int ep_num = 0;
>> +
>> +	if (!dwc->do_fifo_resize)
>> +		return 0;
>> +
>> +	list_for_each_entry(ep, &g->ep_list, ep_list) {
>> +		/* Only interested in the IN endpoints */
>> +		if (ep->claimed && (ep->address & USB_DIR_IN))
>> +			ep_num++;
>> +	}
>> +
>> +	if (ep_num <= dwc->max_cfg_eps)
>> +		return 0;
>> +
>> +	/* Update the max number of eps in the composition */
>> +	dwc->max_cfg_eps = ep_num;
>> +
>> +	fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
>> +	/* Based on the equation, increment by one for every ep */
>> +	fifo_size += dwc->max_cfg_eps;
>> +
>> +	/* Check if we can fit a single fifo per endpoint */
>> +	ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
>> +	if (fifo_size > ram1_depth)
>> +		return -ENOMEM;

This seems fragile... Can we fall back to the default settings if the tx
fifo resize doesn't work? I think the function will fail to bind if this
fails right?

>> +
>> +	return 0;
>> +}
>> +
>>  static const struct usb_gadget_ops dwc3_gadget_ops = {
>>  	.get_frame		= dwc3_gadget_get_frame,
>>  	.wakeup			= dwc3_gadget_wakeup,
>> @@ -2596,6 +2827,7 @@ static const struct usb_gadget_ops dwc3_gadget_ops = {
>>  	.udc_set_ssp_rate	= dwc3_gadget_set_ssp_rate,
>>  	.get_config_params	= dwc3_gadget_config_params,
>>  	.vbus_draw		= dwc3_gadget_vbus_draw,
>> +	.check_config		= dwc3_gadget_check_config,
>>  };
>>  
>>  /* -------------------------------------------------------------------------- */
>>

BR,
Thinh

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
  2021-07-13  8:39     ` Felipe Balbi
  2021-07-14  2:58       ` Thinh Nguyen
@ 2021-07-14  3:10       ` Thinh Nguyen
  2021-07-14  6:40         ` Felipe Balbi
  2021-07-14  6:51         ` gregkh
  1 sibling, 2 replies; 18+ messages in thread
From: Thinh Nguyen @ 2021-07-14  3:10 UTC (permalink / raw)
  To: Felipe Balbi, Thinh Nguyen, Wesley Cheng, gregkh, agross,
	bjorn.andersson, robh+dt, frowand.list
  Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree, jackp

Felipe Balbi wrote:
> 
> Hi,
> 
> Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
>> Wesley Cheng wrote:
>>> Some devices have USB compositions which may require multiple endpoints
>>> that support EP bursting.  HW defined TX FIFO sizes may not always be
>>> sufficient for these compositions.  By utilizing flexible TX FIFO
>>> allocation, this allows for endpoints to request the required FIFO depth to
>>> achieve higher bandwidth.  With some higher bMaxBurst configurations, using
>>> a larger TX FIFO size results in better TX throughput.
>>>
>>> By introducing the check_config() callback, the resizing logic can fetch
>>> the maximum number of endpoints used in the USB composition (can contain
>>> multiple configurations), which helps ensure that the resizing logic can
>>> fulfill the configuration(s), or return an error to the gadget layer
>>> otherwise during bind time.
>>>
>>> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
>>> ---
>>>  drivers/usb/dwc3/core.c   |  15 +++
>>>  drivers/usb/dwc3/core.h   |  16 ++++
>>>  drivers/usb/dwc3/ep0.c    |   2 +
>>>  drivers/usb/dwc3/gadget.c | 232 ++++++++++++++++++++++++++++++++++++++++++++++
>>>  4 files changed, 265 insertions(+)
>>>
>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>>> index ba74ad7..b194aecd 100644
>>> --- a/drivers/usb/dwc3/core.c
>>> +++ b/drivers/usb/dwc3/core.c
>>> @@ -1267,6 +1267,7 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>>  	u8			rx_max_burst_prd;
>>>  	u8			tx_thr_num_pkt_prd;
>>>  	u8			tx_max_burst_prd;
>>> +	u8			tx_fifo_resize_max_num;
>>>  	const char		*usb_psy_name;
>>>  	int			ret;
>>>  
>>> @@ -1282,6 +1283,13 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>>  	 */
>>>  	hird_threshold = 12;
>>>  
>>> +	/*
>>> +	 * default to a TXFIFO size large enough to fit 6 max packets.  This
>>> +	 * allows for systems with larger bus latencies to have some headroom
>>> +	 * for endpoints that have a large bMaxBurst value.
>>> +	 */
>>> +	tx_fifo_resize_max_num = 6;
>>> +
>>>  	dwc->maximum_speed = usb_get_maximum_speed(dev);
>>>  	dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
>>>  	dwc->dr_mode = usb_get_dr_mode(dev);
>>> @@ -1325,6 +1333,11 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>>  				&tx_thr_num_pkt_prd);
>>>  	device_property_read_u8(dev, "snps,tx-max-burst-prd",
>>>  				&tx_max_burst_prd);
>>> +	dwc->do_fifo_resize = device_property_read_bool(dev,
>>> +							"tx-fifo-resize");
>>> +	if (dwc->do_fifo_resize)
>>> +		device_property_read_u8(dev, "tx-fifo-max-num",
>>> +					&tx_fifo_resize_max_num);
>>
>> Why is this check here? The dwc->tx_fifo_resize_max_num should store
>> whatever property the user sets. Whether the driver wants to use this
> 
> Ack!
> 
>> property should depend on "dwc->do_fifo_resize". Also why don't we have
>> "snps," prefix to be consistent with the other properties?
> 
> Ack!
> 
>> Can we enforce to a single property? If the designer wants to enable
>> this feature, he/she can to provide the tx-fifo-max-num. This would
>> simplify the driver a bit. Since this is to optimize for performance,
>> the user should know/want/test the specific value if they want to set
>> for their setup and not hoping that the default setting not break their
>> setup. So we can remove the "do_fifo_resize" property and just check
>> whether tx_fifo_resize_max_num is set.
> 
> Ack!
> 
> All very valid points :-)
> 

Looks like this series already landed in Greg's testing branch. Not sure
how we usually handle this to address some of our concerns. Add fix
patches on top of Greg's testing branch?

BR,
Thinh


^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
  2021-07-14  3:10       ` Thinh Nguyen
@ 2021-07-14  6:40         ` Felipe Balbi
  2021-07-14  6:52           ` gregkh
  2021-07-14  7:30           ` Wesley Cheng
  2021-07-14  6:51         ` gregkh
  1 sibling, 2 replies; 18+ messages in thread
From: Felipe Balbi @ 2021-07-14  6:40 UTC (permalink / raw)
  To: Thinh Nguyen, Thinh Nguyen, Wesley Cheng, gregkh, agross,
	bjorn.andersson, robh+dt, frowand.list
  Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree, jackp

[-- Attachment #1: Type: text/plain, Size: 3841 bytes --]


Hi,

Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
>> Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
>>> Wesley Cheng wrote:
>>>> Some devices have USB compositions which may require multiple endpoints
>>>> that support EP bursting.  HW defined TX FIFO sizes may not always be
>>>> sufficient for these compositions.  By utilizing flexible TX FIFO
>>>> allocation, this allows for endpoints to request the required FIFO depth to
>>>> achieve higher bandwidth.  With some higher bMaxBurst configurations, using
>>>> a larger TX FIFO size results in better TX throughput.
>>>>
>>>> By introducing the check_config() callback, the resizing logic can fetch
>>>> the maximum number of endpoints used in the USB composition (can contain
>>>> multiple configurations), which helps ensure that the resizing logic can
>>>> fulfill the configuration(s), or return an error to the gadget layer
>>>> otherwise during bind time.
>>>>
>>>> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
>>>> ---
>>>>  drivers/usb/dwc3/core.c   |  15 +++
>>>>  drivers/usb/dwc3/core.h   |  16 ++++
>>>>  drivers/usb/dwc3/ep0.c    |   2 +
>>>>  drivers/usb/dwc3/gadget.c | 232 ++++++++++++++++++++++++++++++++++++++++++++++
>>>>  4 files changed, 265 insertions(+)
>>>>
>>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>>>> index ba74ad7..b194aecd 100644
>>>> --- a/drivers/usb/dwc3/core.c
>>>> +++ b/drivers/usb/dwc3/core.c
>>>> @@ -1267,6 +1267,7 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>>>  	u8			rx_max_burst_prd;
>>>>  	u8			tx_thr_num_pkt_prd;
>>>>  	u8			tx_max_burst_prd;
>>>> +	u8			tx_fifo_resize_max_num;
>>>>  	const char		*usb_psy_name;
>>>>  	int			ret;
>>>>  
>>>> @@ -1282,6 +1283,13 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>>>  	 */
>>>>  	hird_threshold = 12;
>>>>  
>>>> +	/*
>>>> +	 * default to a TXFIFO size large enough to fit 6 max packets.  This
>>>> +	 * allows for systems with larger bus latencies to have some headroom
>>>> +	 * for endpoints that have a large bMaxBurst value.
>>>> +	 */
>>>> +	tx_fifo_resize_max_num = 6;
>>>> +
>>>>  	dwc->maximum_speed = usb_get_maximum_speed(dev);
>>>>  	dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
>>>>  	dwc->dr_mode = usb_get_dr_mode(dev);
>>>> @@ -1325,6 +1333,11 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>>>  				&tx_thr_num_pkt_prd);
>>>>  	device_property_read_u8(dev, "snps,tx-max-burst-prd",
>>>>  				&tx_max_burst_prd);
>>>> +	dwc->do_fifo_resize = device_property_read_bool(dev,
>>>> +							"tx-fifo-resize");
>>>> +	if (dwc->do_fifo_resize)
>>>> +		device_property_read_u8(dev, "tx-fifo-max-num",
>>>> +					&tx_fifo_resize_max_num);
>>>
>>> Why is this check here? The dwc->tx_fifo_resize_max_num should store
>>> whatever property the user sets. Whether the driver wants to use this
>> 
>> Ack!
>> 
>>> property should depend on "dwc->do_fifo_resize". Also why don't we have
>>> "snps," prefix to be consistent with the other properties?
>> 
>> Ack!
>> 
>>> Can we enforce to a single property? If the designer wants to enable
>>> this feature, he/she can to provide the tx-fifo-max-num. This would
>>> simplify the driver a bit. Since this is to optimize for performance,
>>> the user should know/want/test the specific value if they want to set
>>> for their setup and not hoping that the default setting not break their
>>> setup. So we can remove the "do_fifo_resize" property and just check
>>> whether tx_fifo_resize_max_num is set.
>> 
>> Ack!
>> 
>> All very valid points :-)
>> 
>
> Looks like this series already landed in Greg's testing branch. Not sure
> how we usually handle this to address some of our concerns. Add fix
> patches on top of Greg's testing branch?

yup, no choice anymore :-(

-- 
balbi

[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
  2021-07-14  3:10       ` Thinh Nguyen
  2021-07-14  6:40         ` Felipe Balbi
@ 2021-07-14  6:51         ` gregkh
  1 sibling, 0 replies; 18+ messages in thread
From: gregkh @ 2021-07-14  6:51 UTC (permalink / raw)
  To: Thinh Nguyen
  Cc: Felipe Balbi, Wesley Cheng, agross, bjorn.andersson, robh+dt,
	frowand.list, linux-usb, linux-kernel, linux-arm-msm, devicetree,
	jackp

On Wed, Jul 14, 2021 at 03:10:25AM +0000, Thinh Nguyen wrote:
> Felipe Balbi wrote:
> > 
> > Hi,
> > 
> > Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
> >> Wesley Cheng wrote:
> >>> Some devices have USB compositions which may require multiple endpoints
> >>> that support EP bursting.  HW defined TX FIFO sizes may not always be
> >>> sufficient for these compositions.  By utilizing flexible TX FIFO
> >>> allocation, this allows for endpoints to request the required FIFO depth to
> >>> achieve higher bandwidth.  With some higher bMaxBurst configurations, using
> >>> a larger TX FIFO size results in better TX throughput.
> >>>
> >>> By introducing the check_config() callback, the resizing logic can fetch
> >>> the maximum number of endpoints used in the USB composition (can contain
> >>> multiple configurations), which helps ensure that the resizing logic can
> >>> fulfill the configuration(s), or return an error to the gadget layer
> >>> otherwise during bind time.
> >>>
> >>> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
> >>> ---
> >>>  drivers/usb/dwc3/core.c   |  15 +++
> >>>  drivers/usb/dwc3/core.h   |  16 ++++
> >>>  drivers/usb/dwc3/ep0.c    |   2 +
> >>>  drivers/usb/dwc3/gadget.c | 232 ++++++++++++++++++++++++++++++++++++++++++++++
> >>>  4 files changed, 265 insertions(+)
> >>>
> >>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> >>> index ba74ad7..b194aecd 100644
> >>> --- a/drivers/usb/dwc3/core.c
> >>> +++ b/drivers/usb/dwc3/core.c
> >>> @@ -1267,6 +1267,7 @@ static void dwc3_get_properties(struct dwc3 *dwc)
> >>>  	u8			rx_max_burst_prd;
> >>>  	u8			tx_thr_num_pkt_prd;
> >>>  	u8			tx_max_burst_prd;
> >>> +	u8			tx_fifo_resize_max_num;
> >>>  	const char		*usb_psy_name;
> >>>  	int			ret;
> >>>  
> >>> @@ -1282,6 +1283,13 @@ static void dwc3_get_properties(struct dwc3 *dwc)
> >>>  	 */
> >>>  	hird_threshold = 12;
> >>>  
> >>> +	/*
> >>> +	 * default to a TXFIFO size large enough to fit 6 max packets.  This
> >>> +	 * allows for systems with larger bus latencies to have some headroom
> >>> +	 * for endpoints that have a large bMaxBurst value.
> >>> +	 */
> >>> +	tx_fifo_resize_max_num = 6;
> >>> +
> >>>  	dwc->maximum_speed = usb_get_maximum_speed(dev);
> >>>  	dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
> >>>  	dwc->dr_mode = usb_get_dr_mode(dev);
> >>> @@ -1325,6 +1333,11 @@ static void dwc3_get_properties(struct dwc3 *dwc)
> >>>  				&tx_thr_num_pkt_prd);
> >>>  	device_property_read_u8(dev, "snps,tx-max-burst-prd",
> >>>  				&tx_max_burst_prd);
> >>> +	dwc->do_fifo_resize = device_property_read_bool(dev,
> >>> +							"tx-fifo-resize");
> >>> +	if (dwc->do_fifo_resize)
> >>> +		device_property_read_u8(dev, "tx-fifo-max-num",
> >>> +					&tx_fifo_resize_max_num);
> >>
> >> Why is this check here? The dwc->tx_fifo_resize_max_num should store
> >> whatever property the user sets. Whether the driver wants to use this
> > 
> > Ack!
> > 
> >> property should depend on "dwc->do_fifo_resize". Also why don't we have
> >> "snps," prefix to be consistent with the other properties?
> > 
> > Ack!
> > 
> >> Can we enforce to a single property? If the designer wants to enable
> >> this feature, he/she can to provide the tx-fifo-max-num. This would
> >> simplify the driver a bit. Since this is to optimize for performance,
> >> the user should know/want/test the specific value if they want to set
> >> for their setup and not hoping that the default setting not break their
> >> setup. So we can remove the "do_fifo_resize" property and just check
> >> whether tx_fifo_resize_max_num is set.
> > 
> > Ack!
> > 
> > All very valid points :-)
> > 
> 
> Looks like this series already landed in Greg's testing branch. Not sure
> how we usually handle this to address some of our concerns. Add fix
> patches on top of Greg's testing branch?

Yes please send patches on top of this series.

thanks,

greg k-h

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
  2021-07-14  6:40         ` Felipe Balbi
@ 2021-07-14  6:52           ` gregkh
  2021-07-14  7:30           ` Wesley Cheng
  1 sibling, 0 replies; 18+ messages in thread
From: gregkh @ 2021-07-14  6:52 UTC (permalink / raw)
  To: Felipe Balbi
  Cc: Thinh Nguyen, Wesley Cheng, agross, bjorn.andersson, robh+dt,
	frowand.list, linux-usb, linux-kernel, linux-arm-msm, devicetree,
	jackp

On Wed, Jul 14, 2021 at 09:40:13AM +0300, Felipe Balbi wrote:
> 
> Hi,
> 
> Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
> >> Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
> >>> Wesley Cheng wrote:
> >>>> Some devices have USB compositions which may require multiple endpoints
> >>>> that support EP bursting.  HW defined TX FIFO sizes may not always be
> >>>> sufficient for these compositions.  By utilizing flexible TX FIFO
> >>>> allocation, this allows for endpoints to request the required FIFO depth to
> >>>> achieve higher bandwidth.  With some higher bMaxBurst configurations, using
> >>>> a larger TX FIFO size results in better TX throughput.
> >>>>
> >>>> By introducing the check_config() callback, the resizing logic can fetch
> >>>> the maximum number of endpoints used in the USB composition (can contain
> >>>> multiple configurations), which helps ensure that the resizing logic can
> >>>> fulfill the configuration(s), or return an error to the gadget layer
> >>>> otherwise during bind time.
> >>>>
> >>>> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
> >>>> ---
> >>>>  drivers/usb/dwc3/core.c   |  15 +++
> >>>>  drivers/usb/dwc3/core.h   |  16 ++++
> >>>>  drivers/usb/dwc3/ep0.c    |   2 +
> >>>>  drivers/usb/dwc3/gadget.c | 232 ++++++++++++++++++++++++++++++++++++++++++++++
> >>>>  4 files changed, 265 insertions(+)
> >>>>
> >>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> >>>> index ba74ad7..b194aecd 100644
> >>>> --- a/drivers/usb/dwc3/core.c
> >>>> +++ b/drivers/usb/dwc3/core.c
> >>>> @@ -1267,6 +1267,7 @@ static void dwc3_get_properties(struct dwc3 *dwc)
> >>>>  	u8			rx_max_burst_prd;
> >>>>  	u8			tx_thr_num_pkt_prd;
> >>>>  	u8			tx_max_burst_prd;
> >>>> +	u8			tx_fifo_resize_max_num;
> >>>>  	const char		*usb_psy_name;
> >>>>  	int			ret;
> >>>>  
> >>>> @@ -1282,6 +1283,13 @@ static void dwc3_get_properties(struct dwc3 *dwc)
> >>>>  	 */
> >>>>  	hird_threshold = 12;
> >>>>  
> >>>> +	/*
> >>>> +	 * default to a TXFIFO size large enough to fit 6 max packets.  This
> >>>> +	 * allows for systems with larger bus latencies to have some headroom
> >>>> +	 * for endpoints that have a large bMaxBurst value.
> >>>> +	 */
> >>>> +	tx_fifo_resize_max_num = 6;
> >>>> +
> >>>>  	dwc->maximum_speed = usb_get_maximum_speed(dev);
> >>>>  	dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
> >>>>  	dwc->dr_mode = usb_get_dr_mode(dev);
> >>>> @@ -1325,6 +1333,11 @@ static void dwc3_get_properties(struct dwc3 *dwc)
> >>>>  				&tx_thr_num_pkt_prd);
> >>>>  	device_property_read_u8(dev, "snps,tx-max-burst-prd",
> >>>>  				&tx_max_burst_prd);
> >>>> +	dwc->do_fifo_resize = device_property_read_bool(dev,
> >>>> +							"tx-fifo-resize");
> >>>> +	if (dwc->do_fifo_resize)
> >>>> +		device_property_read_u8(dev, "tx-fifo-max-num",
> >>>> +					&tx_fifo_resize_max_num);
> >>>
> >>> Why is this check here? The dwc->tx_fifo_resize_max_num should store
> >>> whatever property the user sets. Whether the driver wants to use this
> >> 
> >> Ack!
> >> 
> >>> property should depend on "dwc->do_fifo_resize". Also why don't we have
> >>> "snps," prefix to be consistent with the other properties?
> >> 
> >> Ack!
> >> 
> >>> Can we enforce to a single property? If the designer wants to enable
> >>> this feature, he/she can to provide the tx-fifo-max-num. This would
> >>> simplify the driver a bit. Since this is to optimize for performance,
> >>> the user should know/want/test the specific value if they want to set
> >>> for their setup and not hoping that the default setting not break their
> >>> setup. So we can remove the "do_fifo_resize" property and just check
> >>> whether tx_fifo_resize_max_num is set.
> >> 
> >> Ack!
> >> 
> >> All very valid points :-)
> >> 
> >
> > Looks like this series already landed in Greg's testing branch. Not sure
> > how we usually handle this to address some of our concerns. Add fix
> > patches on top of Greg's testing branch?
> 
> yup, no choice anymore :-(

I took these as they seemed correct.  If they need to be reverted,
that's fine I can do that.  But it looks like Wesley can just make some
simple changes on top of them to resolve the remaining issues, right?

thanks,

greg k-h

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
  2021-07-14  6:40         ` Felipe Balbi
  2021-07-14  6:52           ` gregkh
@ 2021-07-14  7:30           ` Wesley Cheng
  2021-07-20 11:41             ` gregkh
  1 sibling, 1 reply; 18+ messages in thread
From: Wesley Cheng @ 2021-07-14  7:30 UTC (permalink / raw)
  To: Felipe Balbi, Thinh Nguyen, gregkh, agross, bjorn.andersson,
	robh+dt, frowand.list
  Cc: linux-usb, linux-kernel, linux-arm-msm, devicetree, jackp



On 7/13/2021 11:40 PM, Felipe Balbi wrote:
> 
> Hi,
> 
> Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
>>> Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
>>>> Wesley Cheng wrote:
>>>>> Some devices have USB compositions which may require multiple endpoints
>>>>> that support EP bursting.  HW defined TX FIFO sizes may not always be
>>>>> sufficient for these compositions.  By utilizing flexible TX FIFO
>>>>> allocation, this allows for endpoints to request the required FIFO depth to
>>>>> achieve higher bandwidth.  With some higher bMaxBurst configurations, using
>>>>> a larger TX FIFO size results in better TX throughput.
>>>>>
>>>>> By introducing the check_config() callback, the resizing logic can fetch
>>>>> the maximum number of endpoints used in the USB composition (can contain
>>>>> multiple configurations), which helps ensure that the resizing logic can
>>>>> fulfill the configuration(s), or return an error to the gadget layer
>>>>> otherwise during bind time.
>>>>>
>>>>> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
>>>>> ---
>>>>>  drivers/usb/dwc3/core.c   |  15 +++
>>>>>  drivers/usb/dwc3/core.h   |  16 ++++
>>>>>  drivers/usb/dwc3/ep0.c    |   2 +
>>>>>  drivers/usb/dwc3/gadget.c | 232 ++++++++++++++++++++++++++++++++++++++++++++++
>>>>>  4 files changed, 265 insertions(+)
>>>>>
>>>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>>>>> index ba74ad7..b194aecd 100644
>>>>> --- a/drivers/usb/dwc3/core.c
>>>>> +++ b/drivers/usb/dwc3/core.c
>>>>> @@ -1267,6 +1267,7 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>>>>  	u8			rx_max_burst_prd;
>>>>>  	u8			tx_thr_num_pkt_prd;
>>>>>  	u8			tx_max_burst_prd;
>>>>> +	u8			tx_fifo_resize_max_num;
>>>>>  	const char		*usb_psy_name;
>>>>>  	int			ret;
>>>>>  
>>>>> @@ -1282,6 +1283,13 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>>>>  	 */
>>>>>  	hird_threshold = 12;
>>>>>  
>>>>> +	/*
>>>>> +	 * default to a TXFIFO size large enough to fit 6 max packets.  This
>>>>> +	 * allows for systems with larger bus latencies to have some headroom
>>>>> +	 * for endpoints that have a large bMaxBurst value.
>>>>> +	 */
>>>>> +	tx_fifo_resize_max_num = 6;
>>>>> +
>>>>>  	dwc->maximum_speed = usb_get_maximum_speed(dev);
>>>>>  	dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
>>>>>  	dwc->dr_mode = usb_get_dr_mode(dev);
>>>>> @@ -1325,6 +1333,11 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>>>>  				&tx_thr_num_pkt_prd);
>>>>>  	device_property_read_u8(dev, "snps,tx-max-burst-prd",
>>>>>  				&tx_max_burst_prd);
>>>>> +	dwc->do_fifo_resize = device_property_read_bool(dev,
>>>>> +							"tx-fifo-resize");
>>>>> +	if (dwc->do_fifo_resize)
>>>>> +		device_property_read_u8(dev, "tx-fifo-max-num",
>>>>> +					&tx_fifo_resize_max_num);
>>>>
>>>> Why is this check here? The dwc->tx_fifo_resize_max_num should store
>>>> whatever property the user sets. Whether the driver wants to use this
>>>
>>> Ack!
>>>
>>>> property should depend on "dwc->do_fifo_resize". Also why don't we have
>>>> "snps," prefix to be consistent with the other properties?
>>>
>>> Ack!
>>>
>>>> Can we enforce to a single property? If the designer wants to enable
>>>> this feature, he/she can to provide the tx-fifo-max-num. This would
>>>> simplify the driver a bit. Since this is to optimize for performance,
>>>> the user should know/want/test the specific value if they want to set
>>>> for their setup and not hoping that the default setting not break their
>>>> setup. So we can remove the "do_fifo_resize" property and just check
>>>> whether tx_fifo_resize_max_num is set.
>>>
>>> Ack!
>>>
>>> All very valid points :-)
>>>

Hi Thinh/Felipe,

>>
>> Looks like this series already landed in Greg's testing branch. Not sure
>> how we usually handle this to address some of our concerns. Add fix
>> patches on top of Greg's testing branch?
> 
> yup, no choice anymore :-(
> 

Let me review your feedback, which had some good points.  We can add a
change addressing everything on top of what is merged on Greg's branch.
 Thanks for all the input!

Thanks
Wesley Cheng

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
  2021-07-14  7:30           ` Wesley Cheng
@ 2021-07-20 11:41             ` gregkh
  2021-07-21  6:23               ` Wesley Cheng
  0 siblings, 1 reply; 18+ messages in thread
From: gregkh @ 2021-07-20 11:41 UTC (permalink / raw)
  To: Wesley Cheng
  Cc: Felipe Balbi, Thinh Nguyen, agross, bjorn.andersson, robh+dt,
	frowand.list, linux-usb, linux-kernel, linux-arm-msm, devicetree,
	jackp

On Wed, Jul 14, 2021 at 12:30:07AM -0700, Wesley Cheng wrote:
> 
> 
> On 7/13/2021 11:40 PM, Felipe Balbi wrote:
> > 
> > Hi,
> > 
> > Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
> >>> Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
> >>>> Wesley Cheng wrote:
> >>>>> Some devices have USB compositions which may require multiple endpoints
> >>>>> that support EP bursting.  HW defined TX FIFO sizes may not always be
> >>>>> sufficient for these compositions.  By utilizing flexible TX FIFO
> >>>>> allocation, this allows for endpoints to request the required FIFO depth to
> >>>>> achieve higher bandwidth.  With some higher bMaxBurst configurations, using
> >>>>> a larger TX FIFO size results in better TX throughput.
> >>>>>
> >>>>> By introducing the check_config() callback, the resizing logic can fetch
> >>>>> the maximum number of endpoints used in the USB composition (can contain
> >>>>> multiple configurations), which helps ensure that the resizing logic can
> >>>>> fulfill the configuration(s), or return an error to the gadget layer
> >>>>> otherwise during bind time.
> >>>>>
> >>>>> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
> >>>>> ---
> >>>>>  drivers/usb/dwc3/core.c   |  15 +++
> >>>>>  drivers/usb/dwc3/core.h   |  16 ++++
> >>>>>  drivers/usb/dwc3/ep0.c    |   2 +
> >>>>>  drivers/usb/dwc3/gadget.c | 232 ++++++++++++++++++++++++++++++++++++++++++++++
> >>>>>  4 files changed, 265 insertions(+)
> >>>>>
> >>>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> >>>>> index ba74ad7..b194aecd 100644
> >>>>> --- a/drivers/usb/dwc3/core.c
> >>>>> +++ b/drivers/usb/dwc3/core.c
> >>>>> @@ -1267,6 +1267,7 @@ static void dwc3_get_properties(struct dwc3 *dwc)
> >>>>>  	u8			rx_max_burst_prd;
> >>>>>  	u8			tx_thr_num_pkt_prd;
> >>>>>  	u8			tx_max_burst_prd;
> >>>>> +	u8			tx_fifo_resize_max_num;
> >>>>>  	const char		*usb_psy_name;
> >>>>>  	int			ret;
> >>>>>  
> >>>>> @@ -1282,6 +1283,13 @@ static void dwc3_get_properties(struct dwc3 *dwc)
> >>>>>  	 */
> >>>>>  	hird_threshold = 12;
> >>>>>  
> >>>>> +	/*
> >>>>> +	 * default to a TXFIFO size large enough to fit 6 max packets.  This
> >>>>> +	 * allows for systems with larger bus latencies to have some headroom
> >>>>> +	 * for endpoints that have a large bMaxBurst value.
> >>>>> +	 */
> >>>>> +	tx_fifo_resize_max_num = 6;
> >>>>> +
> >>>>>  	dwc->maximum_speed = usb_get_maximum_speed(dev);
> >>>>>  	dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
> >>>>>  	dwc->dr_mode = usb_get_dr_mode(dev);
> >>>>> @@ -1325,6 +1333,11 @@ static void dwc3_get_properties(struct dwc3 *dwc)
> >>>>>  				&tx_thr_num_pkt_prd);
> >>>>>  	device_property_read_u8(dev, "snps,tx-max-burst-prd",
> >>>>>  				&tx_max_burst_prd);
> >>>>> +	dwc->do_fifo_resize = device_property_read_bool(dev,
> >>>>> +							"tx-fifo-resize");
> >>>>> +	if (dwc->do_fifo_resize)
> >>>>> +		device_property_read_u8(dev, "tx-fifo-max-num",
> >>>>> +					&tx_fifo_resize_max_num);
> >>>>
> >>>> Why is this check here? The dwc->tx_fifo_resize_max_num should store
> >>>> whatever property the user sets. Whether the driver wants to use this
> >>>
> >>> Ack!
> >>>
> >>>> property should depend on "dwc->do_fifo_resize". Also why don't we have
> >>>> "snps," prefix to be consistent with the other properties?
> >>>
> >>> Ack!
> >>>
> >>>> Can we enforce to a single property? If the designer wants to enable
> >>>> this feature, he/she can to provide the tx-fifo-max-num. This would
> >>>> simplify the driver a bit. Since this is to optimize for performance,
> >>>> the user should know/want/test the specific value if they want to set
> >>>> for their setup and not hoping that the default setting not break their
> >>>> setup. So we can remove the "do_fifo_resize" property and just check
> >>>> whether tx_fifo_resize_max_num is set.
> >>>
> >>> Ack!
> >>>
> >>> All very valid points :-)
> >>>
> 
> Hi Thinh/Felipe,
> 
> >>
> >> Looks like this series already landed in Greg's testing branch. Not sure
> >> how we usually handle this to address some of our concerns. Add fix
> >> patches on top of Greg's testing branch?
> > 
> > yup, no choice anymore :-(
> > 
> 
> Let me review your feedback, which had some good points.  We can add a
> change addressing everything on top of what is merged on Greg's branch.

Any hint as to when these fixups will be sent?

thanks,

greg k-h

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
  2021-07-20 11:41             ` gregkh
@ 2021-07-21  6:23               ` Wesley Cheng
  0 siblings, 0 replies; 18+ messages in thread
From: Wesley Cheng @ 2021-07-21  6:23 UTC (permalink / raw)
  To: gregkh
  Cc: Felipe Balbi, Thinh Nguyen, agross, bjorn.andersson, robh+dt,
	frowand.list, linux-usb, linux-kernel, linux-arm-msm, devicetree,
	jackp



On 7/20/2021 4:41 AM, gregkh@linuxfoundation.org wrote:
> On Wed, Jul 14, 2021 at 12:30:07AM -0700, Wesley Cheng wrote:
>>
>>
>> On 7/13/2021 11:40 PM, Felipe Balbi wrote:
>>>
>>> Hi,
>>>
>>> Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
>>>>> Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
>>>>>> Wesley Cheng wrote:
>>>>>>> Some devices have USB compositions which may require multiple endpoints
>>>>>>> that support EP bursting.  HW defined TX FIFO sizes may not always be
>>>>>>> sufficient for these compositions.  By utilizing flexible TX FIFO
>>>>>>> allocation, this allows for endpoints to request the required FIFO depth to
>>>>>>> achieve higher bandwidth.  With some higher bMaxBurst configurations, using
>>>>>>> a larger TX FIFO size results in better TX throughput.
>>>>>>>
>>>>>>> By introducing the check_config() callback, the resizing logic can fetch
>>>>>>> the maximum number of endpoints used in the USB composition (can contain
>>>>>>> multiple configurations), which helps ensure that the resizing logic can
>>>>>>> fulfill the configuration(s), or return an error to the gadget layer
>>>>>>> otherwise during bind time.
>>>>>>>
>>>>>>> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
>>>>>>> ---
>>>>>>>  drivers/usb/dwc3/core.c   |  15 +++
>>>>>>>  drivers/usb/dwc3/core.h   |  16 ++++
>>>>>>>  drivers/usb/dwc3/ep0.c    |   2 +
>>>>>>>  drivers/usb/dwc3/gadget.c | 232 ++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>  4 files changed, 265 insertions(+)
>>>>>>>
>>>>>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>>>>>>> index ba74ad7..b194aecd 100644
>>>>>>> --- a/drivers/usb/dwc3/core.c
>>>>>>> +++ b/drivers/usb/dwc3/core.c
>>>>>>> @@ -1267,6 +1267,7 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>>>>>>  	u8			rx_max_burst_prd;
>>>>>>>  	u8			tx_thr_num_pkt_prd;
>>>>>>>  	u8			tx_max_burst_prd;
>>>>>>> +	u8			tx_fifo_resize_max_num;
>>>>>>>  	const char		*usb_psy_name;
>>>>>>>  	int			ret;
>>>>>>>  
>>>>>>> @@ -1282,6 +1283,13 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>>>>>>  	 */
>>>>>>>  	hird_threshold = 12;
>>>>>>>  
>>>>>>> +	/*
>>>>>>> +	 * default to a TXFIFO size large enough to fit 6 max packets.  This
>>>>>>> +	 * allows for systems with larger bus latencies to have some headroom
>>>>>>> +	 * for endpoints that have a large bMaxBurst value.
>>>>>>> +	 */
>>>>>>> +	tx_fifo_resize_max_num = 6;
>>>>>>> +
>>>>>>>  	dwc->maximum_speed = usb_get_maximum_speed(dev);
>>>>>>>  	dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
>>>>>>>  	dwc->dr_mode = usb_get_dr_mode(dev);
>>>>>>> @@ -1325,6 +1333,11 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>>>>>>>  				&tx_thr_num_pkt_prd);
>>>>>>>  	device_property_read_u8(dev, "snps,tx-max-burst-prd",
>>>>>>>  				&tx_max_burst_prd);
>>>>>>> +	dwc->do_fifo_resize = device_property_read_bool(dev,
>>>>>>> +							"tx-fifo-resize");
>>>>>>> +	if (dwc->do_fifo_resize)
>>>>>>> +		device_property_read_u8(dev, "tx-fifo-max-num",
>>>>>>> +					&tx_fifo_resize_max_num);
>>>>>>
>>>>>> Why is this check here? The dwc->tx_fifo_resize_max_num should store
>>>>>> whatever property the user sets. Whether the driver wants to use this
>>>>>
>>>>> Ack!
>>>>>
>>>>>> property should depend on "dwc->do_fifo_resize". Also why don't we have
>>>>>> "snps," prefix to be consistent with the other properties?
>>>>>
>>>>> Ack!
>>>>>
>>>>>> Can we enforce to a single property? If the designer wants to enable
>>>>>> this feature, he/she can to provide the tx-fifo-max-num. This would
>>>>>> simplify the driver a bit. Since this is to optimize for performance,
>>>>>> the user should know/want/test the specific value if they want to set
>>>>>> for their setup and not hoping that the default setting not break their
>>>>>> setup. So we can remove the "do_fifo_resize" property and just check
>>>>>> whether tx_fifo_resize_max_num is set.
>>>>>
>>>>> Ack!
>>>>>
>>>>> All very valid points :-)
>>>>>
>>
>> Hi Thinh/Felipe,
>>
>>>>
>>>> Looks like this series already landed in Greg's testing branch. Not sure
>>>> how we usually handle this to address some of our concerns. Add fix
>>>> patches on top of Greg's testing branch?
>>>
>>> yup, no choice anymore :-(
>>>
>>
>> Let me review your feedback, which had some good points.  We can add a
>> change addressing everything on top of what is merged on Greg's branch.

Hi Greg,

> 
> Any hint as to when these fixups will be sent?
> 

Will get something by mid-week next week.  Sorry have been occupied with
tasks on my end.

Thanks
Wesley Cheng


-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 18+ messages in thread

end of thread, other threads:[~2021-07-21  6:24 UTC | newest]

Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-10  9:13 [PATCH v14 0/6] Re-introduce TX FIFO resize for larger EP bursting Wesley Cheng
2021-07-10  9:13 ` [PATCH v14 1/6] usb: gadget: udc: core: Introduce check_config to verify USB configuration Wesley Cheng
2021-07-10  9:13 ` [PATCH v14 2/6] usb: gadget: configfs: Check USB configuration before adding Wesley Cheng
2021-07-10  9:13 ` [PATCH v14 3/6] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements Wesley Cheng
2021-07-12 23:38   ` Thinh Nguyen
2021-07-13  8:39     ` Felipe Balbi
2021-07-14  2:58       ` Thinh Nguyen
2021-07-14  3:10       ` Thinh Nguyen
2021-07-14  6:40         ` Felipe Balbi
2021-07-14  6:52           ` gregkh
2021-07-14  7:30           ` Wesley Cheng
2021-07-20 11:41             ` gregkh
2021-07-21  6:23               ` Wesley Cheng
2021-07-14  6:51         ` gregkh
2021-07-14  2:59     ` Thinh Nguyen
2021-07-10  9:13 ` [PATCH v14 4/6] of: Add stub for of_add_property() Wesley Cheng
2021-07-10  9:13 ` [PATCH v14 5/6] usb: dwc3: dwc3-qcom: Enable tx-fifo-resize property by default Wesley Cheng
2021-07-10  9:13 ` [PATCH v14 6/6] dt-bindings: usb: dwc3: Update dwc3 TX fifo properties Wesley Cheng

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