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bh=NVfxW8ZqI2b6FGynZRDCjC85/X3SP72iBuprA7dn0yk=; b=d5Y0W8Fr/U4H7dOmU/fks93O0w+kHnQ6I4YiPBmqbbFvUyj5BEB9wiCLMARAod+1nb mMnPrTEh5twLKLekFXDVZKbCb5UxS270KJLpP3XBSmGklFMKoJde/w+3gNhu7yUY9K4v bzy4Y0fiufw825KUoIE0RV7Y739F0cmz10ywLFui+cuavvaAXVMgtMTSp2sFYV7MZHqL gJQgK/WEg9HeaB4VunjM0VXsA0wvOao8ZuWioaYMgj0JejfFlQpzeT/NVvGcqa0ur4+t /CyDKiWX15qAuwEAphXK8MNox/DukRVuRq/Tgy+67LgYVstq9k0FeflgwxN5VcZ7DEJw RuEw== X-Gm-Message-State: AOAM531wszDij2D9FgmdrTUS7lLJFTdTh4BIFgL8C1ralnZhMcor8xm8 JHL6KDaVSMkf3OwpOxs1EQc= X-Google-Smtp-Source: ABdhPJxfs/BlYLDiSH1Jn2j7YToE9+PRsqW4+qCtdXdA4zgAUUgY+mVfkljr1SwT48mSN1FvSLetgQ== X-Received: by 2002:a17:90a:e513:: with SMTP id t19mr3499004pjy.104.1626341084147; Thu, 15 Jul 2021 02:24:44 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([137.59.103.165]) by smtp.gmail.com with ESMTPSA id 11sm6662503pge.7.2021.07.15.02.24.39 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Jul 2021 02:24:43 -0700 (PDT) From: dillon.minfei@gmail.com To: mchehab@kernel.org, mchehab+huawei@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@collabora.com, gnurou@gmail.com, pihsun@chromium.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: patrice.chotard@foss.st.com, hugues.fruchet@foss.st.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Dillon Min Subject: [PATCH v2 2/9] media: dt-bindings: media: add document for STM32 DMA2d bindings Date: Thu, 15 Jul 2021 17:24:11 +0800 Message-Id: <1626341068-20253-3-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1626341068-20253-1-git-send-email-dillon.minfei@gmail.com> References: <1626341068-20253-1-git-send-email-dillon.minfei@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dillon Min This adds documentation of device tree bindings for the STM32 DMA2D Signed-off-by: Dillon Min Reviewed-by: Rob Herring --- v2: add Reviewed-by tag. .../devicetree/bindings/media/st,stm32-dma2d.yaml | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/st,stm32-dma2d.yaml diff --git a/Documentation/devicetree/bindings/media/st,stm32-dma2d.yaml b/Documentation/devicetree/bindings/media/st,stm32-dma2d.yaml new file mode 100644 index 000000000000..f97b4a246605 --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,stm32-dma2d.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/st,stm32-dma2d.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Chrom-Art Accelerator DMA2D binding + +description: + Chrom-ART Accelerator(DMA2D), graphical hardware accelerator + enabling enhanced graphical user interface with minimum CPU load + + It can perform the following operations. + + - Filling a part or the whole of a destination image with a specific color. + - Copying a part or the whole of a source image into a part or the whole of + a destination image. + - Copying a part or the whole of a source image into a part or the whole of + a destination image with a pixel format conversion. + - Blending a part and/or two complete source images with different pixel + format and copy the result into a part or the whole of a destination image + with a different color format. (TODO) + + +maintainers: + - Dillon Min + +properties: + compatible: + const: st,stm32-dma2d + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: dma2d + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include + #include + dma2d: dma2d@4002b000 { + compatible = "st,stm32-dma2d"; + reg = <0x4002b000 0xc00>; + interrupts = <90>; + resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>; + clock-names = "dma2d"; + }; + +... -- 2.7.4