From: Rajendra Nayak <rnayak@codeaurora.org>
To: ulf.hansson@linaro.org, bjorn.andersson@linaro.org,
viresh.kumar@linaro.org
Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
swboyd@chromium.org, rojay@codeaurora.org, stephan@gerhold.net,
Rajendra Nayak <rnayak@codeaurora.org>
Subject: [PATCH v4 2/2] arm64: dts: sc7180: Add required-opps for i2c
Date: Fri, 16 Jul 2021 15:30:58 +0530 [thread overview]
Message-ID: <1626429658-18961-3-git-send-email-rnayak@codeaurora.org> (raw)
In-Reply-To: <1626429658-18961-1-git-send-email-rnayak@codeaurora.org>
qup-i2c devices on sc7180 are clocked with a fixed clock (19.2 MHz)
Though qup-i2c does not support DVFS, it still needs to vote for a
performance state on 'CX' to satisfy the 19.2 Mhz clock frequency
requirement.
Use 'required-opps' to pass this information from
device tree, and also add the power-domains property to specify
the CX power-domain.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index a5d58eb..cd30185 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -785,8 +785,10 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
spi0: spi@880000 {
@@ -837,8 +839,10 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
spi1: spi@884000 {
@@ -889,8 +893,10 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
uart2: serial@888000 {
@@ -923,8 +929,10 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
spi3: spi@88c000 {
@@ -975,8 +983,10 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
uart4: serial@890000 {
@@ -1009,8 +1019,10 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
spi5: spi@894000 {
@@ -1074,8 +1086,10 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
spi6: spi@a80000 {
@@ -1126,8 +1140,10 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
uart7: serial@a84000 {
@@ -1160,8 +1176,10 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
spi8: spi@a88000 {
@@ -1212,8 +1230,10 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
uart9: serial@a8c000 {
@@ -1246,8 +1266,10 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
spi10: spi@a90000 {
@@ -1298,8 +1320,10 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
spi11: spi@a94000 {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2021-07-16 10:02 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-16 10:00 [PATCH v4 0/2] PM / Domains: Add support for 'required-opps' to set default perf state Rajendra Nayak
2021-07-16 10:00 ` [PATCH v4 1/2] " Rajendra Nayak
2021-07-16 20:19 ` Stephen Boyd
2021-07-19 11:50 ` Rajendra Nayak
2021-07-16 10:00 ` Rajendra Nayak [this message]
2021-07-16 19:39 ` [PATCH v4 2/2] arm64: dts: sc7180: Add required-opps for i2c Stephen Boyd
2021-07-16 20:18 ` Bjorn Andersson
2021-07-16 20:21 ` Stephen Boyd
2021-07-16 20:52 ` Bjorn Andersson
2021-07-16 21:49 ` Stephen Boyd
2021-07-16 21:59 ` Bjorn Andersson
2021-07-19 9:37 ` Rajendra Nayak
2021-07-19 19:19 ` Bjorn Andersson
2021-07-20 4:29 ` Rajendra Nayak
2021-07-25 17:01 ` Bjorn Andersson
2021-07-27 7:35 ` Rajendra Nayak
2021-07-28 3:46 ` Bjorn Andersson
2021-07-28 14:01 ` Dmitry Baryshkov
2021-07-28 18:47 ` Bjorn Andersson
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