* [PATCH V2 0/3] Add initial Thunder Bay SoC / Board support
@ 2021-07-20 5:22 kenchappa.demakkanavar
2021-07-20 5:22 ` [PATCH V2 1/3] arm64: Add config for Thunder Bay SoC kenchappa.demakkanavar
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: kenchappa.demakkanavar @ 2021-07-20 5:22 UTC (permalink / raw)
To: will, linux-arm-kernel, linux-kernel, robh+dt, devicetree, dinguyen
Cc: furong.zhou, kris.pan, kris.pan, mgross, mark.gross,
Demakkanavar, Kenchappa
From: "Demakkanavar, Kenchappa" <kenchappa.demakkanavar@intel.com>
Hi,
This patch-set adds initial support for a new Intel Movidius SoC
code-named Thunder Bay. The SoC couples an ARM Cortex A53 CPU
with an Intel Movidius VPU.
This initial patch-set enables only the minimal set of components
required to make the Thunder Bay full or prime configuration boards
boot into initramfs.
Thunder Bay full configuration board has 4 clusters of 4 ARM
Cortex A53 CPUs per cluster, 4 VPU processors and
(8GB + 8GB + 4GB + 4GB) DDR memory.
Thunder Bay prime configuration board has 4 clusters of 4 ARM
Cortex A53 CPUs per cluster, 2 VPU processors and
(8GB + 4GB) DDR memory.
Changes from v1 to v2:
* Commit message updated for patch 3/3
* UART0 enabled by default for all Thunder Bay boards
Regards,
Kenchappa S. D.
Demakkanavar, Kenchappa (2):
arm64: Add config for Thunder Bay SoC
arm64: dts: add initial device tree for Thunder Bay SoC
Pan, Kris (1):
dt-bindings: arm: Add Thunder Bay bindings
.../devicetree/bindings/arm/intel,thunderbay.yaml | 21 ++
MAINTAINERS | 7 +
arch/arm64/Kconfig.platforms | 5 +
arch/arm64/boot/dts/intel/Makefile | 6 +
arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts | 43 ++++
arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts | 43 ++++
arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts | 43 ++++
arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts | 43 ++++
arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts | 54 +++++
arch/arm64/boot/dts/intel/thunderbay-soc.dtsi | 243 +++++++++++++++++++++
10 files changed, 508 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/intel,thunderbay.yaml
create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts
create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts
create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts
create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts
create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts
create mode 100644 arch/arm64/boot/dts/intel/thunderbay-soc.dtsi
--
2.7.4
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH V2 1/3] arm64: Add config for Thunder Bay SoC 2021-07-20 5:22 [PATCH V2 0/3] Add initial Thunder Bay SoC / Board support kenchappa.demakkanavar @ 2021-07-20 5:22 ` kenchappa.demakkanavar 2021-07-20 5:22 ` [PATCH V2 2/3] dt-bindings: arm: Add Thunder Bay bindings kenchappa.demakkanavar 2021-07-20 5:22 ` [PATCH V2 3/3] arm64: dts: add initial device tree for Thunder Bay SoC kenchappa.demakkanavar 2 siblings, 0 replies; 7+ messages in thread From: kenchappa.demakkanavar @ 2021-07-20 5:22 UTC (permalink / raw) To: will, linux-arm-kernel, linux-kernel, robh+dt, devicetree, dinguyen Cc: furong.zhou, kris.pan, kris.pan, mgross, mark.gross, Demakkanavar, Kenchappa From: "Demakkanavar, Kenchappa" <kenchappa.demakkanavar@intel.com> Add ARCH_THUNDERBAY configuration option to support Intel Movidius SoC code-named Thunder Bay Signed-off-by: Demakkanavar, Kenchappa <kenchappa.demakkanavar@intel.com> --- arch/arm64/Kconfig.platforms | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6409b47..8a043e2 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -154,6 +154,11 @@ config ARCH_KEEMBAY help This enables support for Intel Movidius SoC code-named Keem Bay. +config ARCH_THUNDERBAY + bool "Thunder Bay SoC" + help + This enables support for Intel Movidius SoC code-named Thunder Bay. + config ARCH_MEDIATEK bool "MediaTek SoC Family" select ARM_GIC -- 2.7.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH V2 2/3] dt-bindings: arm: Add Thunder Bay bindings 2021-07-20 5:22 [PATCH V2 0/3] Add initial Thunder Bay SoC / Board support kenchappa.demakkanavar 2021-07-20 5:22 ` [PATCH V2 1/3] arm64: Add config for Thunder Bay SoC kenchappa.demakkanavar @ 2021-07-20 5:22 ` kenchappa.demakkanavar 2021-07-29 19:40 ` Rob Herring 2021-07-20 5:22 ` [PATCH V2 3/3] arm64: dts: add initial device tree for Thunder Bay SoC kenchappa.demakkanavar 2 siblings, 1 reply; 7+ messages in thread From: kenchappa.demakkanavar @ 2021-07-20 5:22 UTC (permalink / raw) To: will, linux-arm-kernel, linux-kernel, robh+dt, devicetree, dinguyen Cc: furong.zhou, kris.pan, kris.pan, mgross, mark.gross, Demakkanavar, Kenchappa From: "Pan, Kris" <kris.pan@intel.com> Document Intel Movidius SoC code-named Thunder Bay, along with the Thunder Bay Full and Prime configuration board. Add maintainers for the new Intel Movidius SoC code-named Thunder Bay. Signed-off-by: Pan, Kris <kris.pan@intel.com> Signed-off-by: Demakkanavar, Kenchappa <kenchappa.demakkanavar@intel.com> --- .../devicetree/bindings/arm/intel,thunderbay.yaml | 21 +++++++++++++++++++++ MAINTAINERS | 5 +++++ 2 files changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/intel,thunderbay.yaml diff --git a/Documentation/devicetree/bindings/arm/intel,thunderbay.yaml b/Documentation/devicetree/bindings/arm/intel,thunderbay.yaml new file mode 100644 index 0000000..2b9d5f6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/intel,thunderbay.yaml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/intel,thunderbay.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Thunder Bay platform device tree bindings + +maintainers: + - Demakkanavar, Kenchappa <kenchappa.demakkanavar@intel.com> + +properties: + compatible: + items: + - enum: + - intel,thunderbay + - const: intel,thunderbay + +additionalProperties: true + +... diff --git a/MAINTAINERS b/MAINTAINERS index 503fd21..041f9a0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1992,6 +1992,11 @@ S: Maintained F: arch/arm/mach-pxa/stargate2.c F: drivers/pcmcia/pxa2xx_stargate2.c +ARM/INTEL THUNDERBAY ARCHITECTURE +M: Demakkanavar, Kenchappa <kenchappa.demakkanavar@intel.com> +S: Maintained +F: Documentation/devicetree/bindings/arm/intel,thunderbay.yaml + ARM/INTEL XSC3 (MANZANO) ARM CORE M: Lennert Buytenhek <kernel@wantstofly.org> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- 2.7.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH V2 2/3] dt-bindings: arm: Add Thunder Bay bindings 2021-07-20 5:22 ` [PATCH V2 2/3] dt-bindings: arm: Add Thunder Bay bindings kenchappa.demakkanavar @ 2021-07-29 19:40 ` Rob Herring 0 siblings, 0 replies; 7+ messages in thread From: Rob Herring @ 2021-07-29 19:40 UTC (permalink / raw) To: kenchappa.demakkanavar Cc: will, linux-arm-kernel, linux-kernel, devicetree, dinguyen, furong.zhou, kris.pan, kris.pan, mgross, mark.gross On Tue, Jul 20, 2021 at 10:52:48AM +0530, kenchappa.demakkanavar@intel.com wrote: > From: "Pan, Kris" <kris.pan@intel.com> Kris Pan <kris.pan@intel.com> > > Document Intel Movidius SoC code-named Thunder Bay, along with the > Thunder Bay Full and Prime configuration board. > > Add maintainers for the new Intel Movidius SoC code-named Thunder Bay. > > Signed-off-by: Pan, Kris <kris.pan@intel.com> > Signed-off-by: Demakkanavar, Kenchappa <kenchappa.demakkanavar@intel.com> "First name last name" here too. > --- > .../devicetree/bindings/arm/intel,thunderbay.yaml | 21 +++++++++++++++++++++ > MAINTAINERS | 5 +++++ > 2 files changed, 26 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/intel,thunderbay.yaml > > diff --git a/Documentation/devicetree/bindings/arm/intel,thunderbay.yaml b/Documentation/devicetree/bindings/arm/intel,thunderbay.yaml > new file mode 100644 > index 0000000..2b9d5f6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/intel,thunderbay.yaml > @@ -0,0 +1,21 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/intel,thunderbay.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Thunder Bay platform device tree bindings > + > +maintainers: > + - Demakkanavar, Kenchappa <kenchappa.demakkanavar@intel.com> ditto > + > +properties: > + compatible: > + items: > + - enum: > + - intel,thunderbay > + - const: intel,thunderbay Not valid to have duplicate strings. Like everyone else, you need $nodename schema here to define this is for the root node. > + > +additionalProperties: true > + > +... > diff --git a/MAINTAINERS b/MAINTAINERS > index 503fd21..041f9a0 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1992,6 +1992,11 @@ S: Maintained > F: arch/arm/mach-pxa/stargate2.c > F: drivers/pcmcia/pxa2xx_stargate2.c > > +ARM/INTEL THUNDERBAY ARCHITECTURE > +M: Demakkanavar, Kenchappa <kenchappa.demakkanavar@intel.com> > +S: Maintained > +F: Documentation/devicetree/bindings/arm/intel,thunderbay.yaml > + > ARM/INTEL XSC3 (MANZANO) ARM CORE > M: Lennert Buytenhek <kernel@wantstofly.org> > L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) > -- > 2.7.4 > > ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH V2 3/3] arm64: dts: add initial device tree for Thunder Bay SoC 2021-07-20 5:22 [PATCH V2 0/3] Add initial Thunder Bay SoC / Board support kenchappa.demakkanavar 2021-07-20 5:22 ` [PATCH V2 1/3] arm64: Add config for Thunder Bay SoC kenchappa.demakkanavar 2021-07-20 5:22 ` [PATCH V2 2/3] dt-bindings: arm: Add Thunder Bay bindings kenchappa.demakkanavar @ 2021-07-20 5:22 ` kenchappa.demakkanavar 2021-07-29 19:53 ` Rob Herring 2 siblings, 1 reply; 7+ messages in thread From: kenchappa.demakkanavar @ 2021-07-20 5:22 UTC (permalink / raw) To: will, linux-arm-kernel, linux-kernel, robh+dt, devicetree, dinguyen Cc: furong.zhou, kris.pan, kris.pan, mgross, mark.gross, Demakkanavar, Kenchappa From: "Demakkanavar, Kenchappa" <kenchappa.demakkanavar@intel.com> Add initial device tree for Intel Movidius SoC code-named Thunder Bay. This initial DT includes nodes for 4 CPU clusters with 4 Cortex-A53 cores per cluster, UARTs, GIC, ARM Timer and PSCI. thunderbay-soc.dtsi - Thunder Bay SoC dtsi file hddl_hybrid_4s.dts - Thunder Bay full configuration board dts with 4 VPU processors hddl_hybrid_2s_02.dts - Thunder Bay prime configuration board dts with 2 VPU processors (slice 0 and slice 2 enabled) hddl_hybrid_2s_03.dts - Thunder Bay prime configuration board dts with 2 VPU processors (slice 0 and slice 3 enabled) hddl_hybrid_2s_12.dts - Thunder Bay prime configuration board dts with 2 VPU processors (slice 1 and slice 2 enabled) hddl_hybrid_2s_13.dts - Thunder Bay prime configuration board dts with 2 VPU processors (slice 1 and slice 3 enabled) Signed-off-by: Demakkanavar, Kenchappa <kenchappa.demakkanavar@intel.com> --- MAINTAINERS | 2 + arch/arm64/boot/dts/intel/Makefile | 6 + arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts | 43 +++++ arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts | 43 +++++ arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts | 43 +++++ arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts | 43 +++++ arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts | 54 ++++++ arch/arm64/boot/dts/intel/thunderbay-soc.dtsi | 243 ++++++++++++++++++++++++ 8 files changed, 477 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts create mode 100644 arch/arm64/boot/dts/intel/thunderbay-soc.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 041f9a0..68317f0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1996,6 +1996,8 @@ ARM/INTEL THUNDERBAY ARCHITECTURE M: Demakkanavar, Kenchappa <kenchappa.demakkanavar@intel.com> S: Maintained F: Documentation/devicetree/bindings/arm/intel,thunderbay.yaml +F: arch/arm64/boot/dts/intel/hddl* +F: arch/arm64/boot/dts/intel/thunderbay-soc.dtsi ARM/INTEL XSC3 (MANZANO) ARM CORE M: Lennert Buytenhek <kernel@wantstofly.org> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 0b54774..767b74b 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -3,3 +3,9 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb + +dtb-$(CONFIG_ARCH_THUNDERBAY) += hddl_hybrid_4s.dtb \ + hddl_hybrid_2s_02.dtb \ + hddl_hybrid_2s_03.dtb \ + hddl_hybrid_2s_12.dtb \ + hddl_hybrid_2s_13.dtb diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts new file mode 100644 index 0000000..f907ddd --- /dev/null +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (c) 2021 Intel Corporation. + * + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime configuration + * board. + * + * DDR 8GB + 4GB with vpu slice 0 and vpu slice 2 + */ + +/dts-v1/; + +#include "thunderbay-soc.dtsi" + +/ { + model = "Intel Thunder Bay Hybrid HDDL Prime Board"; + compatible = "intel,thunderbay"; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@100A000000 { + device_type = "memory"; + /* 8GB of DDR memory */ + reg = <0x10 0x0A000000 0x2 0x0>; + }; + + memory@1200000000 { + device_type = "memory"; + /* 4GB of DDR memory */ + reg = <0x12 0x0 0x1 0x0>; + }; + +}; diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts new file mode 100644 index 0000000..01a3d4c --- /dev/null +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (c) 2021 Intel Corporation. + * + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime configuration + * board + * + * DDR 8GB + 4GB with vpu slice 0 and vpu slice 3 + */ + +/dts-v1/; + +#include "thunderbay-soc.dtsi" + +/ { + model = "Intel Thunder Bay Hybrid HDDL Prime Board"; + compatible = "intel,thunderbay"; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@100A000000 { + device_type = "memory"; + /* 8GB of DDR memory */ + reg = <0x10 0x0A000000 0x2 0x0>; + }; + + memory@1200000000 { + device_type = "memory"; + /* 4GB of DDR memory */ + reg = <0x12 0x0 0x1 0x0>; + }; + +}; diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts new file mode 100644 index 0000000..e31db16 --- /dev/null +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (c) 2021 Intel Corporation. + * + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime configuration + * board + * + * DDR 8GB + 4GB with vpu slice 1 and vpu slice 2 + */ + +/dts-v1/; + +#include "thunderbay-soc.dtsi" + +/ { + model = "Intel Thunder Bay Hybrid HDDL Prime Board"; + compatible = "intel,thunderbay"; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@100A000000 { + device_type = "memory"; + /* 8GB of DDR memory */ + reg = <0x10 0x0A000000 0x2 0x0>; + }; + + memory@1200000000 { + device_type = "memory"; + /* 4GB of DDR memory */ + reg = <0x12 0x0 0x1 0x0>; + }; + +}; diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts new file mode 100644 index 0000000..6529664 --- /dev/null +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (c) 2021 Intel Corporation. + * + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime configuration + * board + * + * DDR 8GB + 4GB with vpu slice 1 and vpu slice 3 + */ + +/dts-v1/; + +#include "thunderbay-soc.dtsi" + +/ { + model = "Intel Thunder Bay Hybrid HDDL Prime Board"; + compatible = "intel,thunderbay"; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@100A000000 { + device_type = "memory"; + /* 8GB of DDR memory */ + reg = <0x10 0x0A000000 0x2 0x0>; + }; + + memory@1200000000 { + device_type = "memory"; + /* 4GB of DDR memory */ + reg = <0x12 0x0 0x1 0x0>; + }; + +}; diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts b/arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts new file mode 100644 index 0000000..561ecea --- /dev/null +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (c) 2021 Intel Corporation. + * + * Device tree describing Intel Thunder Bay Hybrid HDDL Full configuration + * board + * + * DDR 8GB + 8GB + 4GB + 4GB with four vpu slices + */ + +/dts-v1/; + +#include "thunderbay-soc.dtsi" + +/ { + model = "Intel Thunder Bay Hybrid HDDL Full Board"; + compatible = "intel,thunderbay"; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@100A000000 { + device_type = "memory"; + /* 8GB of DDR memory */ + reg = <0x10 0x0A000000 0x2 0x0>; + }; + + memory@1200000000 { + device_type = "memory"; + /* 8GB of DDR memory */ + reg = <0x12 0x0 0x2 0x0>; + }; + + memory@1400000000 { + device_type = "memory"; + /* 4GB of DDR memory */ + reg = <0x14 0x0 0x1 0x0>; + }; + + memory@1500000000 { + device_type = "memory"; + /* 4GB of DDR memory */ + reg = <0x15 0x0 0x1 0x0>; + }; +}; diff --git a/arch/arm64/boot/dts/intel/thunderbay-soc.dtsi b/arch/arm64/boot/dts/intel/thunderbay-soc.dtsi new file mode 100644 index 0000000..834200d --- /dev/null +++ b/arch/arm64/boot/dts/intel/thunderbay-soc.dtsi @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (c) 2021 Intel Corporation. + * + * Device tree describing Thunder Bay SoC + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + + compatible = "intel,thunderbay"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + cluster2 { + core0 { + cpu = <&CPU8>; + }; + core1 { + cpu = <&CPU9>; + }; + core2 { + cpu = <&CPU10>; + }; + core3 { + cpu = <&CPU11>; + }; + }; + cluster3 { + core0 { + cpu = <&CPU12>; + }; + core1 { + cpu = <&CPU13>; + }; + core2 { + cpu = <&CPU14>; + }; + core3 { + cpu = <&CPU15>; + }; + }; + }; + + CPU0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + CPU1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + CPU2: cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + CPU3: cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + + CPU4: cpu@100 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + + CPU5: cpu@101 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x101>; + enable-method = "psci"; + }; + + CPU6: cpu@102 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x102>; + enable-method = "psci"; + }; + + CPU7: cpu@103 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x103>; + enable-method = "psci"; + }; + + CPU8: cpu@200 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x200>; + enable-method = "psci"; + }; + + CPU9: cpu@201 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x201>; + enable-method = "psci"; + }; + + CPU10: cpu@202 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x202>; + enable-method = "psci"; + }; + + CPU11: cpu@203 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x203>; + enable-method = "psci"; + }; + + CPU12: cpu@300 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x300>; + enable-method = "psci"; + }; + + CPU13: cpu@301 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x301>; + enable-method = "psci"; + }; + + CPU14: cpu@302 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x302>; + enable-method = "psci"; + }; + + CPU15: cpu@303 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x303>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller@88400000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x88400000 0x0 0x200000>, /* GICD */ + <0x0 0x88600000 0x0 0x200000>; /* GICR */ + /* VGIC maintenance interrupt */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Secure, non-secure, virtual, and hypervisor */ + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + uart0: serial@80460000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x80460000 0x0 0x100>; + interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <50000000>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart1: serial@80470000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x80470000 0x0 0x100>; + interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <50000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + }; +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH V2 3/3] arm64: dts: add initial device tree for Thunder Bay SoC 2021-07-20 5:22 ` [PATCH V2 3/3] arm64: dts: add initial device tree for Thunder Bay SoC kenchappa.demakkanavar @ 2021-07-29 19:53 ` Rob Herring 2021-08-27 7:55 ` Demakkanavar, Kenchappa 0 siblings, 1 reply; 7+ messages in thread From: Rob Herring @ 2021-07-29 19:53 UTC (permalink / raw) To: kenchappa.demakkanavar Cc: will, linux-arm-kernel, linux-kernel, devicetree, dinguyen, furong.zhou, kris.pan, kris.pan, mgross, mark.gross On Tue, Jul 20, 2021 at 10:52:49AM +0530, kenchappa.demakkanavar@intel.com wrote: > From: "Demakkanavar, Kenchappa" <kenchappa.demakkanavar@intel.com> > > Add initial device tree for Intel Movidius SoC code-named Thunder Bay. > > This initial DT includes nodes for 4 CPU clusters with 4 Cortex-A53 > cores per cluster, UARTs, GIC, ARM Timer and PSCI. Make sure you run 'make dtbs_check' on these. There shouldn't be any dtc warnings and or undocumented compatible warnings at a minimum. > thunderbay-soc.dtsi - Thunder Bay SoC dtsi file > hddl_hybrid_4s.dts - Thunder Bay full configuration board dts > with 4 VPU processors > hddl_hybrid_2s_02.dts - Thunder Bay prime configuration board dts with > 2 VPU processors (slice 0 and slice 2 enabled) > hddl_hybrid_2s_03.dts - Thunder Bay prime configuration board dts with > 2 VPU processors (slice 0 and slice 3 enabled) > hddl_hybrid_2s_12.dts - Thunder Bay prime configuration board dts with > 2 VPU processors (slice 1 and slice 2 enabled) > hddl_hybrid_2s_13.dts - Thunder Bay prime configuration board dts with > 2 VPU processors (slice 1 and slice 3 enabled) > > Signed-off-by: Demakkanavar, Kenchappa <kenchappa.demakkanavar@intel.com> > --- > MAINTAINERS | 2 + > arch/arm64/boot/dts/intel/Makefile | 6 + > arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts | 43 +++++ > arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts | 43 +++++ > arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts | 43 +++++ > arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts | 43 +++++ > arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts | 54 ++++++ > arch/arm64/boot/dts/intel/thunderbay-soc.dtsi | 243 ++++++++++++++++++++++++ > 8 files changed, 477 insertions(+) > create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts > create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts > create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts > create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts > create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts > create mode 100644 arch/arm64/boot/dts/intel/thunderbay-soc.dtsi > > diff --git a/MAINTAINERS b/MAINTAINERS > index 041f9a0..68317f0 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1996,6 +1996,8 @@ ARM/INTEL THUNDERBAY ARCHITECTURE > M: Demakkanavar, Kenchappa <kenchappa.demakkanavar@intel.com> > S: Maintained > F: Documentation/devicetree/bindings/arm/intel,thunderbay.yaml > +F: arch/arm64/boot/dts/intel/hddl* > +F: arch/arm64/boot/dts/intel/thunderbay-soc.dtsi > > ARM/INTEL XSC3 (MANZANO) ARM CORE > M: Lennert Buytenhek <kernel@wantstofly.org> > diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile > index 0b54774..767b74b 100644 > --- a/arch/arm64/boot/dts/intel/Makefile > +++ b/arch/arm64/boot/dts/intel/Makefile > @@ -3,3 +3,9 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \ > socfpga_agilex_socdk_nand.dtb \ > socfpga_n5x_socdk.dtb > dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb > + > +dtb-$(CONFIG_ARCH_THUNDERBAY) += hddl_hybrid_4s.dtb \ > + hddl_hybrid_2s_02.dtb \ > + hddl_hybrid_2s_03.dtb \ > + hddl_hybrid_2s_12.dtb \ > + hddl_hybrid_2s_13.dtb > diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts > new file mode 100644 > index 0000000..f907ddd > --- /dev/null > +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts > @@ -0,0 +1,43 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > +/* > + * Copyright (c) 2021 Intel Corporation. > + * > + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime configuration > + * board. > + * > + * DDR 8GB + 4GB with vpu slice 0 and vpu slice 2 > + */ > + > +/dts-v1/; > + > +#include "thunderbay-soc.dtsi" > + > +/ { > + model = "Intel Thunder Bay Hybrid HDDL Prime Board"; > + compatible = "intel,thunderbay"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; Why do you have an alias to a disabled node? > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory@100A000000 { Lowercase hex on unit-addresses. > + device_type = "memory"; > + /* 8GB of DDR memory */ > + reg = <0x10 0x0A000000 0x2 0x0>; > + }; > + > + memory@1200000000 { > + device_type = "memory"; > + /* 4GB of DDR memory */ > + reg = <0x12 0x0 0x1 0x0>; > + }; > + > +}; > diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts > new file mode 100644 > index 0000000..01a3d4c > --- /dev/null > +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts > @@ -0,0 +1,43 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > +/* > + * Copyright (c) 2021 Intel Corporation. > + * > + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime configuration > + * board > + * > + * DDR 8GB + 4GB with vpu slice 0 and vpu slice 3 > + */ > + > +/dts-v1/; > + > +#include "thunderbay-soc.dtsi" > + > +/ { > + model = "Intel Thunder Bay Hybrid HDDL Prime Board"; > + compatible = "intel,thunderbay"; This should have a board specific compatible. Not sure if you need 1 or 4 though. If the VPU slice stuff is determined elsewhere then 1 is enough. > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory@100A000000 { > + device_type = "memory"; > + /* 8GB of DDR memory */ > + reg = <0x10 0x0A000000 0x2 0x0>; > + }; > + > + memory@1200000000 { > + device_type = "memory"; > + /* 4GB of DDR memory */ > + reg = <0x12 0x0 0x1 0x0>; > + }; > + > +}; > diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts > new file mode 100644 > index 0000000..e31db16 > --- /dev/null > +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts > @@ -0,0 +1,43 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > +/* > + * Copyright (c) 2021 Intel Corporation. > + * > + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime configuration > + * board > + * > + * DDR 8GB + 4GB with vpu slice 1 and vpu slice 2 > + */ > + > +/dts-v1/; > + > +#include "thunderbay-soc.dtsi" > + > +/ { > + model = "Intel Thunder Bay Hybrid HDDL Prime Board"; > + compatible = "intel,thunderbay"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory@100A000000 { > + device_type = "memory"; > + /* 8GB of DDR memory */ > + reg = <0x10 0x0A000000 0x2 0x0>; > + }; > + > + memory@1200000000 { > + device_type = "memory"; > + /* 4GB of DDR memory */ > + reg = <0x12 0x0 0x1 0x0>; > + }; > + > +}; > diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts > new file mode 100644 > index 0000000..6529664 > --- /dev/null > +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts > @@ -0,0 +1,43 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > +/* > + * Copyright (c) 2021 Intel Corporation. > + * > + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime configuration > + * board > + * > + * DDR 8GB + 4GB with vpu slice 1 and vpu slice 3 > + */ > + > +/dts-v1/; > + > +#include "thunderbay-soc.dtsi" > + > +/ { > + model = "Intel Thunder Bay Hybrid HDDL Prime Board"; > + compatible = "intel,thunderbay"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory@100A000000 { > + device_type = "memory"; > + /* 8GB of DDR memory */ > + reg = <0x10 0x0A000000 0x2 0x0>; > + }; > + > + memory@1200000000 { > + device_type = "memory"; > + /* 4GB of DDR memory */ > + reg = <0x12 0x0 0x1 0x0>; > + }; > + > +}; These all look the same, why do we need 4 copies? > diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts b/arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts > new file mode 100644 > index 0000000..561ecea > --- /dev/null > +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts > @@ -0,0 +1,54 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > +/* > + * Copyright (c) 2021 Intel Corporation. > + * > + * Device tree describing Intel Thunder Bay Hybrid HDDL Full configuration > + * board > + * > + * DDR 8GB + 8GB + 4GB + 4GB with four vpu slices > + */ > + > +/dts-v1/; > + > +#include "thunderbay-soc.dtsi" > + > +/ { > + model = "Intel Thunder Bay Hybrid HDDL Full Board"; > + compatible = "intel,thunderbay"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory@100A000000 { > + device_type = "memory"; > + /* 8GB of DDR memory */ > + reg = <0x10 0x0A000000 0x2 0x0>; > + }; > + > + memory@1200000000 { > + device_type = "memory"; > + /* 8GB of DDR memory */ > + reg = <0x12 0x0 0x2 0x0>; > + }; > + > + memory@1400000000 { > + device_type = "memory"; > + /* 4GB of DDR memory */ > + reg = <0x14 0x0 0x1 0x0>; > + }; > + > + memory@1500000000 { > + device_type = "memory"; > + /* 4GB of DDR memory */ > + reg = <0x15 0x0 0x1 0x0>; > + }; > +}; > diff --git a/arch/arm64/boot/dts/intel/thunderbay-soc.dtsi b/arch/arm64/boot/dts/intel/thunderbay-soc.dtsi > new file mode 100644 > index 0000000..834200d > --- /dev/null > +++ b/arch/arm64/boot/dts/intel/thunderbay-soc.dtsi > @@ -0,0 +1,243 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > +/* > + * Copyright (c) 2021 Intel Corporation. > + * > + * Device tree describing Thunder Bay SoC > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + > + compatible = "intel,thunderbay"; > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic>; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&CPU0>; > + }; > + core1 { > + cpu = <&CPU1>; > + }; > + core2 { > + cpu = <&CPU2>; > + }; > + core3 { > + cpu = <&CPU3>; > + }; > + }; > + cluster1 { > + core0 { > + cpu = <&CPU4>; > + }; > + core1 { > + cpu = <&CPU5>; > + }; > + core2 { > + cpu = <&CPU6>; > + }; > + core3 { > + cpu = <&CPU7>; > + }; > + }; > + cluster2 { > + core0 { > + cpu = <&CPU8>; > + }; > + core1 { > + cpu = <&CPU9>; > + }; > + core2 { > + cpu = <&CPU10>; > + }; > + core3 { > + cpu = <&CPU11>; > + }; > + }; > + cluster3 { > + core0 { > + cpu = <&CPU12>; > + }; > + core1 { > + cpu = <&CPU13>; > + }; > + core2 { > + cpu = <&CPU14>; > + }; > + core3 { > + cpu = <&CPU15>; > + }; > + }; > + }; > + > + CPU0: cpu@0 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + }; > + > + CPU1: cpu@1 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + }; > + > + CPU2: cpu@2 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + }; > + > + CPU3: cpu@3 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x3>; > + enable-method = "psci"; > + }; > + > + CPU4: cpu@100 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + }; > + > + CPU5: cpu@101 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x101>; > + enable-method = "psci"; > + }; > + > + CPU6: cpu@102 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x102>; > + enable-method = "psci"; > + }; > + > + CPU7: cpu@103 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x103>; > + enable-method = "psci"; > + }; > + > + CPU8: cpu@200 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x200>; > + enable-method = "psci"; > + }; > + > + CPU9: cpu@201 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x201>; > + enable-method = "psci"; > + }; > + > + CPU10: cpu@202 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x202>; > + enable-method = "psci"; > + }; > + > + CPU11: cpu@203 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x203>; > + enable-method = "psci"; > + }; > + > + CPU12: cpu@300 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x300>; > + enable-method = "psci"; > + }; > + > + CPU13: cpu@301 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x301>; > + enable-method = "psci"; > + }; > + > + CPU14: cpu@302 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x302>; > + enable-method = "psci"; > + }; > + > + CPU15: cpu@303 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0x0 0x303>; > + enable-method = "psci"; > + }; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; PSCI 1.0 has been out for 6 years... > + method = "smc"; > + }; > + > + gic: interrupt-controller@88400000 { > + compatible = "arm,gic-v3"; > + interrupt-controller; > + #interrupt-cells = <3>; > + reg = <0x0 0x88400000 0x0 0x200000>, /* GICD */ > + <0x0 0x88600000 0x0 0x200000>; /* GICR */ > + /* VGIC maintenance interrupt */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + /* Secure, non-secure, virtual, and hypervisor */ > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + dma-ranges; > + > + uart0: serial@80460000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x0 0x80460000 0x0 0x100>; > + interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>; > + clock-frequency = <50000000>; > + reg-shift = <2>; > + reg-io-width = <4>; > + }; > + > + uart1: serial@80470000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x0 0x80470000 0x0 0x100>; > + interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>; > + clock-frequency = <50000000>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + }; > +}; > -- > 2.7.4 > > ^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH V2 3/3] arm64: dts: add initial device tree for Thunder Bay SoC 2021-07-29 19:53 ` Rob Herring @ 2021-08-27 7:55 ` Demakkanavar, Kenchappa 0 siblings, 0 replies; 7+ messages in thread From: Demakkanavar, Kenchappa @ 2021-08-27 7:55 UTC (permalink / raw) To: Rob Herring Cc: will, linux-arm-kernel, linux-kernel, devicetree, dinguyen, Zhou, Furong, kris.pan, Pan, Kris, mgross, Gross, Mark Hi Rob, Thanks for your time in providing feedback. Please find my reply in-lined below. Thanks & Regards, Kenchappa S. D. > -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: Friday, July 30, 2021 1:23 AM > To: Demakkanavar, Kenchappa <kenchappa.demakkanavar@intel.com> > Cc: will@kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; devicetree@vger.kernel.org; dinguyen@kernel.org; > Zhou, Furong <furong.zhou@intel.com>; kris.pan@linux.intel.com; Pan, Kris > <kris.pan@intel.com>; mgross@linux.intel.com; Gross, Mark > <mark.gross@intel.com> > Subject: Re: [PATCH V2 3/3] arm64: dts: add initial device tree for Thunder Bay > SoC > > On Tue, Jul 20, 2021 at 10:52:49AM +0530, > kenchappa.demakkanavar@intel.com wrote: > > From: "Demakkanavar, Kenchappa" <kenchappa.demakkanavar@intel.com> > > > > Add initial device tree for Intel Movidius SoC code-named Thunder Bay. > > > > This initial DT includes nodes for 4 CPU clusters with 4 Cortex-A53 > > cores per cluster, UARTs, GIC, ARM Timer and PSCI. > > Make sure you run 'make dtbs_check' on these. Sure. Will post clean patches in next version. > > There shouldn't be any dtc warnings and or undocumented compatible warnings > at a minimum. Sure. Will post clean patches in next version. > > > thunderbay-soc.dtsi - Thunder Bay SoC dtsi file > > hddl_hybrid_4s.dts - Thunder Bay full configuration board dts > > with 4 VPU processors > > hddl_hybrid_2s_02.dts - Thunder Bay prime configuration board dts with > > 2 VPU processors (slice 0 and slice 2 enabled) > > hddl_hybrid_2s_03.dts - Thunder Bay prime configuration board dts with > > 2 VPU processors (slice 0 and slice 3 enabled) > > hddl_hybrid_2s_12.dts - Thunder Bay prime configuration board dts with > > 2 VPU processors (slice 1 and slice 2 enabled) > > hddl_hybrid_2s_13.dts - Thunder Bay prime configuration board dts with > > 2 VPU processors (slice 1 and slice 3 enabled) > > > > Signed-off-by: Demakkanavar, Kenchappa > > <kenchappa.demakkanavar@intel.com> > > --- > > MAINTAINERS | 2 + > > arch/arm64/boot/dts/intel/Makefile | 6 + > > arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts | 43 +++++ > > arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts | 43 +++++ > > arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts | 43 +++++ > > arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts | 43 +++++ > > arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts | 54 ++++++ > > arch/arm64/boot/dts/intel/thunderbay-soc.dtsi | 243 > ++++++++++++++++++++++++ > > 8 files changed, 477 insertions(+) > > create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts > > create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts > > create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts > > create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts > > create mode 100644 arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts > > create mode 100644 arch/arm64/boot/dts/intel/thunderbay-soc.dtsi > > > > diff --git a/MAINTAINERS b/MAINTAINERS index 041f9a0..68317f0 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -1996,6 +1996,8 @@ ARM/INTEL THUNDERBAY ARCHITECTURE > > M: Demakkanavar, Kenchappa <kenchappa.demakkanavar@intel.com> > > S: Maintained > > F: Documentation/devicetree/bindings/arm/intel,thunderbay.yaml > > +F: arch/arm64/boot/dts/intel/hddl* > > +F: arch/arm64/boot/dts/intel/thunderbay-soc.dtsi > > > > ARM/INTEL XSC3 (MANZANO) ARM CORE > > M: Lennert Buytenhek <kernel@wantstofly.org> > > diff --git a/arch/arm64/boot/dts/intel/Makefile > > b/arch/arm64/boot/dts/intel/Makefile > > index 0b54774..767b74b 100644 > > --- a/arch/arm64/boot/dts/intel/Makefile > > +++ b/arch/arm64/boot/dts/intel/Makefile > > @@ -3,3 +3,9 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += > socfpga_agilex_socdk.dtb \ > > socfpga_agilex_socdk_nand.dtb \ > > socfpga_n5x_socdk.dtb > > dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb > > + > > +dtb-$(CONFIG_ARCH_THUNDERBAY) += hddl_hybrid_4s.dtb \ > > + hddl_hybrid_2s_02.dtb \ > > + hddl_hybrid_2s_03.dtb \ > > + hddl_hybrid_2s_12.dtb \ > > + hddl_hybrid_2s_13.dtb > > diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts > > b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts > > new file mode 100644 > > index 0000000..f907ddd > > --- /dev/null > > +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_02.dts > > @@ -0,0 +1,43 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > > +/* > > + * Copyright (c) 2021 Intel Corporation. > > + * > > + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime > > +configuration > > + * board. > > + * > > + * DDR 8GB + 4GB with vpu slice 0 and vpu slice 2 */ > > + > > +/dts-v1/; > > + > > +#include "thunderbay-soc.dtsi" > > + > > +/ { > > + model = "Intel Thunder Bay Hybrid HDDL Prime Board"; > > + compatible = "intel,thunderbay"; > > + > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + aliases { > > + serial0 = &uart0; > > + serial1 = &uart1; > > Why do you have an alias to a disabled node? Ok. Will remove this. > > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > + > > + memory@100A000000 { > > Lowercase hex on unit-addresses. Ok. > > > + device_type = "memory"; > > + /* 8GB of DDR memory */ > > + reg = <0x10 0x0A000000 0x2 0x0>; > > + }; > > + > > + memory@1200000000 { > > + device_type = "memory"; > > + /* 4GB of DDR memory */ > > + reg = <0x12 0x0 0x1 0x0>; > > + }; > > + > > +}; > > diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts > > b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts > > new file mode 100644 > > index 0000000..01a3d4c > > --- /dev/null > > +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_03.dts > > @@ -0,0 +1,43 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > > +/* > > + * Copyright (c) 2021 Intel Corporation. > > + * > > + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime > > +configuration > > + * board > > + * > > + * DDR 8GB + 4GB with vpu slice 0 and vpu slice 3 */ > > + > > +/dts-v1/; > > + > > +#include "thunderbay-soc.dtsi" > > + > > +/ { > > + model = "Intel Thunder Bay Hybrid HDDL Prime Board"; > > + compatible = "intel,thunderbay"; > > This should have a board specific compatible. Not sure if you need 1 or > 4 though. If the VPU slice stuff is determined elsewhere then 1 is enough. Since minimum dts will boot for both 4 slice VPU SoC and 2 slice VPU SoC, I will start with single compatible string now. Also minimum dts for 2 VPU slices are same, I will submit common single dts for 2 VPU slice boards in next version. > > > + > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + aliases { > > + serial0 = &uart0; > > + serial1 = &uart1; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > + > > + memory@100A000000 { > > + device_type = "memory"; > > + /* 8GB of DDR memory */ > > + reg = <0x10 0x0A000000 0x2 0x0>; > > + }; > > + > > + memory@1200000000 { > > + device_type = "memory"; > > + /* 4GB of DDR memory */ > > + reg = <0x12 0x0 0x1 0x0>; > > + }; > > + > > +}; > > diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts > > b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts > > new file mode 100644 > > index 0000000..e31db16 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_12.dts > > @@ -0,0 +1,43 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > > +/* > > + * Copyright (c) 2021 Intel Corporation. > > + * > > + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime > > +configuration > > + * board > > + * > > + * DDR 8GB + 4GB with vpu slice 1 and vpu slice 2 */ > > + > > +/dts-v1/; > > + > > +#include "thunderbay-soc.dtsi" > > + > > +/ { > > + model = "Intel Thunder Bay Hybrid HDDL Prime Board"; > > + compatible = "intel,thunderbay"; > > + > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + aliases { > > + serial0 = &uart0; > > + serial1 = &uart1; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > + > > + memory@100A000000 { > > + device_type = "memory"; > > + /* 8GB of DDR memory */ > > + reg = <0x10 0x0A000000 0x2 0x0>; > > + }; > > + > > + memory@1200000000 { > > + device_type = "memory"; > > + /* 4GB of DDR memory */ > > + reg = <0x12 0x0 0x1 0x0>; > > + }; > > + > > +}; > > diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts > > b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts > > new file mode 100644 > > index 0000000..6529664 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_2s_13.dts > > @@ -0,0 +1,43 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > > +/* > > + * Copyright (c) 2021 Intel Corporation. > > + * > > + * Device tree describing Intel Thunder Bay Hybrid HDDL Prime > > +configuration > > + * board > > + * > > + * DDR 8GB + 4GB with vpu slice 1 and vpu slice 3 */ > > + > > +/dts-v1/; > > + > > +#include "thunderbay-soc.dtsi" > > + > > +/ { > > + model = "Intel Thunder Bay Hybrid HDDL Prime Board"; > > + compatible = "intel,thunderbay"; > > + > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + aliases { > > + serial0 = &uart0; > > + serial1 = &uart1; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > + > > + memory@100A000000 { > > + device_type = "memory"; > > + /* 8GB of DDR memory */ > > + reg = <0x10 0x0A000000 0x2 0x0>; > > + }; > > + > > + memory@1200000000 { > > + device_type = "memory"; > > + /* 4GB of DDR memory */ > > + reg = <0x12 0x0 0x1 0x0>; > > + }; > > + > > +}; > > These all look the same, why do we need 4 copies? Full dts will have VPU slice specific dts nodes. Since minimum dts for 2 VPU slices are same, I will submit common single dts for 2 VPU slice boards in next version. > > > diff --git a/arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts > > b/arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts > > new file mode 100644 > > index 0000000..561ecea > > --- /dev/null > > +++ b/arch/arm64/boot/dts/intel/hddl_hybrid_4s.dts > > @@ -0,0 +1,54 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > > +/* > > + * Copyright (c) 2021 Intel Corporation. > > + * > > + * Device tree describing Intel Thunder Bay Hybrid HDDL Full > > +configuration > > + * board > > + * > > + * DDR 8GB + 8GB + 4GB + 4GB with four vpu slices */ > > + > > +/dts-v1/; > > + > > +#include "thunderbay-soc.dtsi" > > + > > +/ { > > + model = "Intel Thunder Bay Hybrid HDDL Full Board"; > > + compatible = "intel,thunderbay"; > > + > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + aliases { > > + serial0 = &uart0; > > + serial1 = &uart1; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > + > > + memory@100A000000 { > > + device_type = "memory"; > > + /* 8GB of DDR memory */ > > + reg = <0x10 0x0A000000 0x2 0x0>; > > + }; > > + > > + memory@1200000000 { > > + device_type = "memory"; > > + /* 8GB of DDR memory */ > > + reg = <0x12 0x0 0x2 0x0>; > > + }; > > + > > + memory@1400000000 { > > + device_type = "memory"; > > + /* 4GB of DDR memory */ > > + reg = <0x14 0x0 0x1 0x0>; > > + }; > > + > > + memory@1500000000 { > > + device_type = "memory"; > > + /* 4GB of DDR memory */ > > + reg = <0x15 0x0 0x1 0x0>; > > + }; > > +}; > > diff --git a/arch/arm64/boot/dts/intel/thunderbay-soc.dtsi > > b/arch/arm64/boot/dts/intel/thunderbay-soc.dtsi > > new file mode 100644 > > index 0000000..834200d > > --- /dev/null > > +++ b/arch/arm64/boot/dts/intel/thunderbay-soc.dtsi > > @@ -0,0 +1,243 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) > > +/* > > + * Copyright (c) 2021 Intel Corporation. > > + * > > + * Device tree describing Thunder Bay SoC */ > > + > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > +/ { > > + > > + compatible = "intel,thunderbay"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + interrupt-parent = <&gic>; > > + > > + cpus { > > + #address-cells = <2>; > > + #size-cells = <0>; > > + > > + cpu-map { > > + cluster0 { > > + core0 { > > + cpu = <&CPU0>; > > + }; > > + core1 { > > + cpu = <&CPU1>; > > + }; > > + core2 { > > + cpu = <&CPU2>; > > + }; > > + core3 { > > + cpu = <&CPU3>; > > + }; > > + }; > > + cluster1 { > > + core0 { > > + cpu = <&CPU4>; > > + }; > > + core1 { > > + cpu = <&CPU5>; > > + }; > > + core2 { > > + cpu = <&CPU6>; > > + }; > > + core3 { > > + cpu = <&CPU7>; > > + }; > > + }; > > + cluster2 { > > + core0 { > > + cpu = <&CPU8>; > > + }; > > + core1 { > > + cpu = <&CPU9>; > > + }; > > + core2 { > > + cpu = <&CPU10>; > > + }; > > + core3 { > > + cpu = <&CPU11>; > > + }; > > + }; > > + cluster3 { > > + core0 { > > + cpu = <&CPU12>; > > + }; > > + core1 { > > + cpu = <&CPU13>; > > + }; > > + core2 { > > + cpu = <&CPU14>; > > + }; > > + core3 { > > + cpu = <&CPU15>; > > + }; > > + }; > > + }; > > + > > + CPU0: cpu@0 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x0>; > > + enable-method = "psci"; > > + }; > > + > > + CPU1: cpu@1 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x1>; > > + enable-method = "psci"; > > + }; > > + > > + CPU2: cpu@2 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x2>; > > + enable-method = "psci"; > > + }; > > + > > + CPU3: cpu@3 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x3>; > > + enable-method = "psci"; > > + }; > > + > > + CPU4: cpu@100 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x100>; > > + enable-method = "psci"; > > + }; > > + > > + CPU5: cpu@101 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x101>; > > + enable-method = "psci"; > > + }; > > + > > + CPU6: cpu@102 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x102>; > > + enable-method = "psci"; > > + }; > > + > > + CPU7: cpu@103 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x103>; > > + enable-method = "psci"; > > + }; > > + > > + CPU8: cpu@200 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x200>; > > + enable-method = "psci"; > > + }; > > + > > + CPU9: cpu@201 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x201>; > > + enable-method = "psci"; > > + }; > > + > > + CPU10: cpu@202 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x202>; > > + enable-method = "psci"; > > + }; > > + > > + CPU11: cpu@203 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x203>; > > + enable-method = "psci"; > > + }; > > + > > + CPU12: cpu@300 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x300>; > > + enable-method = "psci"; > > + }; > > + > > + CPU13: cpu@301 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x301>; > > + enable-method = "psci"; > > + }; > > + > > + CPU14: cpu@302 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x302>; > > + enable-method = "psci"; > > + }; > > + > > + CPU15: cpu@303 { > > + compatible = "arm,cortex-a53"; > > + device_type = "cpu"; > > + reg = <0x0 0x303>; > > + enable-method = "psci"; > > + }; > > + }; > > + > > + psci { > > + compatible = "arm,psci-0.2"; > > PSCI 1.0 has been out for 6 years... I will update this after verifying our ATF supported PSCI version > > > + method = "smc"; > > + }; > > + > > + gic: interrupt-controller@88400000 { > > + compatible = "arm,gic-v3"; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + reg = <0x0 0x88400000 0x0 0x200000>, /* GICD */ > > + <0x0 0x88600000 0x0 0x200000>; /* GICR */ > > + /* VGIC maintenance interrupt */ > > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + /* Secure, non-secure, virtual, and hypervisor */ > > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + dma-ranges; > > + > > + uart0: serial@80460000 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0x0 0x80460000 0x0 0x100>; > > + interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>; > > + clock-frequency = <50000000>; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + }; > > + > > + uart1: serial@80470000 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0x0 0x80470000 0x0 0x100>; > > + interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>; > > + clock-frequency = <50000000>; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + status = "disabled"; > > + }; > > + }; > > +}; > > -- > > 2.7.4 > > > > ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-08-27 7:55 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-07-20 5:22 [PATCH V2 0/3] Add initial Thunder Bay SoC / Board support kenchappa.demakkanavar 2021-07-20 5:22 ` [PATCH V2 1/3] arm64: Add config for Thunder Bay SoC kenchappa.demakkanavar 2021-07-20 5:22 ` [PATCH V2 2/3] dt-bindings: arm: Add Thunder Bay bindings kenchappa.demakkanavar 2021-07-29 19:40 ` Rob Herring 2021-07-20 5:22 ` [PATCH V2 3/3] arm64: dts: add initial device tree for Thunder Bay SoC kenchappa.demakkanavar 2021-07-29 19:53 ` Rob Herring 2021-08-27 7:55 ` Demakkanavar, Kenchappa
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