From: "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>
To: sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org,
paul@crapouillou.net
Cc: linux-clk@vger.kernel.org, linux-mips@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com,
rick.tyliu@ingenic.com, sihui.liu@ingenic.com,
jun.jiang@ingenic.com, sernia.zhou@foxmail.com
Subject: [PATCH v7 01/11] clk: JZ4780: Add function for disable the second core.
Date: Sat, 24 Jul 2021 17:34:36 +0800 [thread overview]
Message-ID: <1627119286-125821-2-git-send-email-zhouyanjie@wanyeetech.com> (raw)
In-Reply-To: <1627119286-125821-1-git-send-email-zhouyanjie@wanyeetech.com>
Add "jz4780_core1_disable()" for disable the second core of JZ4780,
prepare for later commits.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
---
Notes:
v1->v2:
Add Paul Cercueil's Reviewed-by.
v2->v3:
No change.
v3->v4:
No change.
v4->v5:
No change.
v5->v6:
No change.
v6->v7:
No change.
drivers/clk/ingenic/jz4780-cgu.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index 0268d23..dcca74e 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -252,8 +252,29 @@ static int jz4780_core1_enable(struct clk_hw *hw)
return 0;
}
+static void jz4780_core1_disable(struct clk_hw *hw)
+{
+ struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
+ struct ingenic_cgu *cgu = ingenic_clk->cgu;
+ unsigned long flags;
+ u32 lcr, clkgr1;
+
+ spin_lock_irqsave(&cgu->lock, flags);
+
+ lcr = readl(cgu->base + CGU_REG_LCR);
+ lcr |= LCR_PD_SCPU;
+ writel(lcr, cgu->base + CGU_REG_LCR);
+
+ clkgr1 = readl(cgu->base + CGU_REG_CLKGR1);
+ clkgr1 |= CLKGR1_CORE1;
+ writel(clkgr1, cgu->base + CGU_REG_CLKGR1);
+
+ spin_unlock_irqrestore(&cgu->lock, flags);
+}
+
static const struct clk_ops jz4780_core1_ops = {
.enable = jz4780_core1_enable,
+ .disable = jz4780_core1_disable,
};
static const s8 pll_od_encoding[16] = {
--
2.7.4
next prev parent reply other threads:[~2021-07-24 9:35 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-24 9:34 [PATCH v7 00/11] Add new clocks and fix bugs for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-07-24 9:34 ` 周琰杰 (Zhou Yanjie) [this message]
2021-07-24 9:34 ` [PATCH v7 02/11] clk: Ingenic: Adjust cgu code to make it compatible with I2S PLL 周琰杰 (Zhou Yanjie)
2021-08-19 9:37 ` Paul Cercueil
2021-08-27 17:46 ` Zhou Yanjie
2021-07-24 9:34 ` [PATCH v7 03/11] dt-bindings: clock: Add missing clocks for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-07-24 9:34 ` [PATCH v7 04/11] clk: Ingenic: Fix problem of MAC clock in Ingenic X1000 and X1830 周琰杰 (Zhou Yanjie)
2021-08-19 9:39 ` Paul Cercueil
2021-07-24 9:34 ` [PATCH v7 05/11] clk: Ingenic: Add missing clocks for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-07-24 9:34 ` [PATCH v7 06/11] clk: Ingenic: Clean up and reformat the code 周琰杰 (Zhou Yanjie)
2021-08-19 9:46 ` Paul Cercueil
2021-08-27 17:47 ` Zhou Yanjie
2021-07-24 9:34 ` [PATCH v7 07/11] dt-bindings: clock: Add documentation for JZ4775 and X2000 bindings 周琰杰 (Zhou Yanjie)
2021-07-24 9:34 ` [PATCH v7 08/11] dt-bindings: clock: Add JZ4775 clock bindings 周琰杰 (Zhou Yanjie)
2021-07-26 22:18 ` Rob Herring
2021-08-19 9:47 ` Paul Cercueil
2021-07-24 9:34 ` [PATCH v7 09/11] dt-bindings: clock: Add X2000 " 周琰杰 (Zhou Yanjie)
2021-07-26 22:19 ` Rob Herring
2021-08-19 9:48 ` Paul Cercueil
2021-07-24 9:34 ` [PATCH v7 10/11] clk: Ingenic: Add CGU driver for JZ4775 周琰杰 (Zhou Yanjie)
2021-07-24 9:34 ` [PATCH v7 11/11] clk: Ingenic: Add CGU driver for X2000 周琰杰 (Zhou Yanjie)
2021-08-19 6:44 ` [PATCH v7 00/11] Add new clocks and fix bugs for Ingenic SoCs Zhou Yanjie
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