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From: Sibi Sankar <sibis@codeaurora.org>
To: sboyd@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org,
	mka@chromium.org
Cc: viresh.kumar@linaro.org, agross@kernel.org, rjw@rjwysocki.net,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
	dianders@chromium.org, tdas@codeaurora.org,
	Sibi Sankar <sibis@codeaurora.org>
Subject: [PATCH 0/4] Fixup register offsets to support per core L3 DCVS
Date: Thu, 29 Jul 2021 23:34:41 +0530	[thread overview]
Message-ID: <1627581885-32165-1-git-send-email-sibis@codeaurora.org> (raw)

Qualcomm SoCs (starting with SM8350) support per core voting for L3 cache
frequency. The patch series re-arranges the cpufreq register offsets to
allow access for the L3 interconnect to implement per core control i.e.
the first 0x100 is now accessed by the L3 interconnect driver instead.

L3 interconnect provider node on SC7280 SoC:
epss_l3: interconnect@18590000 {
	compatible = "qcom,sc7280-epss-l3";
        reg = <0 0x18590000 0 0x1000>, <0 0x18591000 0 0x100>,
	      <0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>;
	...
};

CPUFREQ node on SC7280 SoC:
cpufreq_hw: cpufreq@18591000 {
	compatible = "qcom,cpufreq-epss";
	reg = <0 0x18591100 0 0x900>,
	      <0 0x18592100 0 0x900>,
	      <0 0x18593100 0 0x900>;
	...
};

The patch series also prevents binding breakage by using the
SM8250/SM8350 EPSS compatible.

Sibi Sankar (4):
  dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350
  cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS
  arm64: dts: qcom: sc7280: Fixup the cpufreq node
  arm64: dts: qcom: sm8350: Fixup the cpufreq node

 .../bindings/cpufreq/cpufreq-qcom-hw.txt           |  6 +++++-
 arch/arm64/boot/dts/qcom/sc7280.dtsi               |  6 +++---
 arch/arm64/boot/dts/qcom/sm8350.dtsi               |  9 ++++-----
 drivers/cpufreq/qcom-cpufreq-hw.c                  | 23 ++++++++++++++++++----
 4 files changed, 31 insertions(+), 13 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


             reply	other threads:[~2021-07-29 18:05 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-29 18:04 Sibi Sankar [this message]
2021-07-29 18:04 ` [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350 Sibi Sankar
2021-08-03 19:23   ` Rob Herring
2021-08-04 18:56   ` Stephen Boyd
2021-07-29 18:04 ` [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS Sibi Sankar
2021-08-04 19:01   ` Stephen Boyd
2021-08-05 17:47     ` Sibi Sankar
2021-08-05 18:25       ` Stephen Boyd
2021-08-06  6:42         ` Sibi Sankar
2021-08-04 23:11   ` Bjorn Andersson
2021-08-04 23:20     ` Bjorn Andersson
2021-07-29 18:04 ` [PATCH 3/4] arm64: dts: qcom: sc7280: Fixup the cpufreq node Sibi Sankar
2021-08-04 18:57   ` Stephen Boyd
2021-08-31 15:30   ` Matthias Kaehlcke
2021-08-31 17:04     ` Bjorn Andersson
2021-09-06  3:20       ` Sibi Sankar
2021-09-07 19:14         ` Doug Anderson
2021-07-29 18:04 ` [PATCH 4/4] arm64: dts: qcom: sm8350: " Sibi Sankar
2021-08-04 22:59   ` Bjorn Andersson
2021-08-04 23:58     ` Matthias Kaehlcke
2021-08-30  6:47       ` Sibi Sankar

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