From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D50CC432BE for ; Thu, 29 Jul 2021 18:05:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 88F586054E for ; Thu, 29 Jul 2021 18:05:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232030AbhG2SFn (ORCPT ); Thu, 29 Jul 2021 14:05:43 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:32051 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231816AbhG2SFk (ORCPT ); Thu, 29 Jul 2021 14:05:40 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1627581937; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=ftwcXvxs2q2J5gUs8pkqXIhBDrujiscNrQ/zdQQCG7s=; b=rXP+GJmedcLQ3VxLZzf7YKoF9RES3w/qihEoP03F4dBvjdfh9C7VDAFq21MEngfuANs0/ASD gd27fHjoL4XpYa5ZFI+E4kJPdBFqJxu8Gbvl04Ua9stW5EO4fMIk60pPmG2GRTWyiQqu9anc R3CTerIEWRLtCsnFwhFlZ+kJ8Hk= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n04.prod.us-east-1.postgun.com with SMTP id 6102edd6b653fbdadd3ccdd0 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 29 Jul 2021 18:05:10 GMT Sender: sibis=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id DD695C4338A; Thu, 29 Jul 2021 18:05:09 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 34D05C4338A; Thu, 29 Jul 2021 18:05:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 34D05C4338A Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: sboyd@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, mka@chromium.org Cc: viresh.kumar@linaro.org, agross@kernel.org, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, tdas@codeaurora.org, Sibi Sankar Subject: [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS Date: Thu, 29 Jul 2021 23:34:43 +0530 Message-Id: <1627581885-32165-3-git-send-email-sibis@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1627581885-32165-1-git-send-email-sibis@codeaurora.org> References: <1627581885-32165-1-git-send-email-sibis@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Qualcomm SoCs (starting with SM8350) support per core voting for L3 cache frequency. So, re-arrange the cpufreq register offsets to allow access for the L3 interconnect to implement per core control. Also prevent binding breakage caused by register offset shuffling by using the SM8250/SM8350 EPSS compatible. Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node") Signed-off-by: Sibi Sankar --- drivers/cpufreq/qcom-cpufreq-hw.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index f86859bf76f1..74ef3b38343b 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -28,6 +28,7 @@ struct qcom_cpufreq_soc_data { u32 reg_volt_lut; u32 reg_perf_state; u8 lut_row_size; + bool skip_enable; }; struct qcom_cpufreq_data { @@ -257,19 +258,31 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = { .reg_volt_lut = 0x114, .reg_perf_state = 0x920, .lut_row_size = 32, + .skip_enable = false, }; static const struct qcom_cpufreq_soc_data epss_soc_data = { + .reg_freq_lut = 0x0, + .reg_volt_lut = 0x100, + .reg_perf_state = 0x220, + .lut_row_size = 4, + .skip_enable = true, +}; + +static const struct qcom_cpufreq_soc_data epss_sm8250_soc_data = { .reg_enable = 0x0, .reg_freq_lut = 0x100, .reg_volt_lut = 0x200, .reg_perf_state = 0x320, .lut_row_size = 4, + .skip_enable = false, }; static const struct of_device_id qcom_cpufreq_hw_match[] = { { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data }, + { .compatible = "qcom,sm8250-cpufreq-epss", .data = &epss_sm8250_soc_data }, + { .compatible = "qcom,sm8350-cpufreq-epss", .data = &epss_sm8250_soc_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); @@ -334,10 +347,12 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) data->res = res; /* HW should be in enabled state to proceed */ - if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) { - dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); - ret = -ENODEV; - goto error; + if (!data->soc_data->skip_enable) { + if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) { + dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); + ret = -ENODEV; + goto error; + } } qcom_get_related_cpus(index, policy->cpus); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project