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From: Rajendra Nayak <rnayak@codeaurora.org>
To: agross@kernel.org, bjorn.andersson@linaro.org,
	srinivas.kandagatla@linaro.org, robh+dt@kernel.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, rbokka@codeaurora.org,
	dianders@chromium.org, Rajendra Nayak <rnayak@codeaurora.org>
Subject: [PATCH v3 2/4] nvmem: qfprom: Fix up qfprom_disable_fuse_blowing() ordering
Date: Fri, 30 Jul 2021 12:16:11 +0530	[thread overview]
Message-ID: <1627627573-32454-3-git-send-email-rnayak@codeaurora.org> (raw)
In-Reply-To: <1627627573-32454-1-git-send-email-rnayak@codeaurora.org>

qfprom_disable_fuse_blowing() disables a bunch of resources,
and then does a few register writes in the 'conf' address
space.
It works perhaps because the resources are needed only for the
'raw' register space writes, and that the 'conf' space allows
read/writes regardless.
However that makes the code look confusing, so just move the
register writes before turning off the resources in the
function.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 drivers/nvmem/qfprom.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c
index 81fbad5..b0ca4c6 100644
--- a/drivers/nvmem/qfprom.c
+++ b/drivers/nvmem/qfprom.c
@@ -139,6 +139,9 @@ static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv,
 {
 	int ret;
 
+	writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
+	writel(old->accel_val, priv->qfpconf + QFPROM_ACCEL_OFFSET);
+
 	/*
 	 * This may be a shared rail and may be able to run at a lower rate
 	 * when we're not blowing fuses.  At the moment, the regulator framework
@@ -159,9 +162,6 @@ static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv,
 			 "Failed to set clock rate for disable (ignoring)\n");
 
 	clk_disable_unprepare(priv->secclk);
-
-	writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
-	writel(old->accel_val, priv->qfpconf + QFPROM_ACCEL_OFFSET);
 }
 
 /**
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


  parent reply	other threads:[~2021-07-30  6:46 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-30  6:46 [PATCH v3 0/4] nvmem: qfprom: Add binding updates and power-domain handling Rajendra Nayak
2021-07-30  6:46 ` [PATCH v3 1/4] dt-bindings: nvmem: qfprom: Add optional power-domains property Rajendra Nayak
2021-08-03 19:38   ` Rob Herring
2021-07-30  6:46 ` Rajendra Nayak [this message]
2021-07-30 13:49   ` [PATCH v3 2/4] nvmem: qfprom: Fix up qfprom_disable_fuse_blowing() ordering Doug Anderson
2021-07-30  6:46 ` [PATCH v3 3/4] nvmem: qfprom: sc7280: Handle the additional power-domains vote Rajendra Nayak
2021-07-30  6:46 ` [PATCH v3 4/4] arm64: dts: qcom: sc7280: Add qfprom node Rajendra Nayak
2021-08-04  8:29 ` [PATCH v3 0/4] nvmem: qfprom: Add binding updates and power-domain handling Srinivas Kandagatla

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